From 973077704469369a77ed84c8ff388edfe097a55c Mon Sep 17 00:00:00 2001
From: Clark Coleman <clc@zephyr-software.com>
Date: Mon, 22 Mar 2021 14:38:24 -0400
Subject: [PATCH] Handle new opcodes from IDA Pro 7.5.
---
include/interfaces/STARSTypes.h | 41 +++++++++++++++++++++++++
src/base/SMPInstr.cpp | 54 +++++++++++++++++++++++++++++++--
2 files changed, 92 insertions(+), 3 deletions(-)
diff --git a/include/interfaces/STARSTypes.h b/include/interfaces/STARSTypes.h
index 0510fbcc..a6d9c91e 100644
--- a/include/interfaces/STARSTypes.h
+++ b/include/interfaces/STARSTypes.h
@@ -120,6 +120,7 @@ struct SMP_bounds_t {
struct SwitchTableInfo { // info about a switch table
STARS_ea_t DefaultJumpAddr; // address of jump to default case; precedes indirect jump; STARS_BADADDR if no default
+ // NOTE: Weakness of IDA Pro is that it does not consider that there might be more than one branch to the default case.
int DefaultCaseBlockNum; // block number of default case, which is the target of the default jump; could also be in CaseBlockNums
int IndirJumpBlockNum; // block number with the INDIR_JUMP at the end
int IDomBlockNum; // Block that is the immediate dominator of all blocks in the switch statement
@@ -2434,6 +2435,46 @@ enum
STARS_NN_endbr64, // Terminate an Indirect Branch in 64-bit Mode
STARS_NN_endbr32, // Terminate an Indirect Branch in 32-bit and Compatibility Mode
+ // Undefined Instruction
+
+ STARS_NN_ud0, // Undefined Instruction
+ STARS_NN_ud1, // Undefined Instruction
+
+ // Enqueue Stores
+
+ STARS_NN_enqcmd, // Enqueue Command
+ STARS_NN_enqcmds, // Enqueue Command Supervisor
+
+ // AMD Zen2
+
+ STARS_NN_mcommit, // Commit Stores to Memory
+ STARS_NN_rdpru, // Read Processor Register
+
+ // Intel Tremont instructions
+
+ STARS_NN_cldemote, // Cache Line Demote
+ STARS_NN_enclv, // Execute an Enclave VMM Function of Specified Leaf Number
+
+ // Direct Stores
+
+ STARS_NN_movdiri, // Move Doubleword as Direct Store
+ STARS_NN_movdir64b, // Move 64 Bytes as Direct Store
+
+ // Intel WAITPKG instructions
+
+ STARS_NN_tpause, // Timed PAUSE
+ STARS_NN_umonitor, // User Level Set Up Monitor Address
+ STARS_NN_umwait, // User Level Monitor Wait
+
+ // Intel Sapphire Rapids instructions
+
+ STARS_NN_serialize, // Serialize Instruction Execution
+
+ // Intel TSX
+
+ STARS_NN_xresldtrk, // Resume Tracking Load Addresses
+ STARS_NN_xsusldtrk, // Suspend Tracking Load Addresses
+
STARS_NN_last,
diff --git a/src/base/SMPInstr.cpp b/src/base/SMPInstr.cpp
index 20fdafd6..9c6f0a2b 100644
--- a/src/base/SMPInstr.cpp
+++ b/src/base/SMPInstr.cpp
@@ -26307,8 +26307,8 @@ bool SMPInstr::BuildX86RTL(void)
return this->BuildBinary3OpndRTL(SMP_COMPARE_GT_AND_SET);
break;
- case STARS_NN_vcmptruess: // Scalar Single-FP Compare - True (unordered: non-signaling)
- return true;
+ case STARS_NN_vcmptruess: // Pseudo-op: Scalar Single-FP Compare - True (unordered: non-signaling)
+ return false;
break;
case STARS_NN_vcmpeq_osss: // Scalar Single-FP Compare - Equal (ordered: signaling)
@@ -26931,8 +26931,56 @@ bool SMPInstr::BuildX86RTL(void)
return false;
break;
+ // Undefined Instruction
+
+ case STARS_NN_ud0: // Undefined Instruction
+ case STARS_NN_ud1: // Undefined Instruction
+ NopRT = new SMPRegTransfer;
+ NopRT->SetParentInst(this);
+ NopRT->SetOperator(SMP_NULL_OPERATOR);
+ this->RTL.push_back(NopRT);
+ NopRT = nullptr;
+ return true;
+
+ // Enqueue Stores
+
+ case STARS_NN_enqcmd: // Enqueue Command
+ case STARS_NN_enqcmds: // Enqueue Command Supervisor
+
+ // AMD Zen2
+
+ case STARS_NN_mcommit: // Commit Stores to Memory
+ case STARS_NN_rdpru: // Read Processor Register
+
+ // Intel Tremont instructions
+
+ case STARS_NN_cldemote: // Cache Line Demote
+ case STARS_NN_enclv: // Execute an Enclave VMM Function of Specified Leaf Number
+
+ // Direct Stores
+
+ case STARS_NN_movdiri: // Move Doubleword as Direct Store
+ case STARS_NN_movdir64b: // Move 64 Bytes as Direct Store
+
+ // Intel WAITPKG instructions
+
+ case STARS_NN_tpause: // Timed PAUSE
+ case STARS_NN_umonitor: // User Level Set Up Monitor Address
+ case STARS_NN_umwait: // User Level Monitor Wait
+
+ // Intel Sapphire Rapids instructions
+
+ case STARS_NN_serialize: // Serialize Instruction Execution
+
+ // Intel TSX
+
+ case STARS_NN_xresldtrk: // Resume Tracking Load Addresses
+ case STARS_NN_xsusldtrk: // Suspend Tracking Load Addresses
+ return false;
+ break;
+
default:
- SMP_msg("ERROR: Unknown instruction opcode at %llx : %s\n", (unsigned long long) this->GetAddr(),
+ SMP_msg("ERROR: Unknown instruction opcode at %llx : %s\n", (uint64_t) this->GetAddr(),
DisAsmText.GetDisAsm(this->GetAddr()));
return false;
break;
--
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