From c9d9744d10910982b75ecc188655b54dfdb002f1 Mon Sep 17 00:00:00 2001
From: clc5q <clc5q@git.zephyr-software.com>
Date: Fri, 11 Apr 2008 17:45:22 +0000
Subject: [PATCH] Move conditional moves from type category 12 to 0; most of
category 15 to 14 (FP with MemSrc possible but not MemDest).
---
SMPDataFlowAnalysis.cpp | 443 ++++++++++++++++++++--------------------
1 file changed, 222 insertions(+), 221 deletions(-)
diff --git a/SMPDataFlowAnalysis.cpp b/SMPDataFlowAnalysis.cpp
index ca63a9d0..cb8216ff 100644
--- a/SMPDataFlowAnalysis.cpp
+++ b/SMPDataFlowAnalysis.cpp
@@ -1666,10 +1666,11 @@ void InitTypeCategory(void) {
// Category 13 instructions imply that their memory destination is 'n'.
// Category 14 instructions imply that their reg or memory source operand is 'n';
// if source is not memory, they are category 1 (inferences, but no instrumentation).
+ // There should never be a memory destination (usual destination is fpreg or flags).
// Category 15 instructions always have 'n' source AND destination operands;
- // if addressed using indexed addressing, they are a subset of category 0
- // (must be instrumented by mmStrata to keep index in bounds), else they are
- // a subset of category 14 (numeric memory source if any, no instrumentation).
+ // if addressed using indirect or indexed addressing, they are a subset of category 0
+ // (must be instrumented by mmStrata to keep index in bounds). Memory destinations
+ // are common in this category.
// NOTE: The Memory Monitor SDT needs just three categories, corresponding
// to categories 0, 1, and all others. For all categories > 1, the
@@ -1923,22 +1924,22 @@ SMPTypeCategory[NN_rsm] = 1; // Resume from System Management Mo
// Pentium Pro instructions
//
-SMPTypeCategory[NN_cmova] = 12; // Move if Above (CF=0 & ZF=0)
-SMPTypeCategory[NN_cmovb] = 12; // Move if Below (CF=1)
-SMPTypeCategory[NN_cmovbe] = 12; // Move if Below or Equal (CF=1 | ZF=1)
-SMPTypeCategory[NN_cmovg] = 12; // Move if Greater (ZF=0 & SF=OF)
-SMPTypeCategory[NN_cmovge] = 12; // Move if Greater or Equal (SF=OF)
-SMPTypeCategory[NN_cmovl] = 12; // Move if Less (SF!=OF)
-SMPTypeCategory[NN_cmovle] = 12; // Move if Less or Equal (ZF=1 | SF!=OF)
-SMPTypeCategory[NN_cmovnb] = 12; // Move if Not Below (CF=0)
-SMPTypeCategory[NN_cmovno] = 12; // Move if Not Overflow (OF=0)
-SMPTypeCategory[NN_cmovnp] = 12; // Move if Not Parity (PF=0)
-SMPTypeCategory[NN_cmovns] = 12; // Move if Not Sign (SF=0)
-SMPTypeCategory[NN_cmovnz] = 12; // Move if Not Zero (ZF=0)
-SMPTypeCategory[NN_cmovo] = 12; // Move if Overflow (OF=1)
-SMPTypeCategory[NN_cmovp] = 12; // Move if Parity (PF=1)
-SMPTypeCategory[NN_cmovs] = 12; // Move if Sign (SF=1)
-SMPTypeCategory[NN_cmovz] = 12; // Move if Zero (ZF=1)
+SMPTypeCategory[NN_cmova] = 0; // Move if Above (CF=0 & ZF=0)
+SMPTypeCategory[NN_cmovb] = 0; // Move if Below (CF=1)
+SMPTypeCategory[NN_cmovbe] = 0; // Move if Below or Equal (CF=1 | ZF=1)
+SMPTypeCategory[NN_cmovg] = 0; // Move if Greater (ZF=0 & SF=OF)
+SMPTypeCategory[NN_cmovge] = 0; // Move if Greater or Equal (SF=OF)
+SMPTypeCategory[NN_cmovl] = 0; // Move if Less (SF!=OF)
+SMPTypeCategory[NN_cmovle] = 0; // Move if Less or Equal (ZF=1 | SF!=OF)
+SMPTypeCategory[NN_cmovnb] = 0; // Move if Not Below (CF=0)
+SMPTypeCategory[NN_cmovno] = 0; // Move if Not Overflow (OF=0)
+SMPTypeCategory[NN_cmovnp] = 0; // Move if Not Parity (PF=0)
+SMPTypeCategory[NN_cmovns] = 0; // Move if Not Sign (SF=0)
+SMPTypeCategory[NN_cmovnz] = 0; // Move if Not Zero (ZF=0)
+SMPTypeCategory[NN_cmovo] = 0; // Move if Overflow (OF=1)
+SMPTypeCategory[NN_cmovp] = 0; // Move if Parity (PF=1)
+SMPTypeCategory[NN_cmovs] = 0; // Move if Sign (SF=1)
+SMPTypeCategory[NN_cmovz] = 0; // Move if Zero (ZF=1)
SMPTypeCategory[NN_fcmovb] = 1; // Floating Move if Below
SMPTypeCategory[NN_fcmove] = 1; // Floating Move if Equal
SMPTypeCategory[NN_fcmovbe] = 1; // Floating Move if Below or Equal
@@ -2068,50 +2069,50 @@ SMPTypeCategory[NN_loadall] = 0; // Load the entire CPU state from E
SMPTypeCategory[NN_emms] = 1; // Empty MMX state
SMPTypeCategory[NN_movd] = 15; // Move 32 bits
SMPTypeCategory[NN_movq] = 15; // Move 64 bits
-SMPTypeCategory[NN_packsswb] = 15; // Pack with Signed Saturation (Word->Byte)
-SMPTypeCategory[NN_packssdw] = 15; // Pack with Signed Saturation (Dword->Word)
-SMPTypeCategory[NN_packuswb] = 15; // Pack with Unsigned Saturation (Word->Byte)
-SMPTypeCategory[NN_paddb] = 15; // Packed Add Byte
-SMPTypeCategory[NN_paddw] = 15; // Packed Add Word
-SMPTypeCategory[NN_paddd] = 15; // Packed Add Dword
-SMPTypeCategory[NN_paddsb] = 15; // Packed Add with Saturation (Byte)
-SMPTypeCategory[NN_paddsw] = 15; // Packed Add with Saturation (Word)
-SMPTypeCategory[NN_paddusb] = 15; // Packed Add Unsigned with Saturation (Byte)
-SMPTypeCategory[NN_paddusw] = 15; // Packed Add Unsigned with Saturation (Word)
-SMPTypeCategory[NN_pand] = 15; // Bitwise Logical And
-SMPTypeCategory[NN_pandn] = 15; // Bitwise Logical And Not
-SMPTypeCategory[NN_pcmpeqb] = 15; // Packed Compare for Equal (Byte)
-SMPTypeCategory[NN_pcmpeqw] = 15; // Packed Compare for Equal (Word)
-SMPTypeCategory[NN_pcmpeqd] = 15; // Packed Compare for Equal (Dword)
-SMPTypeCategory[NN_pcmpgtb] = 15; // Packed Compare for Greater Than (Byte)
-SMPTypeCategory[NN_pcmpgtw] = 15; // Packed Compare for Greater Than (Word)
-SMPTypeCategory[NN_pcmpgtd] = 15; // Packed Compare for Greater Than (Dword)
-SMPTypeCategory[NN_pmaddwd] = 15; // Packed Multiply and Add
-SMPTypeCategory[NN_pmulhw] = 15; // Packed Multiply High
-SMPTypeCategory[NN_pmullw] = 15; // Packed Multiply Low
-SMPTypeCategory[NN_por] = 15; // Bitwise Logical Or
-SMPTypeCategory[NN_psllw] = 15; // Packed Shift Left Logical (Word)
-SMPTypeCategory[NN_pslld] = 15; // Packed Shift Left Logical (Dword)
-SMPTypeCategory[NN_psllq] = 15; // Packed Shift Left Logical (Qword)
-SMPTypeCategory[NN_psraw] = 15; // Packed Shift Right Arithmetic (Word)
-SMPTypeCategory[NN_psrad] = 15; // Packed Shift Right Arithmetic (Dword)
-SMPTypeCategory[NN_psrlw] = 15; // Packed Shift Right Logical (Word)
-SMPTypeCategory[NN_psrld] = 15; // Packed Shift Right Logical (Dword)
-SMPTypeCategory[NN_psrlq] = 15; // Packed Shift Right Logical (Qword)
-SMPTypeCategory[NN_psubb] = 15; // Packed Subtract Byte
-SMPTypeCategory[NN_psubw] = 15; // Packed Subtract Word
-SMPTypeCategory[NN_psubd] = 15; // Packed Subtract Dword
-SMPTypeCategory[NN_psubsb] = 15; // Packed Subtract with Saturation (Byte)
-SMPTypeCategory[NN_psubsw] = 15; // Packed Subtract with Saturation (Word)
-SMPTypeCategory[NN_psubusb] = 15; // Packed Subtract Unsigned with Saturation (Byte)
-SMPTypeCategory[NN_psubusw] = 15; // Packed Subtract Unsigned with Saturation (Word)
-SMPTypeCategory[NN_punpckhbw] = 15; // Unpack High Packed Data (Byte->Word)
-SMPTypeCategory[NN_punpckhwd] = 15; // Unpack High Packed Data (Word->Dword)
-SMPTypeCategory[NN_punpckhdq] = 15; // Unpack High Packed Data (Dword->Qword)
-SMPTypeCategory[NN_punpcklbw] = 15; // Unpack Low Packed Data (Byte->Word)
-SMPTypeCategory[NN_punpcklwd] = 15; // Unpack Low Packed Data (Word->Dword)
-SMPTypeCategory[NN_punpckldq] = 15; // Unpack Low Packed Data (Dword->Qword)
-SMPTypeCategory[NN_pxor] = 15; // Bitwise Logical Exclusive Or
+SMPTypeCategory[NN_packsswb] = 14; // Pack with Signed Saturation (Word->Byte)
+SMPTypeCategory[NN_packssdw] = 14; // Pack with Signed Saturation (Dword->Word)
+SMPTypeCategory[NN_packuswb] = 14; // Pack with Unsigned Saturation (Word->Byte)
+SMPTypeCategory[NN_paddb] = 14; // Packed Add Byte
+SMPTypeCategory[NN_paddw] = 14; // Packed Add Word
+SMPTypeCategory[NN_paddd] = 14; // Packed Add Dword
+SMPTypeCategory[NN_paddsb] = 14; // Packed Add with Saturation (Byte)
+SMPTypeCategory[NN_paddsw] = 14; // Packed Add with Saturation (Word)
+SMPTypeCategory[NN_paddusb] = 14; // Packed Add Unsigned with Saturation (Byte)
+SMPTypeCategory[NN_paddusw] = 14; // Packed Add Unsigned with Saturation (Word)
+SMPTypeCategory[NN_pand] = 14; // Bitwise Logical And
+SMPTypeCategory[NN_pandn] = 14; // Bitwise Logical And Not
+SMPTypeCategory[NN_pcmpeqb] = 14; // Packed Compare for Equal (Byte)
+SMPTypeCategory[NN_pcmpeqw] = 14; // Packed Compare for Equal (Word)
+SMPTypeCategory[NN_pcmpeqd] = 14; // Packed Compare for Equal (Dword)
+SMPTypeCategory[NN_pcmpgtb] = 14; // Packed Compare for Greater Than (Byte)
+SMPTypeCategory[NN_pcmpgtw] = 14; // Packed Compare for Greater Than (Word)
+SMPTypeCategory[NN_pcmpgtd] = 14; // Packed Compare for Greater Than (Dword)
+SMPTypeCategory[NN_pmaddwd] = 14; // Packed Multiply and Add
+SMPTypeCategory[NN_pmulhw] = 14; // Packed Multiply High
+SMPTypeCategory[NN_pmullw] = 14; // Packed Multiply Low
+SMPTypeCategory[NN_por] = 14; // Bitwise Logical Or
+SMPTypeCategory[NN_psllw] = 14; // Packed Shift Left Logical (Word)
+SMPTypeCategory[NN_pslld] = 14; // Packed Shift Left Logical (Dword)
+SMPTypeCategory[NN_psllq] = 14; // Packed Shift Left Logical (Qword)
+SMPTypeCategory[NN_psraw] = 14; // Packed Shift Right Arithmetic (Word)
+SMPTypeCategory[NN_psrad] = 14; // Packed Shift Right Arithmetic (Dword)
+SMPTypeCategory[NN_psrlw] = 14; // Packed Shift Right Logical (Word)
+SMPTypeCategory[NN_psrld] = 14; // Packed Shift Right Logical (Dword)
+SMPTypeCategory[NN_psrlq] = 14; // Packed Shift Right Logical (Qword)
+SMPTypeCategory[NN_psubb] = 14; // Packed Subtract Byte
+SMPTypeCategory[NN_psubw] = 14; // Packed Subtract Word
+SMPTypeCategory[NN_psubd] = 14; // Packed Subtract Dword
+SMPTypeCategory[NN_psubsb] = 14; // Packed Subtract with Saturation (Byte)
+SMPTypeCategory[NN_psubsw] = 14; // Packed Subtract with Saturation (Word)
+SMPTypeCategory[NN_psubusb] = 14; // Packed Subtract Unsigned with Saturation (Byte)
+SMPTypeCategory[NN_psubusw] = 14; // Packed Subtract Unsigned with Saturation (Word)
+SMPTypeCategory[NN_punpckhbw] = 14; // Unpack High Packed Data (Byte->Word)
+SMPTypeCategory[NN_punpckhwd] = 14; // Unpack High Packed Data (Word->Dword)
+SMPTypeCategory[NN_punpckhdq] = 14; // Unpack High Packed Data (Dword->Qword)
+SMPTypeCategory[NN_punpcklbw] = 14; // Unpack Low Packed Data (Byte->Word)
+SMPTypeCategory[NN_punpcklwd] = 14; // Unpack Low Packed Data (Word->Dword)
+SMPTypeCategory[NN_punpckldq] = 14; // Unpack Low Packed Data (Dword->Qword)
+SMPTypeCategory[NN_pxor] = 14; // Bitwise Logical Exclusive Or
//
// Undocumented Deschutes processor instructions
@@ -2127,25 +2128,25 @@ SMPTypeCategory[NN_sysexit] = 1; // Fast Transition from System Call
// 3DNow! instructions
-SMPTypeCategory[NN_pavgusb] = 15; // Packed 8-bit Unsigned Integer Averaging
-SMPTypeCategory[NN_pfadd] = 15; // Packed Floating-Point Addition
-SMPTypeCategory[NN_pfsub] = 15; // Packed Floating-Point Subtraction
-SMPTypeCategory[NN_pfsubr] = 15; // Packed Floating-Point Reverse Subtraction
-SMPTypeCategory[NN_pfacc] = 15; // Packed Floating-Point Accumulate
-SMPTypeCategory[NN_pfcmpge] = 15; // Packed Floating-Point Comparison, Greater or Equal
-SMPTypeCategory[NN_pfcmpgt] = 15; // Packed Floating-Point Comparison, Greater
-SMPTypeCategory[NN_pfcmpeq] = 15; // Packed Floating-Point Comparison, Equal
-SMPTypeCategory[NN_pfmin] = 15; // Packed Floating-Point Minimum
-SMPTypeCategory[NN_pfmax] = 15; // Packed Floating-Point Maximum
-SMPTypeCategory[NN_pi2fd] = 15; // Packed 32-bit Integer to Floating-Point
-SMPTypeCategory[NN_pf2id] = 15; // Packed Floating-Point to 32-bit Integer
-SMPTypeCategory[NN_pfrcp] = 15; // Packed Floating-Point Reciprocal Approximation
-SMPTypeCategory[NN_pfrsqrt] = 15; // Packed Floating-Point Reciprocal Square Root Approximation
-SMPTypeCategory[NN_pfmul] = 15; // Packed Floating-Point Multiplication
-SMPTypeCategory[NN_pfrcpit1] = 15; // Packed Floating-Point Reciprocal First Iteration Step
-SMPTypeCategory[NN_pfrsqit1] = 15; // Packed Floating-Point Reciprocal Square Root First Iteration Step
-SMPTypeCategory[NN_pfrcpit2] = 15; // Packed Floating-Point Reciprocal Second Iteration Step
-SMPTypeCategory[NN_pmulhrw] = 15; // Packed Floating-Point 16-bit Integer Multiply with rounding
+SMPTypeCategory[NN_pavgusb] = 14; // Packed 8-bit Unsigned Integer Averaging
+SMPTypeCategory[NN_pfadd] = 14; // Packed Floating-Point Addition
+SMPTypeCategory[NN_pfsub] = 14; // Packed Floating-Point Subtraction
+SMPTypeCategory[NN_pfsubr] = 14; // Packed Floating-Point Reverse Subtraction
+SMPTypeCategory[NN_pfacc] = 14; // Packed Floating-Point Accumulate
+SMPTypeCategory[NN_pfcmpge] = 14; // Packed Floating-Point Comparison, Greater or Equal
+SMPTypeCategory[NN_pfcmpgt] = 14; // Packed Floating-Point Comparison, Greater
+SMPTypeCategory[NN_pfcmpeq] = 14; // Packed Floating-Point Comparison, Equal
+SMPTypeCategory[NN_pfmin] = 14; // Packed Floating-Point Minimum
+SMPTypeCategory[NN_pfmax] = 14; // Packed Floating-Point Maximum
+SMPTypeCategory[NN_pi2fd] = 14; // Packed 32-bit Integer to Floating-Point
+SMPTypeCategory[NN_pf2id] = 14; // Packed Floating-Point to 32-bit Integer
+SMPTypeCategory[NN_pfrcp] = 14; // Packed Floating-Point Reciprocal Approximation
+SMPTypeCategory[NN_pfrsqrt] = 14; // Packed Floating-Point Reciprocal Square Root Approximation
+SMPTypeCategory[NN_pfmul] = 14; // Packed Floating-Point Multiplication
+SMPTypeCategory[NN_pfrcpit1] = 14; // Packed Floating-Point Reciprocal First Iteration Step
+SMPTypeCategory[NN_pfrsqit1] = 14; // Packed Floating-Point Reciprocal Square Root First Iteration Step
+SMPTypeCategory[NN_pfrcpit2] = 14; // Packed Floating-Point Reciprocal Second Iteration Step
+SMPTypeCategory[NN_pmulhrw] = 14; // Packed Floating-Point 16-bit Integer Multiply with rounding
SMPTypeCategory[NN_femms] = 1; // Faster entry/exit of the MMX or floating-point state
SMPTypeCategory[NN_prefetch] = 1; // Prefetch at least a 32-byte line into L1 data cache
SMPTypeCategory[NN_prefetchw] = 1; // Prefetch processor cache line into L1 data cache (mark as modified)
@@ -2153,26 +2154,26 @@ SMPTypeCategory[NN_prefetchw] = 1; // Prefetch processor cache line in
// Pentium III instructions
-SMPTypeCategory[NN_addps] = 15; // Packed Single-FP Add
-SMPTypeCategory[NN_addss] = 15; // Scalar Single-FP Add
-SMPTypeCategory[NN_andnps] = 15; // Bitwise Logical And Not for Single-FP
-SMPTypeCategory[NN_andps] = 15; // Bitwise Logical And for Single-FP
-SMPTypeCategory[NN_cmpps] = 15; // Packed Single-FP Compare
-SMPTypeCategory[NN_cmpss] = 15; // Scalar Single-FP Compare
-SMPTypeCategory[NN_comiss] = 15; // Scalar Ordered Single-FP Compare and Set EFLAGS
-SMPTypeCategory[NN_cvtpi2ps] = 15; // Packed signed INT32 to Packed Single-FP conversion
-SMPTypeCategory[NN_cvtps2pi] = 15; // Packed Single-FP to Packed INT32 conversion
-SMPTypeCategory[NN_cvtsi2ss] = 15; // Scalar signed INT32 to Single-FP conversion
-SMPTypeCategory[NN_cvtss2si] = 15; // Scalar Single-FP to signed INT32 conversion
-SMPTypeCategory[NN_cvttps2pi] = 15; // Packed Single-FP to Packed INT32 conversion (truncate)
-SMPTypeCategory[NN_cvttss2si] = 15; // Scalar Single-FP to signed INT32 conversion (truncate)
-SMPTypeCategory[NN_divps] = 15; // Packed Single-FP Divide
-SMPTypeCategory[NN_divss] = 15; // Scalar Single-FP Divide
-SMPTypeCategory[NN_ldmxcsr] = 15; // Load Streaming SIMD Extensions Technology Control/Status Register
-SMPTypeCategory[NN_maxps] = 15; // Packed Single-FP Maximum
-SMPTypeCategory[NN_maxss] = 15; // Scalar Single-FP Maximum
-SMPTypeCategory[NN_minps] = 15; // Packed Single-FP Minimum
-SMPTypeCategory[NN_minss] = 15; // Scalar Single-FP Minimum
+SMPTypeCategory[NN_addps] = 14; // Packed Single-FP Add
+SMPTypeCategory[NN_addss] = 14; // Scalar Single-FP Add
+SMPTypeCategory[NN_andnps] = 14; // Bitwise Logical And Not for Single-FP
+SMPTypeCategory[NN_andps] = 14; // Bitwise Logical And for Single-FP
+SMPTypeCategory[NN_cmpps] = 14; // Packed Single-FP Compare
+SMPTypeCategory[NN_cmpss] = 14; // Scalar Single-FP Compare
+SMPTypeCategory[NN_comiss] = 14; // Scalar Ordered Single-FP Compare and Set EFLAGS
+SMPTypeCategory[NN_cvtpi2ps] = 14; // Packed signed INT32 to Packed Single-FP conversion
+SMPTypeCategory[NN_cvtps2pi] = 14; // Packed Single-FP to Packed INT32 conversion
+SMPTypeCategory[NN_cvtsi2ss] = 14; // Scalar signed INT32 to Single-FP conversion
+SMPTypeCategory[NN_cvtss2si] = 14; // Scalar Single-FP to signed INT32 conversion
+SMPTypeCategory[NN_cvttps2pi] = 14; // Packed Single-FP to Packed INT32 conversion (truncate)
+SMPTypeCategory[NN_cvttss2si] = 14; // Scalar Single-FP to signed INT32 conversion (truncate)
+SMPTypeCategory[NN_divps] = 14; // Packed Single-FP Divide
+SMPTypeCategory[NN_divss] = 14; // Scalar Single-FP Divide
+SMPTypeCategory[NN_ldmxcsr] = 14; // Load Streaming SIMD Extensions Technology Control/Status Register
+SMPTypeCategory[NN_maxps] = 14; // Packed Single-FP Maximum
+SMPTypeCategory[NN_maxss] = 14; // Scalar Single-FP Maximum
+SMPTypeCategory[NN_minps] = 14; // Packed Single-FP Minimum
+SMPTypeCategory[NN_minss] = 14; // Scalar Single-FP Minimum
SMPTypeCategory[NN_movaps] = 15; // Move Aligned Four Packed Single-FP ** infer memsrc 'n'?
SMPTypeCategory[NN_movhlps] = 15; // Move High to Low Packed Single-FP
SMPTypeCategory[NN_movhps] = 15; // Move High Packed Single-FP
@@ -2181,35 +2182,35 @@ SMPTypeCategory[NN_movlps] = 15; // Move Low Packed Single-FP
SMPTypeCategory[NN_movmskps] = 15; // Move Mask to Register
SMPTypeCategory[NN_movss] = 15; // Move Scalar Single-FP
SMPTypeCategory[NN_movups] = 15; // Move Unaligned Four Packed Single-FP
-SMPTypeCategory[NN_mulps] = 15; // Packed Single-FP Multiply
-SMPTypeCategory[NN_mulss] = 15; // Scalar Single-FP Multiply
-SMPTypeCategory[NN_orps] = 15; // Bitwise Logical OR for Single-FP Data
-SMPTypeCategory[NN_rcpps] = 15; // Packed Single-FP Reciprocal
-SMPTypeCategory[NN_rcpss] = 15; // Scalar Single-FP Reciprocal
-SMPTypeCategory[NN_rsqrtps] = 15; // Packed Single-FP Square Root Reciprocal
-SMPTypeCategory[NN_rsqrtss] = 15; // Scalar Single-FP Square Root Reciprocal
-SMPTypeCategory[NN_shufps] = 15; // Shuffle Single-FP
-SMPTypeCategory[NN_sqrtps] = 15; // Packed Single-FP Square Root
-SMPTypeCategory[NN_sqrtss] = 15; // Scalar Single-FP Square Root
+SMPTypeCategory[NN_mulps] = 14; // Packed Single-FP Multiply
+SMPTypeCategory[NN_mulss] = 14; // Scalar Single-FP Multiply
+SMPTypeCategory[NN_orps] = 14; // Bitwise Logical OR for Single-FP Data
+SMPTypeCategory[NN_rcpps] = 14; // Packed Single-FP Reciprocal
+SMPTypeCategory[NN_rcpss] = 14; // Scalar Single-FP Reciprocal
+SMPTypeCategory[NN_rsqrtps] = 14; // Packed Single-FP Square Root Reciprocal
+SMPTypeCategory[NN_rsqrtss] = 14; // Scalar Single-FP Square Root Reciprocal
+SMPTypeCategory[NN_shufps] = 14; // Shuffle Single-FP
+SMPTypeCategory[NN_sqrtps] = 14; // Packed Single-FP Square Root
+SMPTypeCategory[NN_sqrtss] = 14; // Scalar Single-FP Square Root
SMPTypeCategory[NN_stmxcsr] = 15; // Store Streaming SIMD Extensions Technology Control/Status Register ** Infer dest is 'n'
-SMPTypeCategory[NN_subps] = 15; // Packed Single-FP Subtract
-SMPTypeCategory[NN_subss] = 15; // Scalar Single-FP Subtract
-SMPTypeCategory[NN_ucomiss] = 15; // Scalar Unordered Single-FP Compare and Set EFLAGS
-SMPTypeCategory[NN_unpckhps] = 15; // Unpack High Packed Single-FP Data
-SMPTypeCategory[NN_unpcklps] = 15; // Unpack Low Packed Single-FP Data
-SMPTypeCategory[NN_xorps] = 15; // Bitwise Logical XOR for Single-FP Data
-SMPTypeCategory[NN_pavgb] = 15; // Packed Average (Byte)
-SMPTypeCategory[NN_pavgw] = 15; // Packed Average (Word)
-SMPTypeCategory[NN_pextrw] = 15; // Extract Word
-SMPTypeCategory[NN_pinsrw] = 15; // Insert Word
-SMPTypeCategory[NN_pmaxsw] = 15; // Packed Signed Integer Word Maximum
-SMPTypeCategory[NN_pmaxub] = 15; // Packed Unsigned Integer Byte Maximum
-SMPTypeCategory[NN_pminsw] = 15; // Packed Signed Integer Word Minimum
-SMPTypeCategory[NN_pminub] = 15; // Packed Unsigned Integer Byte Minimum
-SMPTypeCategory[NN_pmovmskb] = 15; // Move Byte Mask to Integer
-SMPTypeCategory[NN_pmulhuw] = 15; // Packed Multiply High Unsigned
-SMPTypeCategory[NN_psadbw] = 15; // Packed Sum of Absolute Differences
-SMPTypeCategory[NN_pshufw] = 15; // Packed Shuffle Word
+SMPTypeCategory[NN_subps] = 14; // Packed Single-FP Subtract
+SMPTypeCategory[NN_subss] = 14; // Scalar Single-FP Subtract
+SMPTypeCategory[NN_ucomiss] = 14; // Scalar Unordered Single-FP Compare and Set EFLAGS
+SMPTypeCategory[NN_unpckhps] = 14; // Unpack High Packed Single-FP Data
+SMPTypeCategory[NN_unpcklps] = 14; // Unpack Low Packed Single-FP Data
+SMPTypeCategory[NN_xorps] = 14; // Bitwise Logical XOR for Single-FP Data
+SMPTypeCategory[NN_pavgb] = 14; // Packed Average (Byte)
+SMPTypeCategory[NN_pavgw] = 14; // Packed Average (Word)
+SMPTypeCategory[NN_pextrw] = 2; // Extract Word
+SMPTypeCategory[NN_pinsrw] = 14; // Insert Word
+SMPTypeCategory[NN_pmaxsw] = 14; // Packed Signed Integer Word Maximum
+SMPTypeCategory[NN_pmaxub] = 14; // Packed Unsigned Integer Byte Maximum
+SMPTypeCategory[NN_pminsw] = 14; // Packed Signed Integer Word Minimum
+SMPTypeCategory[NN_pminub] = 14; // Packed Unsigned Integer Byte Minimum
+SMPTypeCategory[NN_pmovmskb] = 2; // Move Byte Mask to Integer
+SMPTypeCategory[NN_pmulhuw] = 14; // Packed Multiply High Unsigned
+SMPTypeCategory[NN_psadbw] = 14; // Packed Sum of Absolute Differences
+SMPTypeCategory[NN_pshufw] = 14; // Packed Shuffle Word
SMPTypeCategory[NN_maskmovq] = 15; // Byte Mask write ** Infer dest is 'n'
SMPTypeCategory[NN_movntps] = 13; // Move Aligned Four Packed Single-FP Non Temporal * infer dest is 'n'
SMPTypeCategory[NN_movntq] = 13; // Move 64 Bits Non Temporal ** Infer dest is 'n'
@@ -2221,22 +2222,22 @@ SMPTypeCategory[NN_sfence] = 1; // Store Fence
// Pentium III Pseudo instructions
-SMPTypeCategory[NN_cmpeqps] = 15; // Packed Single-FP Compare EQ
-SMPTypeCategory[NN_cmpltps] = 15; // Packed Single-FP Compare LT
-SMPTypeCategory[NN_cmpleps] = 15; // Packed Single-FP Compare LE
-SMPTypeCategory[NN_cmpunordps] = 15; // Packed Single-FP Compare UNORD
-SMPTypeCategory[NN_cmpneqps] = 15; // Packed Single-FP Compare NOT EQ
-SMPTypeCategory[NN_cmpnltps] = 15; // Packed Single-FP Compare NOT LT
-SMPTypeCategory[NN_cmpnleps] = 15; // Packed Single-FP Compare NOT LE
-SMPTypeCategory[NN_cmpordps] = 15; // Packed Single-FP Compare ORDERED
-SMPTypeCategory[NN_cmpeqss] = 15; // Scalar Single-FP Compare EQ
-SMPTypeCategory[NN_cmpltss] = 15; // Scalar Single-FP Compare LT
-SMPTypeCategory[NN_cmpless] = 15; // Scalar Single-FP Compare LE
-SMPTypeCategory[NN_cmpunordss] = 15; // Scalar Single-FP Compare UNORD
-SMPTypeCategory[NN_cmpneqss] = 15; // Scalar Single-FP Compare NOT EQ
-SMPTypeCategory[NN_cmpnltss] = 15; // Scalar Single-FP Compare NOT LT
-SMPTypeCategory[NN_cmpnless] = 15; // Scalar Single-FP Compare NOT LE
-SMPTypeCategory[NN_cmpordss] = 15; // Scalar Single-FP Compare ORDERED
+SMPTypeCategory[NN_cmpeqps] = 14; // Packed Single-FP Compare EQ
+SMPTypeCategory[NN_cmpltps] = 14; // Packed Single-FP Compare LT
+SMPTypeCategory[NN_cmpleps] = 14; // Packed Single-FP Compare LE
+SMPTypeCategory[NN_cmpunordps] = 14; // Packed Single-FP Compare UNORD
+SMPTypeCategory[NN_cmpneqps] = 14; // Packed Single-FP Compare NOT EQ
+SMPTypeCategory[NN_cmpnltps] = 14; // Packed Single-FP Compare NOT LT
+SMPTypeCategory[NN_cmpnleps] = 14; // Packed Single-FP Compare NOT LE
+SMPTypeCategory[NN_cmpordps] = 14; // Packed Single-FP Compare ORDERED
+SMPTypeCategory[NN_cmpeqss] = 14; // Scalar Single-FP Compare EQ
+SMPTypeCategory[NN_cmpltss] = 14; // Scalar Single-FP Compare LT
+SMPTypeCategory[NN_cmpless] = 14; // Scalar Single-FP Compare LE
+SMPTypeCategory[NN_cmpunordss] = 14; // Scalar Single-FP Compare UNORD
+SMPTypeCategory[NN_cmpneqss] = 14; // Scalar Single-FP Compare NOT EQ
+SMPTypeCategory[NN_cmpnltss] = 14; // Scalar Single-FP Compare NOT LT
+SMPTypeCategory[NN_cmpnless] = 14; // Scalar Single-FP Compare NOT LE
+SMPTypeCategory[NN_cmpordss] = 14; // Scalar Single-FP Compare ORDERED
// AMD K7 instructions
@@ -2261,39 +2262,39 @@ SMPTypeCategory[NN_fstp9] = 9; // Alias of Store Real and Pop
// Pentium 4 instructions
-SMPTypeCategory[NN_addpd] = 15; // Add Packed Double-Precision Floating-Point Values
-SMPTypeCategory[NN_addsd] = 15; // Add Scalar Double-Precision Floating-Point Values
-SMPTypeCategory[NN_andnpd] = 15; // Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
-SMPTypeCategory[NN_andpd] = 15; // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
+SMPTypeCategory[NN_addpd] = 14; // Add Packed Double-Precision Floating-Point Values
+SMPTypeCategory[NN_addsd] = 14; // Add Scalar Double-Precision Floating-Point Values
+SMPTypeCategory[NN_andnpd] = 14; // Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
+SMPTypeCategory[NN_andpd] = 14; // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_clflush] = 1; // Flush Cache Line
-SMPTypeCategory[NN_cmppd] = 15; // Compare Packed Double-Precision Floating-Point Values
-SMPTypeCategory[NN_cmpsd] = 15; // Compare Scalar Double-Precision Floating-Point Values
-SMPTypeCategory[NN_comisd] = 15; // Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
-SMPTypeCategory[NN_cvtdq2pd] = 15; // Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
-SMPTypeCategory[NN_cvtdq2ps] = 15; // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
-SMPTypeCategory[NN_cvtpd2dq] = 15; // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
-SMPTypeCategory[NN_cvtpd2pi] = 15; // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
-SMPTypeCategory[NN_cvtpd2ps] = 15; // Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
-SMPTypeCategory[NN_cvtpi2pd] = 15; // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
-SMPTypeCategory[NN_cvtps2dq] = 15; // Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
-SMPTypeCategory[NN_cvtps2pd] = 15; // Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
-SMPTypeCategory[NN_cvtsd2si] = 15; // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
-SMPTypeCategory[NN_cvtsd2ss] = 15; // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
-SMPTypeCategory[NN_cvtsi2sd] = 15; // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
-SMPTypeCategory[NN_cvtss2sd] = 15; // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
-SMPTypeCategory[NN_cvttpd2dq] = 15; // Convert With Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
-SMPTypeCategory[NN_cvttpd2pi] = 15; // Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
-SMPTypeCategory[NN_cvttps2dq] = 15; // Convert With Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
-SMPTypeCategory[NN_cvttsd2si] = 15; // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
-SMPTypeCategory[NN_divpd] = 15; // Divide Packed Double-Precision Floating-Point Values
-SMPTypeCategory[NN_divsd] = 15; // Divide Scalar Double-Precision Floating-Point Values
+SMPTypeCategory[NN_cmppd] = 14; // Compare Packed Double-Precision Floating-Point Values
+SMPTypeCategory[NN_cmpsd] = 14; // Compare Scalar Double-Precision Floating-Point Values
+SMPTypeCategory[NN_comisd] = 14; // Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
+SMPTypeCategory[NN_cvtdq2pd] = 14; // Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
+SMPTypeCategory[NN_cvtdq2ps] = 14; // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
+SMPTypeCategory[NN_cvtpd2dq] = 14; // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
+SMPTypeCategory[NN_cvtpd2pi] = 14; // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
+SMPTypeCategory[NN_cvtpd2ps] = 14; // Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
+SMPTypeCategory[NN_cvtpi2pd] = 14; // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
+SMPTypeCategory[NN_cvtps2dq] = 14; // Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
+SMPTypeCategory[NN_cvtps2pd] = 14; // Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
+SMPTypeCategory[NN_cvtsd2si] = 14; // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
+SMPTypeCategory[NN_cvtsd2ss] = 14; // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
+SMPTypeCategory[NN_cvtsi2sd] = 14; // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
+SMPTypeCategory[NN_cvtss2sd] = 14; // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
+SMPTypeCategory[NN_cvttpd2dq] = 14; // Convert With Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
+SMPTypeCategory[NN_cvttpd2pi] = 14; // Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
+SMPTypeCategory[NN_cvttps2dq] = 14; // Convert With Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
+SMPTypeCategory[NN_cvttsd2si] = 14; // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
+SMPTypeCategory[NN_divpd] = 14; // Divide Packed Double-Precision Floating-Point Values
+SMPTypeCategory[NN_divsd] = 14; // Divide Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_lfence] = 1; // Load Fence
SMPTypeCategory[NN_maskmovdqu] = 13; // Store Selected Bytes of Double Quadword ** Infer dest is 'n'
-SMPTypeCategory[NN_maxpd] = 15; // Return Maximum Packed Double-Precision Floating-Point Values
-SMPTypeCategory[NN_maxsd] = 15; // Return Maximum Scalar Double-Precision Floating-Point Value
+SMPTypeCategory[NN_maxpd] = 14; // Return Maximum Packed Double-Precision Floating-Point Values
+SMPTypeCategory[NN_maxsd] = 14; // Return Maximum Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_mfence] = 1; // Memory Fence
-SMPTypeCategory[NN_minpd] = 15; // Return Minimum Packed Double-Precision Floating-Point Values
-SMPTypeCategory[NN_minsd] = 15; // Return Minimum Scalar Double-Precision Floating-Point Value
+SMPTypeCategory[NN_minpd] = 14; // Return Minimum Packed Double-Precision Floating-Point Values
+SMPTypeCategory[NN_minsd] = 14; // Return Minimum Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_movapd] = 15; // Move Aligned Packed Double-Precision Floating-Point Values ** Infer dest is 'n'
SMPTypeCategory[NN_movdq2q] = 15; // Move Quadword from XMM to MMX Register
SMPTypeCategory[NN_movdqa] = 15; // Move Aligned Double Quadword ** Infer dest is 'n'
@@ -2307,29 +2308,29 @@ SMPTypeCategory[NN_movntpd] = 13; // Store Packed Double-Precision F
SMPTypeCategory[NN_movq2dq] = 1; // Move Quadword from MMX to XMM Register
SMPTypeCategory[NN_movsd] = 15; // Move Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_movupd] = 15; // Move Unaligned Packed Double-Precision Floating-Point Values
-SMPTypeCategory[NN_mulpd] = 15; // Multiply Packed Double-Precision Floating-Point Values
-SMPTypeCategory[NN_mulsd] = 15; // Multiply Scalar Double-Precision Floating-Point Values
-SMPTypeCategory[NN_orpd] = 15; // Bitwise Logical OR of Double-Precision Floating-Point Values
-SMPTypeCategory[NN_paddq] = 15; // Add Packed Quadword Integers
+SMPTypeCategory[NN_mulpd] = 14; // Multiply Packed Double-Precision Floating-Point Values
+SMPTypeCategory[NN_mulsd] = 14; // Multiply Scalar Double-Precision Floating-Point Values
+SMPTypeCategory[NN_orpd] = 14; // Bitwise Logical OR of Double-Precision Floating-Point Values
+SMPTypeCategory[NN_paddq] = 14; // Add Packed Quadword Integers
SMPTypeCategory[NN_pause] = 1; // Spin Loop Hint
-SMPTypeCategory[NN_pmuludq] = 15; // Multiply Packed Unsigned Doubleword Integers
-SMPTypeCategory[NN_pshufd] = 15; // Shuffle Packed Doublewords
-SMPTypeCategory[NN_pshufhw] = 15; // Shuffle Packed High Words
-SMPTypeCategory[NN_pshuflw] = 15; // Shuffle Packed Low Words
-SMPTypeCategory[NN_pslldq] = 15; // Shift Double Quadword Left Logical
-SMPTypeCategory[NN_psrldq] = 15; // Shift Double Quadword Right Logical
-SMPTypeCategory[NN_psubq] = 15; // Subtract Packed Quadword Integers
-SMPTypeCategory[NN_punpckhqdq] = 15; // Unpack High Data
-SMPTypeCategory[NN_punpcklqdq] = 15; // Unpack Low Data
-SMPTypeCategory[NN_shufpd] = 15; // Shuffle Packed Double-Precision Floating-Point Values
+SMPTypeCategory[NN_pmuludq] = 14; // Multiply Packed Unsigned Doubleword Integers
+SMPTypeCategory[NN_pshufd] = 14; // Shuffle Packed Doublewords
+SMPTypeCategory[NN_pshufhw] = 14; // Shuffle Packed High Words
+SMPTypeCategory[NN_pshuflw] = 14; // Shuffle Packed Low Words
+SMPTypeCategory[NN_pslldq] = 14; // Shift Double Quadword Left Logical
+SMPTypeCategory[NN_psrldq] = 14; // Shift Double Quadword Right Logical
+SMPTypeCategory[NN_psubq] = 14; // Subtract Packed Quadword Integers
+SMPTypeCategory[NN_punpckhqdq] = 14; // Unpack High Data
+SMPTypeCategory[NN_punpcklqdq] = 14; // Unpack Low Data
+SMPTypeCategory[NN_shufpd] = 14; // Shuffle Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_sqrtpd] = 1; // Compute Square Roots of Packed Double-Precision Floating-Point Values
-SMPTypeCategory[NN_sqrtsd] = 15; // Compute Square Rootof Scalar Double-Precision Floating-Point Value
-SMPTypeCategory[NN_subpd] = 15; // Subtract Packed Double-Precision Floating-Point Values
-SMPTypeCategory[NN_subsd] = 15; // Subtract Scalar Double-Precision Floating-Point Values
-SMPTypeCategory[NN_ucomisd] = 15; // Unordered Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
-SMPTypeCategory[NN_unpckhpd] = 15; // Unpack and Interleave High Packed Double-Precision Floating-Point Values
-SMPTypeCategory[NN_unpcklpd] = 15; // Unpack and Interleave Low Packed Double-Precision Floating-Point Values
-SMPTypeCategory[NN_xorpd] = 15; // Bitwise Logical OR of Double-Precision Floating-Point Values
+SMPTypeCategory[NN_sqrtsd] = 14; // Compute Square Rootof Scalar Double-Precision Floating-Point Value
+SMPTypeCategory[NN_subpd] = 14; // Subtract Packed Double-Precision Floating-Point Values
+SMPTypeCategory[NN_subsd] = 14; // Subtract Scalar Double-Precision Floating-Point Values
+SMPTypeCategory[NN_ucomisd] = 14; // Unordered Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
+SMPTypeCategory[NN_unpckhpd] = 14; // Unpack and Interleave High Packed Double-Precision Floating-Point Values
+SMPTypeCategory[NN_unpcklpd] = 14; // Unpack and Interleave Low Packed Double-Precision Floating-Point Values
+SMPTypeCategory[NN_xorpd] = 14; // Bitwise Logical OR of Double-Precision Floating-Point Values
// AMD syscall/sysret instructions NOTE: not AMD, found in Intel manual
@@ -2343,9 +2344,9 @@ SMPTypeCategory[NN_swapgs] = 1; // Exchange GS base with KernelGSBa
// New Pentium instructions (SSE3)
-SMPTypeCategory[NN_movddup] = 15; // Move One Double-FP and Duplicate
-SMPTypeCategory[NN_movshdup] = 15; // Move Packed Single-FP High and Duplicate
-SMPTypeCategory[NN_movsldup] = 15; // Move Packed Single-FP Low and Duplicate
+SMPTypeCategory[NN_movddup] = 14; // Move One Double-FP and Duplicate
+SMPTypeCategory[NN_movshdup] = 14; // Move Packed Single-FP High and Duplicate
+SMPTypeCategory[NN_movsldup] = 14; // Move Packed Single-FP Low and Duplicate
// Missing AMD64 instructions NOTE: also found in Intel manual
@@ -2354,12 +2355,12 @@ SMPTypeCategory[NN_cmpxchg16b] = 0; // Compare and Exchange 16 Bytes
// SSE3 instructions
-SMPTypeCategory[NN_addsubpd] = 15; // Add /Sub packed DP FP numbers
-SMPTypeCategory[NN_addsubps] = 15; // Add /Sub packed SP FP numbers
-SMPTypeCategory[NN_haddpd] = 15; // Add horizontally packed DP FP numbers
-SMPTypeCategory[NN_haddps] = 15; // Add horizontally packed SP FP numbers
-SMPTypeCategory[NN_hsubpd] = 15; // Sub horizontally packed DP FP numbers
-SMPTypeCategory[NN_hsubps] = 15; // Sub horizontally packed SP FP numbers
+SMPTypeCategory[NN_addsubpd] = 14; // Add /Sub packed DP FP numbers
+SMPTypeCategory[NN_addsubps] = 14; // Add /Sub packed SP FP numbers
+SMPTypeCategory[NN_haddpd] = 14; // Add horizontally packed DP FP numbers
+SMPTypeCategory[NN_haddps] = 14; // Add horizontally packed SP FP numbers
+SMPTypeCategory[NN_hsubpd] = 14; // Sub horizontally packed DP FP numbers
+SMPTypeCategory[NN_hsubps] = 14; // Sub horizontally packed SP FP numbers
SMPTypeCategory[NN_monitor] = 1; // Set up a linear address range to be monitored by hardware
SMPTypeCategory[NN_mwait] = 1; // Wait until write-back store performed within the range specified by the MONITOR instruction
SMPTypeCategory[NN_fisttp] = 13; // Store ST in intXX (chop) and pop
@@ -2367,22 +2368,22 @@ SMPTypeCategory[NN_lddqu] = 14; // Load unaligned integer 128-bit
// SSSE3 instructions
-SMPTypeCategory[NN_psignb] = 15; // Packed SIGN Byte
-SMPTypeCategory[NN_psignw] = 15; // Packed SIGN Word
-SMPTypeCategory[NN_psignd] = 15; // Packed SIGN Doubleword
-SMPTypeCategory[NN_pshufb] = 15; // Packed Shuffle Bytes
-SMPTypeCategory[NN_pmulhrsw] = 15; // Packed Multiply High with Round and Scale
-SMPTypeCategory[NN_pmaddubsw] = 15; // Multiply and Add Packed Signed and Unsigned Bytes
-SMPTypeCategory[NN_phsubsw] = 15; // Packed Horizontal Subtract and Saturate
-SMPTypeCategory[NN_phaddsw] = 15; // Packed Horizontal Add and Saturate
-SMPTypeCategory[NN_phaddw] = 15; // Packed Horizontal Add Word
-SMPTypeCategory[NN_phaddd] = 15; // Packed Horizontal Add Doubleword
-SMPTypeCategory[NN_phsubw] = 15; // Packed Horizontal Subtract Word
-SMPTypeCategory[NN_phsubd] = 15; // Packed Horizontal Subtract Doubleword
-SMPTypeCategory[NN_palignr] = 15; // Packed Align Right
-SMPTypeCategory[NN_pabsb] = 15; // Packed Absolute Value Byte
-SMPTypeCategory[NN_pabsw] = 15; // Packed Absolute Value Word
-SMPTypeCategory[NN_pabsd] = 15; // Packed Absolute Value Doubleword
+SMPTypeCategory[NN_psignb] = 14; // Packed SIGN Byte
+SMPTypeCategory[NN_psignw] = 14; // Packed SIGN Word
+SMPTypeCategory[NN_psignd] = 14; // Packed SIGN Doubleword
+SMPTypeCategory[NN_pshufb] = 14; // Packed Shuffle Bytes
+SMPTypeCategory[NN_pmulhrsw] = 14; // Packed Multiply High with Round and Scale
+SMPTypeCategory[NN_pmaddubsw] = 14; // Multiply and Add Packed Signed and Unsigned Bytes
+SMPTypeCategory[NN_phsubsw] = 14; // Packed Horizontal Subtract and Saturate
+SMPTypeCategory[NN_phaddsw] = 14; // Packed Horizontal Add and Saturate
+SMPTypeCategory[NN_phaddw] = 14; // Packed Horizontal Add Word
+SMPTypeCategory[NN_phaddd] = 14; // Packed Horizontal Add Doubleword
+SMPTypeCategory[NN_phsubw] = 14; // Packed Horizontal Subtract Word
+SMPTypeCategory[NN_phsubd] = 14; // Packed Horizontal Subtract Doubleword
+SMPTypeCategory[NN_palignr] = 14; // Packed Align Right
+SMPTypeCategory[NN_pabsb] = 14; // Packed Absolute Value Byte
+SMPTypeCategory[NN_pabsw] = 14; // Packed Absolute Value Word
+SMPTypeCategory[NN_pabsd] = 14; // Packed Absolute Value Doubleword
// VMX instructions
--
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