/*
* SMPDataFlowAnalysis.cpp - <see below>.
*
* Copyright (c) 2000, 2001, 2010 - University of Virginia
*
* This file is part of the Memory Error Detection System (MEDS) infrastructure.
* This file may be used and modified for non-commercial purposes as long as
* all copyright, permission, and nonwarranty notices are preserved.
* Redistribution is prohibited without prior written consent from the University
* of Virginia.
*
* Please contact the authors for restrictions applying to commercial use.
*
* THIS SOURCE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
* MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*
* Author: University of Virginia
* e-mail: jwd@virginia.com
* URL : http://www.cs.virginia.edu/
*
* Additional copyrights 2010, 2011 by Zephyr Software LLC
* e-mail: {clc,jwd}@zephyr-software.com
* URL : http://www.zephyr-software.com/
*
*/
//
// SMPDataFlowAnalysis.cpp
//
// This module contains common types an helper classes needed for the
// SMP project (Software Memory Protection).
//
#include <list>
#include <set>
#include <vector>
#include <algorithm>
#include <string>
#include <cstring>
#include <pro.h>
#include <assert.h>
#include <ida.hpp>
#include <idp.hpp>
#include <auto.hpp>
#include <bytes.hpp>
#include <funcs.hpp>
#include <intel.hpp>
#include <loader.hpp>
#include <lines.hpp>
#include <name.hpp>
#include "SMPDataFlowAnalysis.h"
#include "SMPStaticAnalyzer.h"
#include "SMPInstr.h"
#include "SMPBasicBlock.h"
#include "SMPFunction.h"
// Set these to 1 for debugging output
#define SMP_DEBUG_CONTROLFLOW 0 // tells what processing stage is entered
#define SMP_DEBUG_CHUNKS 1 // tracking down tail chunks for functions
#define SMP_DEBUG_FRAMEFIXUP 0 // Fixing up stack frame info the way we want the offsets
#define SMP_DEBUG_OPERAND_TYPES 1 // leave on; warnings that should never happen
#define STARS_DEBUG_DUMP_IDENTIFY_HIDDEN_OPERANDS 0 // print HIDDEN if operand.showed() is false
#if IDA_SDK_VERSION > 560
#define MAX_IDA_REG R_last
#else
#define MAX_IDA_REG 80
#endif
const char *RegNames[MAX_IDA_REG + 1] =
{ "EAX", "ECX", "EDX", "EBX", "ESP", "EBP", "ESI", "EDI",
"R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
"AL", "CL", "DL", "BL", "AH", "CH", "DH", "BH",
"SPL", "BPL", "SIL", "DIL", "EIP", "ES", "CS", "SS",
"DS", "FS", "GS", "CF", "ZF", "SF", "OF", "PF",
"AF", "TF", "IF", "DF", "EFLAGS", "FPU_ST0", "FPU_ST1", "FPU_ST2",
"FPU_ST3", "FPU_ST4", "FPU_ST5", "FPU_ST6", "FPU_ST7", "FPU_CTRL", "FPU_STAT", "FPU_TAGS",
"MMX0", "MMX1", "MMX2", "MMX3", "MMX4", "MMX5", "MMX6", "MMX7",
"XMM0", "XMM1", "XMM2", "XMM3", "XMM4", "XMM5", "XMM6", "XMM7",
"XMM8", "XMM9", "XMM10", "XMM11", "XMM12", "XMM13", "XMM14", "XMM15",
"MXCSR",
"YMM0", "YMM1", "YMM2", "YMM3", "YMM4", "YMM5", "YMM6", "YMM7",
"YMM8", "YMM9", "YMM10", "YMM11", "YMM12", "YMM13", "YMM14", "YMM15",
"REG_ERROR"
};
const unsigned char RegSizes[MAX_IDA_REG + 1] =
{ 4, 4, 4, 4, 4, 4, 4, 4,
8, 8, 8, 8, 8, 8, 8, 8,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 8, 8, 8,
8, 8, 8, 8, 8, 4, 4, 4,
16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16,
4,
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
4
};
const char *ErrorStrings[1] = { "ERROR_REG" };
const char *WordRegStrings[8] = { "AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI" };
const char *QWordRegStrings[8] = { "RAX", "RCX", "RDX", "RBX", "RSP", "RBP", "RSI", "RDI" };
const char *SignednessStrings[4] = { "UNKNOWNSIGN", "SIGNED", "UNSIGNED", "UNKNOWNSIGN" };
const char *LeaSignednessStrings[4] = { "NOFLAGUNKNOWNSIGN", "NOFLAGSIGNED", "NOFLAGUNSIGNED", "NOFLAGUNKNOWNSIGN" };
// Distinguishes subword regs from their parent regs
const char *MDGetRegName(STARSOpndType RegOp) {
if ((o_reg != RegOp.type) || (R_none == RegOp.reg) || (MAX_IDA_REG < RegOp.reg))
return ErrorStrings[0];
else if ((RegOp.dtyp == dt_word) && (RegOp.reg >= R_ax) && (RegOp.reg <= R_di)) {
// 16-bit registers
return WordRegStrings[RegOp.reg];
}
else if ((RegOp.dtyp == dt_qword) && (RegOp.reg >= R_ax) && (RegOp.reg <= R_di)) {
// 64-bit registers
return QWordRegStrings[RegOp.reg];
}
else {
return RegNames[RegOp.reg];
}
}
// Define instruction categories for data flow analysis.
SMPitype DFACategory[NN_last+1];
// Define instruction categories for data type analysis.
int SMPTypeCategory[NN_last+1];
// Define which instructions define and use the CPU flags.
bool SMPDefsFlags[NN_last + 1];
bool SMPUsesFlags[NN_last + 1];
// Hash a global name and SSA number into an int, for use in SMPFunction.GlobalDefAddrBySSA map
int HashGlobalNameAndSSA(STARSOpndType DefOp, int SSANum) {
assert(o_reg == DefOp.type);
return ((SSANum << 16) | (DefOp.reg));
}
// Get the size in bytes of the data type of an operand.
size_t GetOpDataSize(STARSOpndType DataOp) {
size_t DataSize;
if (o_reg == DataOp.type) {
DataSize = RegSizes[DataOp.reg];
if (DataOp.dtyp == dt_word) {
DataSize = 2;
#if 0
SMP_msg("Found 16-bit register using dtyp field.\n");
#endif
}
else if (DataOp.dtyp == dt_qword) {
DataSize = 8;
#if 0
SMP_msg("Found 64-bit register using dtyp field.\n");
#endif
}
return DataSize;
}
switch (DataOp.dtyp) {
case dt_byte:
DataSize = 1;
break;
case dt_word:
DataSize = 2;
break;
case dt_dword:
case dt_float:
case dt_code:
case dt_unicode:
case dt_string:
DataSize = 4;
break;
case dt_double:
case dt_qword:
DataSize = 8;
break;
case dt_tbyte:
DataSize = 10;
break;
case dt_packreal:
DataSize = 12;
break;
case dt_byte16:
#if IDA_SDK_VERSION > 599
case dt_ldbl:
#endif
DataSize = 16;
break;
case dt_fword:
DataSize = 6;
break;
case dt_3byte:
DataSize = 3;
break;
default:
SMP_msg("ERROR: unexpected data type %d in GetOpDataSize() :", DataOp.dtyp);
PrintOperand(DataOp);
SMP_msg("\n");
DataSize = 4;
break;
}
return DataSize;
} // end of GetOpDataSize()
// Return one of the bit width masks for the current operand.
// Pass in DataSize in bytes if known, else pass in DataSize = 0.
unsigned short ComputeOperandBitWidthMask(STARSOpndType CurrOp, size_t DataSize) {
unsigned short BitWidthMask = 32;
if (0 == DataSize)
DataSize = GetOpDataSize(CurrOp);
if (4 == DataSize)
BitWidthMask = FG_MASK_BITWIDTH_32;
else if (8 == DataSize)
BitWidthMask = FG_MASK_BITWIDTH_64;
else if (1 == DataSize)
BitWidthMask = FG_MASK_BITWIDTH_8;
else if (2 == DataSize)
BitWidthMask = FG_MASK_BITWIDTH_16;
else if (16 == DataSize)
BitWidthMask = FG_MASK_BITWIDTH_128;
else if (3 == DataSize)
BitWidthMask = FG_MASK_BITWIDTH_24;
else if (6 == DataSize)
BitWidthMask = FG_MASK_BITWIDTH_48;
else if (10 == DataSize)
BitWidthMask = FG_MASK_BITWIDTH_80;
else if (12 == DataSize)
BitWidthMask = FG_MASK_BITWIDTH_96;
else if (32 == DataSize)
BitWidthMask = FG_MASK_BITWIDTH_256;
else {
SMP_msg("ERROR: Unknown DataSize: %zu bytes ", DataSize);
PrintOperand(CurrOp);
SMP_msg("\n");
}
return BitWidthMask;
} // end of ComputeOperandBitWidthMask()
// Compute largest bit width from a SignMiscInfo bit mask.
size_t LargestBitWidthFromMask(unsigned short WidthTypeInfo) {
unsigned short BitWidthMask = WidthTypeInfo & FG_MASK_BITWIDTH_FIELDS;
size_t LargestWidth = 0;
// Go from highest bit width to lowest.
if (BitWidthMask & FG_MASK_BITWIDTH_256)
LargestWidth = 256;
else if (BitWidthMask & FG_MASK_BITWIDTH_128)
LargestWidth = 128;
else if (BitWidthMask & FG_MASK_BITWIDTH_96)
LargestWidth = 96;
else if (BitWidthMask & FG_MASK_BITWIDTH_64)
LargestWidth = 64;
else if (BitWidthMask & FG_MASK_BITWIDTH_48)
LargestWidth = 48;
else if (BitWidthMask & FG_MASK_BITWIDTH_32)
LargestWidth = 32;
else if (BitWidthMask & FG_MASK_BITWIDTH_24)
LargestWidth = 24;
else if (BitWidthMask & FG_MASK_BITWIDTH_16)
LargestWidth = 16;
else if (BitWidthMask & FG_MASK_BITWIDTH_8)
LargestWidth = 8;
return LargestWidth;
} // end of LargestBitWidthFromMask()
// Is CurrOp a general purpose register? (not flags, instruction pointer, non-integer reg, etc.)
bool MDIsGeneralPurposeReg(STARSOpndType CurrOp) {
// intel.hpp defines two ranges that are general purpose regs in enum RegNo.
return ((o_reg == CurrOp.type)
&& (((CurrOp.reg >= R_ax) && (CurrOp.reg <= R_di))
|| ((CurrOp.reg >= R_al) && (CurrOp.reg <= R_dil))));
}
// We maintain a list of the caller-saved regs for the current binary's ABI.
// This differs from 32-bit to 64-bit x86 binaries, as well as across other ISAs.
list<uint16> STARS_MDCallerSavedRegs;
void MDInitializeCallerSavedRegs(void) {
STARS_MDCallerSavedRegs.clear();
bool x86_64_ISA_flag = false;
#ifdef __EA64__
x86_64_ISA_flag = (STARS_ISA_Bitwidth == 64);
#endif
if (!x86_64_ISA_flag) {
// 32-bit x86 uses EAX, ECX, EDX as caller-saved.
STARS_MDCallerSavedRegs.push_back(R_ax);
STARS_MDCallerSavedRegs.push_back(R_cx);
STARS_MDCallerSavedRegs.push_back(R_dx);
}
else {
// 64-bit x86 uses EDI, ESI, EDX, ECX, R8 and R9
// in that order. After six arguments that fit into
// these regs, arguments are passed on the stack.
// In addition, registers EAX, R10 and R11 are caller-saved
// but are not used to pass arguments.
STARS_MDCallerSavedRegs.push_back(R_ax);
STARS_MDCallerSavedRegs.push_back(R_cx);
STARS_MDCallerSavedRegs.push_back(R_dx);
STARS_MDCallerSavedRegs.push_back(R_si);
STARS_MDCallerSavedRegs.push_back(R_di);
STARS_MDCallerSavedRegs.push_back(R_r8);
STARS_MDCallerSavedRegs.push_back(R_r9);
STARS_MDCallerSavedRegs.push_back(R_r10);
STARS_MDCallerSavedRegs.push_back(R_r11);
}
return;
}
list<uint16>::iterator GetFirstCallerSavedReg(void) {
return STARS_MDCallerSavedRegs.begin();
}
list<uint16>::iterator GetLastCallerSavedReg(void) {
return STARS_MDCallerSavedRegs.end();
}
// We maintain a list of the argument-passing regs for the current binary's ABI.
// This differs from 32-bit to 64-bit x86 binaries, as well as across other ISAs.
// The list is in order of argument position number. For x86-64, this means EDI,
// ESI, EDX, ECX, R8, R9.
list<uint16> STARS_MDArgumentRegs;
void MDInitializeArgumentRegs(void) {
bool x86_64_ISA_flag = false;
#ifdef __EA64__
x86_64_ISA_flag = (STARS_ISA_Bitwidth == 64);
#endif
if (x86_64_ISA_flag) {
STARS_MDArgumentRegs.push_back(R_di);
STARS_MDArgumentRegs.push_back(R_si);
STARS_MDArgumentRegs.push_back(R_dx);
STARS_MDArgumentRegs.push_back(R_cx);
STARS_MDArgumentRegs.push_back(R_r8);
STARS_MDArgumentRegs.push_back(R_r9);
}
else {
STARS_MDArgumentRegs.clear();
}
return;
}
list<uint16>::iterator GetFirstArgumentReg(void) {
return STARS_MDArgumentRegs.begin();
}
list<uint16>::iterator GetLastArgumentReg(void) {
return STARS_MDArgumentRegs.end();
}
// Are operands equal?
bool IsEqOp(STARSOpndType Opnd1, STARSOpndType Opnd2) {
if (Opnd1.type != Opnd2.type)
return false;
switch (Opnd1.type) {
case o_void: return true;
case o_reg: return ((Opnd1.reg == Opnd2.reg) && (Opnd1.dtyp == Opnd2.dtyp));
case o_mem: return (Opnd1.addr == Opnd2.addr);
case o_phrase: if (Opnd1.hasSIB && Opnd2.hasSIB) return ((Opnd1.sib == Opnd2.sib) && (Opnd1.specflag4 == Opnd2.specflag4));
else if (Opnd1.hasSIB || Opnd2.hasSIB) return false; // no SIB != has SIB
else return (Opnd1.reg == Opnd2.reg); // neither has SIB; compare register, e.g. [ebx] to [edx]
case o_displ: if (Opnd1.hasSIB && Opnd2.hasSIB)
return ((Opnd1.sib == Opnd2.sib) && (Opnd1.addr == Opnd2.addr) && (Opnd1.specflag4 == Opnd2.specflag4));
else if ((!Opnd1.hasSIB) && (!Opnd2.hasSIB))
return ((Opnd1.addr == Opnd2.addr) && (Opnd1.reg == Opnd2.reg));
else return false; // no SIB != has SIB
case o_imm: return (Opnd1.value == Opnd2.value);
case o_far: // fall through to o_near case
case o_near: return (Opnd1.addr == Opnd2.addr);
case o_trreg: // fall through
case o_dbreg: // fall through
case o_crreg: // fall through
case o_fpreg: // fall through
case o_mmxreg: // fall through
case o_xmmreg: return (Opnd1.reg == Opnd2.reg); // no subword regs to deal with
default: SMP_msg("ERROR: Unknown operand type in IsEqOp.\n"); return false;
}; // end switch (Opnd1.type)}
} // end of function IsEqOp()
// Are operands equal, ignoring bitwidth differences for register operands?
bool IsEqOpIgnoreBitwidth(STARSOpndType Opnd1, STARSOpndType Opnd2) {
if (Opnd1.type != Opnd2.type)
return false;
switch (Opnd1.type) {
case o_void: return true;
case o_reg: return (Opnd1.reg == Opnd2.reg);
case o_mem: return (Opnd1.addr == Opnd2.addr);
case o_phrase: if (Opnd1.hasSIB && Opnd2.hasSIB) return ((Opnd1.sib == Opnd2.sib) && (Opnd1.specflag4 == Opnd2.specflag4));
else if (Opnd1.hasSIB || Opnd2.hasSIB) return false; // no SIB != has SIB
else return (Opnd1.reg == Opnd2.reg); // neither has SIB; compare register, e.g. [ebx] to [edx]
case o_displ: if (Opnd1.hasSIB && Opnd2.hasSIB)
return ((Opnd1.sib == Opnd2.sib) && (Opnd1.addr == Opnd2.addr) && (Opnd1.specflag4 == Opnd2.specflag4));
else if ((!Opnd1.hasSIB) && (!Opnd2.hasSIB))
return ((Opnd1.addr == Opnd2.addr) && (Opnd1.reg == Opnd2.reg));
else return false; // no SIB != has SIB
case o_imm: return (Opnd1.value == Opnd2.value);
case o_far: // fall through to o_near case
case o_near: return (Opnd1.addr == Opnd2.addr);
case o_trreg: // fall through
case o_dbreg: // fall through
case o_crreg: // fall through
case o_fpreg: // fall through
case o_mmxreg: // fall through
case o_xmmreg: return (Opnd1.reg == Opnd2.reg); // no subword regs to deal with
default: SMP_msg("ERROR: Unknown operand type in IsEqOpIgnoreBitwidth.\n"); return false;
}; // end switch (Opnd1.type)}
} // end of function IsEqOpIgnoreBitwidth()
// We need to make subword registers equal to their containing registers when we
// do comparisons, so that we will realize that register EAX is killed by a prior DEF
// of register AL, for example, and vice versa. To keep sets ordered strictly,
// we also have to make AL and AH be equal to each other as well as equal to EAX.
#define FIRST_x86_SUBWORD_REG R_al
#define LAST_x86_SUBWORD_REG R_dil
bool MDLessReg(const ushort Reg1, const ushort Reg2) {
ushort SReg1 = MDCanonicalizeSubReg(Reg1);
ushort SReg2 = MDCanonicalizeSubReg(Reg2);
return (SReg1 < SReg2);
} // end of MDLessReg()
bool MDEqReg(const ushort Reg1, const ushort Reg2) {
ushort SReg1 = MDCanonicalizeSubReg(Reg1);
ushort SReg2 = MDCanonicalizeSubReg(Reg2);
return (SReg1 == SReg2);
} // end of MDEqReg()
bool MDLessRegOpnd(const STARSOpndType RegOp1, const STARSOpndType RegOp2) {
ushort SReg1 = MDCanonicalizeSubReg(RegOp1.reg);
ushort SReg2 = MDCanonicalizeSubReg(RegOp2.reg);
return ((SReg1 < SReg2) || ((SReg1 == SReg2) && (RegOp1.dtyp < RegOp2.dtyp)));
} // end of MDLessRegOpnd()
ushort MDCanonicalizeSubReg(const ushort Reg1) {
bool Subword = ((Reg1 >= FIRST_x86_SUBWORD_REG) && (Reg1 <= LAST_x86_SUBWORD_REG));
ushort SReg1 = Reg1;
if (Subword) {
// See enumeration RegNo in intel.hpp.
if (SReg1 < R_ah) // AL, CL, DL or BL
SReg1 -= (R_al - R_ax);
else // AH, CH, DH, BH, SPL, BPL, SIL, DIL
SReg1 -= (R_ah - R_ax);
}
return SReg1;
} // end of MDCanonicalizeSubReg()
#if 0
// If TempOp is a register, call MDCanonicalizeSubReg() on it.
void CanonicalizeOpnd(STARSOpndType &TempOp) {
if (o_reg == TempOp.type) {
uint16 NewReg = MDCanonicalizeSubReg(TempOp.reg);
if (TempOp.reg != NewReg) {
TempOp.reg = NewReg;
TempOp.dtyp = STARS_ISA_dtyp; // set to full reg width
}
}
}
#else
// If TempOp is a register, call MDCanonicalizeSubReg() on it.
void CanonicalizeOpnd(STARSOpndType &TempOp) {
if (o_reg == TempOp.type) {
if (4 > GetOpDataSize(TempOp)) {
TempOp.reg = MDCanonicalizeSubReg(TempOp.reg);
TempOp.dtyp = dt_dword; // set to normal reg width
}
}
}
#endif
bool MDIsStackOrFramePointerReg(STARSOpndType RegOp, bool UseFP) {
bool PtrReg = false;
if (o_reg == RegOp.type) {
PtrReg = RegOp.is_reg(MD_STACK_POINTER_REG) || (UseFP && RegOp.is_reg(MD_FRAME_POINTER_REG));
}
return PtrReg;
}
// In SSA computations, we are storing the GlobalNames index into the op_t fields
// n, offb, and offo. This function extracts an unsigned int from these three 8-bit
// fields.
unsigned int ExtractGlobalIndex(STARSOpndType GlobalOp) {
unsigned int index = 0;
index |= (((unsigned int) GlobalOp.offo) & 0x000000ff);
index <<= 8;
index |= (((unsigned int) GlobalOp.offb) & 0x000000ff);
index <<= 8;
index |= (((unsigned int) GlobalOp.n) & 0x000000ff);
return index;
}
void SetGlobalIndex(STARSOpndType *TempOp, size_t index) {
TempOp->n = (char) (index & 0x000000ff);
TempOp->offb = (char) ((index & 0x0000ff00) >> 8);
TempOp->offo = (char) ((index & 0x00ff0000) >> 16);
return;
}
bool MD_STARS_op256(const STARSOpndType &x) // is VEX.L set?
{
return ((x.specflag4 & STARS_VEXPR) != 0) && ((x.specflag4 & VEX_L) != 0);
}
bool MD_STARS_is_vsib(const STARSOpndType &x) // does instruction use VSIB variant of the sib byte?
{
return ((x.specflag4 & STARS_VSIB) != 0);
}
int MD_STARS_sib_base(const STARSOpndType &x) // get extended sib base
{
int base = x.sib & 7;
#ifdef __EA64__
if ( x.specflag4 & REX_B )
base |= 8;
#endif
return base;
}
regnum_t MD_STARS_sib_index(const STARSOpndType &x) // get extended sib index
{
regnum_t index = regnum_t((x.sib >> 3) & 7);
#ifdef __EA64__
if ( x.specflag4 & REX_X )
index |= 8;
#endif
if (MD_STARS_is_vsib(x))
index += MD_STARS_op256(x) ? 81 /*R_ymm0*/ : 64 /*R_xmm0*/;
return index;
}
// Return true if CurrOp could be an indirect memory reference.
bool MDIsIndirectMemoryOpnd(STARSOpndType CurrOp, bool UseFP) {
bool indirect = false;
if ((CurrOp.type != o_mem) && (CurrOp.type != o_phrase) && (CurrOp.type != o_displ))
return false;
if (CurrOp.hasSIB) {
int BaseReg = MD_STARS_sib_base(CurrOp);
short IndexReg = MD_STARS_sib_index(CurrOp);
if ((R_none != IndexReg) && (MD_STACK_POINTER_REG != IndexReg)) {
if ((MD_FRAME_POINTER_REG == IndexReg) && UseFP)
;
else
indirect = true;
}
if (0 != sib_scale(CurrOp))
indirect = true;
if (R_none != BaseReg) {
if ((BaseReg == MD_FRAME_POINTER_REG) && (CurrOp.type == o_mem)) {
; // EBP ==> no base register for o_mem type
}
else if ((BaseReg == MD_FRAME_POINTER_REG) && UseFP)
; // EBP used as frame pointer for direct access
else if (BaseReg == MD_STACK_POINTER_REG)
; // ESP used as stack pointer for direct access
else
indirect = true; // conservative; some register used for addressing
// other than a stack or frame pointer
}
} // end if hasSIB
else { // no SIB; can have base register only
ushort BaseReg = CurrOp.reg;
if (CurrOp.type == o_mem) { // no base register for o_mem
if (!((0 == BaseReg) || (MD_FRAME_POINTER_REG == BaseReg))) {
SMP_msg("base reg %d ignored \n", BaseReg);
}
}
else if ((BaseReg == MD_FRAME_POINTER_REG) && UseFP)
; // EBP used as frame pointer for direct access
else if (BaseReg == MD_STACK_POINTER_REG)
; // ESP used as stack pointer for direct access
else {
indirect = true;
}
}
return indirect;
} // end MDIsIndirectMemoryOpnd()
// Extract the base and index registers and scale factor and displacement from the
// memory operand.
void MDExtractAddressFields(STARSOpndType MemOp, int &BaseReg, int &IndexReg, ushort &Scale, ea_t &Offset) {
assert((MemOp.type == o_phrase) || (MemOp.type == o_displ) || (MemOp.type == o_mem));
Scale = 0;
BaseReg = R_none;
IndexReg = R_none;
Offset = MemOp.addr;
if (MemOp.hasSIB) {
BaseReg = MD_STARS_sib_base(MemOp);
IndexReg = (int) MD_STARS_sib_index(MemOp);
if (MD_STACK_POINTER_REG == IndexReg) // signifies no index register
IndexReg = R_none;
if (R_none != IndexReg) {
Scale = (ushort) sib_scale(MemOp);
}
if (R_none != BaseReg) {
if ((BaseReg == MD_FRAME_POINTER_REG) && (MemOp.type == o_mem)) {
BaseReg = R_none;
// **!!** BaseReg allowed for o_mem with SIB byte???
}
}
}
else { // no SIB byte; can have base reg but no index reg or scale factor
BaseReg = (int) MemOp.reg; // cannot be R_none for no SIB case
if (MemOp.type == o_mem) {
BaseReg = R_none; // no Base register for o_mem operands
}
}
return;
} // end of MDExtractAddressFields()
// Is CurrOp a memory operand?
bool IsMemOperand(STARSOpndType CurrOp) {
return ((o_mem == CurrOp.type) || (o_displ == CurrOp.type) || (o_phrase == CurrOp.type));
}
// MACHINE DEPENDENT: Is CurrOp the flags register?
bool MDIsFlagsReg(STARSOpndType CurrOp) {
return ((o_reg == CurrOp.type) && CurrOp.is_reg(X86_FLAGS_REG));
}
// MACHINE DEPENDENT: Is register a stack pointer or frame pointer?
bool MDIsStackPtrReg(int RegNumber, bool UseFP) {
return ((RegNumber == MD_STACK_POINTER_REG) || (UseFP && (RegNumber == MD_FRAME_POINTER_REG)));
}
// MACHINE DEPENDENT: Is operand a stack memory access?
bool MDIsStackAccessOpnd(STARSOpndType CurrOp, bool UseFP) {
int BaseReg;
int IndexReg;
ushort ScaleFactor;
ea_t offset;
if ((o_displ != CurrOp.type) && (o_phrase != CurrOp.type)) {
return false;
}
MDExtractAddressFields(CurrOp, BaseReg, IndexReg, ScaleFactor, offset);
return MDIsStackPtrReg(BaseReg, UseFP);
} // end of MDIsStackAccessOpnd()
// MACHINE DEPENDENT: Is operand a direct stack memory access?
bool MDIsDirectStackAccessOpnd(STARSOpndType CurrOp, bool UseFP) {
int BaseReg;
int IndexReg;
ushort ScaleFactor;
ea_t offset;
if ((o_displ != CurrOp.type) && (o_phrase != CurrOp.type)) {
return false;
}
MDExtractAddressFields(CurrOp, BaseReg, IndexReg, ScaleFactor, offset);
// When the IndexReg is
return (MDIsStackPtrReg(BaseReg, UseFP) && (IndexReg == R_none));
} // end of MDIsDirectStackAccessOpnd()
// MACHINE DEPENDENT: Is operand trackable in data flow analyses (i.e. a direct stack memory access or a register?)
bool MDIsDataFlowOpnd(STARSOpndType CurrOp, bool UseFP) {
return ((o_reg == CurrOp.type) || MDIsDirectStackAccessOpnd(CurrOp, UseFP));
}
// MACHINE DEPENDENT: Is operand a caller-saved register?
bool MDIsCallerSavedReg(STARSOpndType CurrOp) {
if (o_reg != CurrOp.type)
return false;
ushort CurrReg = MDCanonicalizeSubReg(CurrOp.reg);
return ((R_ax == CurrReg) || (R_cx == CurrReg) || (R_dx == CurrReg));
} // end of MDIsCallerSavedReg()
// DEBUG Print DEF and/or USE for an operand.
void PrintDefUse(ulong feature, int OpNum) {
// CF_ macros number the operands from 1 to 6, while OpNum
// is a 0 to 5 index into the insn_t.Operands[] array.
// OpNum == -1 is a signal that this is a DEF or USE or VarKillSet etc.
// operand and not an instruction operand.
if (-1 == OpNum)
return;
switch (OpNum) {
case 0:
if (feature & CF_CHG1)
SMP_msg(" DEF");
if (feature & CF_USE1)
SMP_msg(" USE");
break;
case 1:
if (feature & CF_CHG2)
SMP_msg(" DEF");
if (feature & CF_USE2)
SMP_msg(" USE");
break;
case 2:
if (feature & CF_CHG3)
SMP_msg(" DEF");
if (feature & CF_USE3)
SMP_msg(" USE");
break;
case 3:
if (feature & CF_CHG4)
SMP_msg(" DEF");
if (feature & CF_USE4)
SMP_msg(" USE");
break;
case 4:
if (feature & CF_CHG5)
SMP_msg(" DEF");
if (feature & CF_USE5)
SMP_msg(" USE");
break;
case 5:
if (feature & CF_CHG6)
SMP_msg(" DEF");
if (feature & CF_USE6)
SMP_msg(" USE");
break;
}
return;
} // end PrintDefUse()
// DEBUG print SIB info for an operand.
void PrintSIB(STARSOpndType Opnd) {
int BaseReg;
int IndexReg;
ushort ScaleFactor;
ea_t offset;
#define NAME_LEN 5
char BaseName[NAME_LEN] = {'N', 'o', 'n', 'e', '\0'};
char IndexName[NAME_LEN] = {'N', 'o', 'n', 'e', '\0'};
MDExtractAddressFields(Opnd, BaseReg, IndexReg, ScaleFactor, offset);
if (BaseReg != R_none)
SMP_strncpy(BaseName, RegNames[BaseReg], NAME_LEN - 1);
if (IndexReg != R_none) {
SMP_strncpy(IndexName, RegNames[IndexReg], NAME_LEN -1);
}
SMP_msg(" Base %s Index %s Scale %d Flag4 %d", BaseName, IndexName, ScaleFactor, Opnd.specflag4);
} // end PrintSIB()
// Annotations: concisely print SIB info for an operand.
void AnnotPrintSIB(STARSOpndType Opnd, bool HasOffset, FILE *OutFile) {
int BaseReg;
int IndexReg;
ushort ScaleFactor;
ea_t offset;
char OutString[MAXSTR] = {'[', '\0'};
char ScaleString[4];
STARSOpndType BaseOp = InitOp, IndexOp = InitOp;
BaseOp.type = o_reg;
IndexOp.type = o_reg;
#if 0
BaseOp.dtyp = Opnd.dtyp;
IndexOp.dtyp = Opnd.dtyp;
#endif
MDExtractAddressFields(Opnd, BaseReg, IndexReg, ScaleFactor, offset);
if (ScaleFactor > 0) {
ScaleFactor = 1 << (ScaleFactor - 1);
(void) SMP_snprintf(ScaleString, 4, "%d", ScaleFactor);
}
if (BaseReg != R_none) {
BaseOp.reg = BaseReg;
if (RegSizes[BaseReg] == 1)
BaseOp.dtyp = dt_byte;
(void) SMP_strncat(OutString, MDGetRegName(BaseOp), MAXSTR-1);
if (IndexReg != R_none) {
IndexOp.reg = IndexReg;
if (RegSizes[IndexReg] == 1)
IndexOp.dtyp = dt_byte;
(void) SMP_strncat(OutString, "+", MAXSTR-1);
(void) SMP_strncat(OutString, MDGetRegName(IndexOp), MAXSTR-1);
if (ScaleFactor > 0) {
(void) SMP_strncat(OutString, "*", MAXSTR-1);
(void) SMP_strncat(OutString, ScaleString, MAXSTR-1);
}
}
}
else if (IndexReg != R_none) {
IndexOp.reg = IndexReg;
if (RegSizes[IndexReg] == 1)
IndexOp.dtyp = dt_byte;
(void) SMP_strncat(OutString, MDGetRegName(IndexOp), MAXSTR-1);
if (ScaleFactor > 0) {
(void) SMP_strncat(OutString, "*", MAXSTR-1);
(void) SMP_strncat(OutString, ScaleString, MAXSTR-1);
}
}
else {
SMP_msg("ERROR: No BaseReg, no IndexReg in SIB\n");
}
if (!HasOffset) // can close the brackets around regs
(void) SMP_strncat(OutString, "]", MAXSTR-1);
SMP_fprintf(OutFile, " %s", OutString);
} // end AnnotPrintSIB()
// Annotations: concisely print SIB info for an operand.
void SPARKAnnotPrintSIB(STARSOpndType Opnd, bool HasOffset, FILE *OutFile, uint16 SegReg, bool UseFP) {
int BaseReg;
int IndexReg;
ushort ScaleFactor;
ea_t offset;
char OutString[MAXSTR] = {'(', '\0'};
char ScaleString[4];
STARSOpndType BaseOp = InitOp, IndexOp = InitOp;
BaseOp.type = o_reg;
IndexOp.type = o_reg;
#if 0
BaseOp.dtyp = Opnd.dtyp;
IndexOp.dtyp = Opnd.dtyp;
#endif
MDExtractAddressFields(Opnd, BaseReg, IndexReg, ScaleFactor, offset);
bool SegRegPrefix = is_segreg((int) SegReg);
if (SegRegPrefix) {
// Emit segment register string unless it is just the stack segment plus a stack operand,
// where the stack segment is implied anyway.
if ((SegReg == R_ss) && MDIsStackAccessOpnd(Opnd, UseFP)) {
SegRegPrefix = false;
}
else {
STARSOpndType SegRegOp = InitOp;
SegRegOp.type = o_reg;
SegRegOp.reg = SegReg;
(void) SMP_strncat(OutString, "X86.", MAXSTR-1);
(void) SMP_strncat(OutString, MDGetRegName(SegRegOp), MAXSTR-1);
}
}
if (ScaleFactor > 0) {
ScaleFactor = 1 << (ScaleFactor - 1);
(void) SMP_snprintf(ScaleString, 4, "%d", ScaleFactor);
}
if (BaseReg != R_none) {
if (SegRegPrefix) {
(void) SMP_strncat(OutString, " + ", MAXSTR-1);
}
BaseOp.reg = BaseReg;
if (RegSizes[BaseReg] == 1)
BaseOp.dtyp = dt_byte;
(void) SMP_strncat(OutString, "X86.", MAXSTR-1);
(void) SMP_strncat(OutString, MDGetRegName(BaseOp), MAXSTR-1);
if (STARS_ISA_Bytewidth > GetOpDataSize(BaseOp)) {
++SubwordAddressRegCount;
}
if (IndexReg != R_none) {
IndexOp.reg = IndexReg;
if (RegSizes[IndexReg] == 1)
IndexOp.dtyp = dt_byte;
(void) SMP_strncat(OutString, " + ", MAXSTR-1);
(void) SMP_strncat(OutString, "X86.", MAXSTR-1);
(void) SMP_strncat(OutString, MDGetRegName(IndexOp), MAXSTR-1);
if (STARS_ISA_Bytewidth > GetOpDataSize(IndexOp)) {
++SubwordAddressRegCount;
}
if (ScaleFactor > 0) {
(void) SMP_strncat(OutString, "*", MAXSTR-1);
(void) SMP_strncat(OutString, ScaleString, MAXSTR-1);
}
}
}
else if (IndexReg != R_none) {
if (SegRegPrefix) {
(void) SMP_strncat(OutString, " + ", MAXSTR-1);
}
IndexOp.reg = IndexReg;
if (RegSizes[IndexReg] == 1)
IndexOp.dtyp = dt_byte;
(void) SMP_strncat(OutString, "X86.", MAXSTR-1);
(void) SMP_strncat(OutString, MDGetRegName(IndexOp), MAXSTR-1);
if (STARS_ISA_Bytewidth > GetOpDataSize(IndexOp)) {
++SubwordAddressRegCount;
}
if (ScaleFactor > 0) {
(void) SMP_strncat(OutString, "*", MAXSTR-1);
(void) SMP_strncat(OutString, ScaleString, MAXSTR-1);
}
}
else if (!SegRegPrefix) {
SMP_msg("ERROR: No BaseReg, no IndexReg in SIB\n");
}
if (!HasOffset) // can close the parens around regs
(void) SMP_strncat(OutString, ")", MAXSTR-1);
SMP_fprintf(OutFile, " %s", OutString);
} // end SPARKAnnotPrintSIB()
// Debug: print one operand from an instruction or DEF or USE list.
void PrintOneOperand(STARSOpndType Opnd, uint32 features, int OpNum) {
if (Opnd.type != o_void) {
PrintOperand(Opnd);
PrintDefUse(features, OpNum);
}
return;
} // end of PrintOneOperand()
// Debug: print one operand.
void PrintOperand(STARSOpndType Opnd) {
if (Opnd.type == o_void)
return;
else if (Opnd.type == o_mem) {
SMP_msg(" Operand: memory : addr: %lx", (unsigned long) Opnd.addr);
if (Opnd.hasSIB) {
PrintSIB(Opnd);
}
}
else if (Opnd.type == o_phrase) {
SMP_msg(" Operand: memory phrase :");
if (Opnd.hasSIB) { // has SIB info
PrintSIB(Opnd);
}
else { // no SIB info
ushort BaseReg = Opnd.phrase;
SMP_msg(" reg %s", RegNames[BaseReg]);
}
if (Opnd.addr != 0) {
SMP_msg(" \n WARNING: addr for o_phrase type: %lx\n", (unsigned long) Opnd.addr);
}
}
else if (Opnd.type == o_displ) {
SMP_msg(" Operand: memory displ :");
ea_t offset = Opnd.addr;
int SignedOffset = (int) offset;
if (Opnd.hasSIB) {
PrintSIB(Opnd);
SMP_msg(" displ %d", SignedOffset);
}
else {
ushort BaseReg = Opnd.reg;
SMP_msg(" reg %s displ %d", RegNames[BaseReg], SignedOffset);
}
}
else if (Opnd.type == o_reg) {
SMP_msg(" Operand: register %s", MDGetRegName(Opnd));
}
else if (Opnd.type == o_imm) {
SMP_msg(" Operand: immed %ld", (long) Opnd.value);
}
else if (Opnd.type == o_far) {
SMP_msg(" Operand: FarPtrImmed addr: %lx", (unsigned long) Opnd.addr);
}
else if (Opnd.type == o_near) {
SMP_msg(" Operand: NearPtrImmed addr: %lx", (unsigned long) Opnd.addr);
}
else if (Opnd.type == o_trreg) {
SMP_msg(" Operand: TaskReg reg: %d", Opnd.reg);
}
else if (Opnd.type == o_dbreg) {
SMP_msg(" Operand: DebugReg reg: %d", Opnd.reg);
}
else if (Opnd.type == o_crreg) {
SMP_msg(" Operand: ControlReg reg: %d", Opnd.reg);
}
else if (Opnd.type == o_fpreg) {
SMP_msg(" Operand: FloatReg reg: %d", Opnd.reg);
}
else if (Opnd.type == o_mmxreg) {
SMP_msg(" Operand: MMXReg reg: %d", Opnd.reg);
}
else if (Opnd.type == o_xmmreg) {
SMP_msg(" Operand: XMMReg reg: %d", Opnd.reg);
}
else {
SMP_msg(" Operand: unknown");
}
#if STARS_DEBUG_DUMP_IDENTIFY_HIDDEN_OPERANDS
if (!(Opnd.showed()))
SMP_msg(" HIDDEN ");
#endif
return;
} // end of PrintOperand()
// Print an operand that has no features flags or operand position number, such
// as the op_t types found in lists and sets throughout the blocks, phi functions, etc.
void PrintListOperand(STARSOpndType Opnd, int SSANum) {
if (Opnd.type != o_void) {
PrintOperand(Opnd);
SMP_msg(" SSANum: %d ", SSANum);
}
return;
} // end of PrintListOperand()
// Annotations: concisely print one operand.
void AnnotPrintOperand(STARSOpndType Opnd, FILE *OutFile) {
STARSOpndType BaseOp = InitOp;
STARSOpndType IndexOp = InitOp;
BaseOp.type = o_reg;
IndexOp.type = o_reg;
#if 0
BaseOp.dtyp = Opnd.dtyp;
IndexOp.dtyp = Opnd.dtyp;
#endif
if (Opnd.type == o_mem) {
SMP_fprintf(OutFile, " %lx", (unsigned long) Opnd.addr);
if (Opnd.hasSIB) {
AnnotPrintSIB(Opnd, false, OutFile);
}
}
else if (Opnd.type == o_phrase) {
if (Opnd.hasSIB) { // has SIB info
AnnotPrintSIB(Opnd, false, OutFile);
}
else { // no SIB info
ushort BaseReg = Opnd.phrase;
BaseOp.reg = BaseReg;
if (RegSizes[BaseReg] == 1)
BaseOp.dtyp = dt_byte;
SMP_fprintf(OutFile, " [%s]", MDGetRegName(BaseOp));
}
if (Opnd.addr != 0) {
SMP_msg(" \n WARNING: addr for o_phrase type: %lx\n", (unsigned long) Opnd.addr);
}
}
else if (Opnd.type == o_displ) {
ea_t offset = Opnd.addr;
int SignedOffset = (int) offset;
if (Opnd.hasSIB) {
AnnotPrintSIB(Opnd, (SignedOffset != 0), OutFile);
if (SignedOffset > 0) // print plus sign
SMP_fprintf(OutFile, "+%d]", SignedOffset);
else if (SignedOffset < 0) // minus sign will print automatically
SMP_fprintf(OutFile, "%d]", SignedOffset);
}
else {
ushort BaseReg = Opnd.reg;
BaseOp.reg = BaseReg;
if (RegSizes[BaseReg] == 1)
BaseOp.dtyp = dt_byte;
if (SignedOffset >= 0) // print plus sign
SMP_fprintf(OutFile, " [%s+%d]", MDGetRegName(BaseOp), SignedOffset);
else // minus sign will print automatically
SMP_fprintf(OutFile, " [%s%d]", MDGetRegName(BaseOp), SignedOffset);
}
}
else if (Opnd.type == o_reg) {
SMP_fprintf(OutFile, " %s", MDGetRegName(Opnd));
}
else if (Opnd.type == o_imm) {
SMP_fprintf(OutFile, " %ld", (long) Opnd.value);
}
else if ((Opnd.type == o_far) || (Opnd.type == o_near)) {
SMP_fprintf(OutFile, " %lx", (unsigned long) Opnd.addr);
}
else {
SMP_fprintf(OutFile, " ERROROP");
}
return;
} // end of AnnotPrintOperand()
// Print opcode string.
void PrintOpcode(uint16 opcode, FILE *OutFile) {
switch (opcode) {
case NN_null: // Unknown Operation
case NN_aaa: // ASCII Adjust after Addition
case NN_aad: // ASCII Adjust AX before Division
case NN_aam: // ASCII Adjust AX after Multiply
case NN_aas: // ASCII Adjust AL after Subtraction
case NN_adc: // Add with Carry
SMP_fprintf(OutFile, "ERROR");
break;
case NN_add: // Add
SMP_fprintf(OutFile, "add");
break;
case NN_and: // Logical AND
SMP_fprintf(OutFile, "and");
break;
case NN_arpl: // Adjust RPL Field of Selector
case NN_bound: // Check Array Index Against Bounds
case NN_bsf: // Bit Scan Forward
case NN_bsr: // Bit Scan Reverse
case NN_bt: // Bit Test
case NN_btc: // Bit Test and Complement
case NN_btr: // Bit Test and Reset
case NN_bts: // Bit Test and Set
SMP_fprintf(OutFile, "ERROR");
break;
case NN_call: // Call Procedure
case NN_callfi: // Indirect Call Far Procedure
case NN_callni: // Indirect Call Near Procedure
SMP_fprintf(OutFile, "");
break;
case NN_cbw: // AL -> AX (with sign)
case NN_cwde: // AX -> EAX (with sign)
case NN_cdqe: // EAX -> RAX (with sign)
case NN_clc: // Clear Carry Flag
case NN_cld: // Clear Direction Flag
case NN_cli: // Clear Interrupt Flag
case NN_clts: // Clear Task-Switched Flag in CR0
case NN_cmc: // Complement Carry Flag
case NN_cmp: // Compare Two Operands
case NN_cmps: // Compare Strings
case NN_cwd: // AX -> DX:AX (with sign)
case NN_cdq: // EAX -> EDX:EAX (with sign)
case NN_cqo: // RAX -> RDX:RAX (with sign)
case NN_daa: // Decimal Adjust AL after Addition
case NN_das: // Decimal Adjust AL after Subtraction
SMP_fprintf(OutFile, "ERROR");
break;
case NN_dec: // Decrement by 1
SMP_fprintf(OutFile, "sub");
break;
case NN_div: // Unsigned Divide
SMP_fprintf(OutFile, "div");
break;
case NN_enterw: // Make Stack Frame for Procedure Parameters
case NN_enter: // Make Stack Frame for Procedure Parameters
case NN_enterd: // Make Stack Frame for Procedure Parameters
case NN_enterq: // Make Stack Frame for Procedure Parameters
SMP_fprintf(OutFile, "ERROR");
break;
case NN_hlt: // Halt
SMP_fprintf(OutFile, "ERROR");
break;
case NN_idiv: // Signed Divide
SMP_fprintf(OutFile, "div");
break;
case NN_imul: // Signed Multiply
SMP_fprintf(OutFile, "mul");
break;
case NN_in: // Input from Port
SMP_fprintf(OutFile, "ERROR");
break;
case NN_inc: // Increment by 1
SMP_fprintf(OutFile, "add");
break;
case NN_ins: // Input Byte(s) from Port to String
case NN_int: // Call to Interrupt Procedure
case NN_into: // Call to Interrupt Procedure if Overflow Flag = 1
case NN_int3: // Trap to Debugger
case NN_iretw: // Interrupt Return
case NN_iret: // Interrupt Return
case NN_iretd: // Interrupt Return (use32)
case NN_iretq: // Interrupt Return (use64)
SMP_fprintf(OutFile, "ERROR");
break;
case NN_ja: // Jump if Above (CF=0 & ZF=0)
case NN_jae: // Jump if Above or Equal (CF=0)
case NN_jb: // Jump if Below (CF=1)
case NN_jbe: // Jump if Below or Equal (CF=1 | ZF=1)
case NN_jc: // Jump if Carry (CF=1)
case NN_jcxz: // Jump if CX is 0
case NN_jecxz: // Jump if ECX is 0
case NN_jrcxz: // Jump if RCX is 0
case NN_je: // Jump if Equal (ZF=1)
case NN_jg: // Jump if Greater (ZF=0 & SF=OF)
case NN_jge: // Jump if Greater or Equal (SF=OF)
case NN_jl: // Jump if Less (SF!=OF)
case NN_jle: // Jump if Less or Equal (ZF=1 | SF!=OF)
case NN_jna: // Jump if Not Above (CF=1 | ZF=1)
case NN_jnae: // Jump if Not Above or Equal (CF=1)
case NN_jnb: // Jump if Not Below (CF=0)
case NN_jnbe: // Jump if Not Below or Equal (CF=0 & ZF=0)
case NN_jnc: // Jump if Not Carry (CF=0)
case NN_jne: // Jump if Not Equal (ZF=0)
case NN_jng: // Jump if Not Greater (ZF=1 | SF!=OF)
case NN_jnge: // Jump if Not Greater or Equal (ZF=1)
case NN_jnl: // Jump if Not Less (SF=OF)
case NN_jnle: // Jump if Not Less or Equal (ZF=0 & SF=OF)
case NN_jno: // Jump if Not Overflow (OF=0)
case NN_jnp: // Jump if Not Parity (PF=0)
case NN_jns: // Jump if Not Sign (SF=0)
case NN_jnz: // Jump if Not Zero (ZF=0)
case NN_jo: // Jump if Overflow (OF=1)
case NN_jp: // Jump if Parity (PF=1)
case NN_jpe: // Jump if Parity Even (PF=1)
case NN_jpo: // Jump if Parity Odd (PF=0)
case NN_js: // Jump if Sign (SF=1)
case NN_jz: // Jump if Zero (ZF=1)
case NN_jmp: // Jump
case NN_jmpfi: // Indirect Far Jump
case NN_jmpni: // Indirect Near Jump
case NN_jmpshort: // Jump Short (not used)
SMP_fprintf(OutFile, "ERROR");
break;
case NN_lahf: // Load Flags into AH Register
case NN_lar: // Load Access Right Byte
SMP_fprintf(OutFile, "ERROR");
break;
case NN_lea: // Load Effective Address
SMP_fprintf(OutFile, "lea");
break;
case NN_leavew: // High Level Procedure Exit
case NN_leave: // High Level Procedure Exit
case NN_leaved: // High Level Procedure Exit
case NN_leaveq: // High Level Procedure Exit
SMP_fprintf(OutFile, "ERROR");
break;
case NN_lgdt: // Load Global Descriptor Table Register
case NN_lidt: // Load Interrupt Descriptor Table Register
case NN_lgs: // Load Full Pointer to GS:xx
case NN_lss: // Load Full Pointer to SS:xx
case NN_lds: // Load Full Pointer to DS:xx
case NN_les: // Load Full Pointer to ES:xx
case NN_lfs: // Load Full Pointer to FS:xx
case NN_lldt: // Load Local Descriptor Table Register
case NN_lmsw: // Load Machine Status Word
case NN_lock: // Assert LOCK# Signal Prefix
SMP_fprintf(OutFile, "ERROR");
break;
case NN_lods: // Load String
SMP_fprintf(OutFile, "ERROR");
break;
case NN_loopw: // Loop while ECX != 0
case NN_loop: // Loop while CX != 0
case NN_loopd: // Loop while ECX != 0
case NN_loopq: // Loop while RCX != 0
case NN_loopwe: // Loop while CX != 0 and ZF=1
case NN_loope: // Loop while rCX != 0 and ZF=1
case NN_loopde: // Loop while ECX != 0 and ZF=1
case NN_loopqe: // Loop while RCX != 0 and ZF=1
case NN_loopwne: // Loop while CX != 0 and ZF=0
case NN_loopne: // Loop while rCX != 0 and ZF=0
case NN_loopdne: // Loop while ECX != 0 and ZF=0
case NN_loopqne: // Loop while RCX != 0 and ZF=0
SMP_fprintf(OutFile, "ERROR");
break;
case NN_lsl: // Load Segment Limit
case NN_ltr: // Load Task Register
SMP_fprintf(OutFile, "ERROR");
break;
case NN_mov: // Move Data
SMP_fprintf(OutFile, "mov");
break;
case NN_movsp: // Move to/from Special Registers
SMP_fprintf(OutFile, "ERROR");
break;
case NN_movs: // Move Byte(s) from String to String
SMP_fprintf(OutFile, "ERROR");
break;
case NN_movsx: // Move with Sign-Extend
SMP_fprintf(OutFile, "movsx");
break;
case NN_movzx: // Move with Zero-Extend
SMP_fprintf(OutFile, "movzx");
break;
case NN_mul: // Unsigned Multiplication of AL or AX
SMP_fprintf(OutFile, "mul");
break;
case NN_neg: // Two's Complement Negation
SMP_fprintf(OutFile, "ERROR");
break;
case NN_nop: // No Operation
SMP_fprintf(OutFile, "");
break;
case NN_not: // One's Complement Negation
SMP_fprintf(OutFile, "not");
break;
case NN_or: // Logical Inclusive OR
SMP_fprintf(OutFile, "or");
break;
case NN_out: // Output to Port
case NN_outs: // Output Byte(s) to Port
SMP_fprintf(OutFile, "ERROR");
break;
case NN_pop: // Pop a word from the Stack
SMP_fprintf(OutFile, "pop");
break;
case NN_popaw: // Pop all General Registers
case NN_popa: // Pop all General Registers
case NN_popad: // Pop all General Registers (use32)
case NN_popaq: // Pop all General Registers (use64)
case NN_popfw: // Pop Stack into Flags Register
case NN_popf: // Pop Stack into Flags Register
case NN_popfd: // Pop Stack into Eflags Register
case NN_popfq: // Pop Stack into Rflags Register
SMP_fprintf(OutFile, "ERROR");
break;
case NN_push: // Push Operand onto the Stack
SMP_fprintf(OutFile, "push");
break;
case NN_pushaw: // Push all General Registers
case NN_pusha: // Push all General Registers
case NN_pushad: // Push all General Registers (use32)
case NN_pushaq: // Push all General Registers (use64)
case NN_pushfw: // Push Flags Register onto the Stack
case NN_pushf: // Push Flags Register onto the Stack
case NN_pushfd: // Push Flags Register onto the Stack (use32)
case NN_pushfq: // Push Flags Register onto the Stack (use64)
SMP_fprintf(OutFile, "ERROR");
break;
case NN_rcl: // Rotate Through Carry Left
case NN_rcr: // Rotate Through Carry Right
case NN_rol: // Rotate Left
case NN_ror: // Rotate Right
SMP_fprintf(OutFile, "ERROR");
break;
case NN_rep: // Repeat String Operation
case NN_repe: // Repeat String Operation while ZF=1
case NN_repne: // Repeat String Operation while ZF=0
SMP_fprintf(OutFile, "ERROR");
break;
case NN_retn: // Return Near from Procedure
case NN_retf: // Return Far from Procedure
SMP_fprintf(OutFile, "return");
break;
case NN_sahf: // Store AH into Flags Register
SMP_fprintf(OutFile, "ERROR");
break;
case NN_sal: // Shift Arithmetic Left
SMP_fprintf(OutFile, "sal");
break;
case NN_sar: // Shift Arithmetic Right
SMP_fprintf(OutFile, "sar");
break;
case NN_shl: // Shift Logical Left
SMP_fprintf(OutFile, "shl");
break;
case NN_shr: // Shift Logical Right
SMP_fprintf(OutFile, "shr");
break;
case NN_sbb: // Integer Subtraction with Borrow
SMP_fprintf(OutFile, "ERROR");
break;
case NN_scas: // Compare String
SMP_fprintf(OutFile, "ERROR");
break;
case NN_seta: // Set Byte if Above (CF=0 & ZF=0)
case NN_setae: // Set Byte if Above or Equal (CF=0)
case NN_setb: // Set Byte if Below (CF=1)
case NN_setbe: // Set Byte if Below or Equal (CF=1 | ZF=1)
case NN_setc: // Set Byte if Carry (CF=1)
case NN_sete: // Set Byte if Equal (ZF=1)
case NN_setg: // Set Byte if Greater (ZF=0 & SF=OF)
case NN_setge: // Set Byte if Greater or Equal (SF=OF)
case NN_setl: // Set Byte if Less (SF!=OF)
case NN_setle: // Set Byte if Less or Equal (ZF=1 | SF!=OF)
case NN_setna: // Set Byte if Not Above (CF=1 | ZF=1)
case NN_setnae: // Set Byte if Not Above or Equal (CF=1)
case NN_setnb: // Set Byte if Not Below (CF=0)
case NN_setnbe: // Set Byte if Not Below or Equal (CF=0 & ZF=0)
case NN_setnc: // Set Byte if Not Carry (CF=0)
case NN_setne: // Set Byte if Not Equal (ZF=0)
case NN_setng: // Set Byte if Not Greater (ZF=1 | SF!=OF)
case NN_setnge: // Set Byte if Not Greater or Equal (ZF=1)
case NN_setnl: // Set Byte if Not Less (SF=OF)
case NN_setnle: // Set Byte if Not Less or Equal (ZF=0 & SF=OF)
case NN_setno: // Set Byte if Not Overflow (OF=0)
case NN_setnp: // Set Byte if Not Parity (PF=0)
case NN_setns: // Set Byte if Not Sign (SF=0)
case NN_setnz: // Set Byte if Not Zero (ZF=0)
case NN_seto: // Set Byte if Overflow (OF=1)
case NN_setp: // Set Byte if Parity (PF=1)
case NN_setpe: // Set Byte if Parity Even (PF=1)
case NN_setpo: // Set Byte if Parity Odd (PF=0)
case NN_sets: // Set Byte if Sign (SF=1)
case NN_setz: // Set Byte if Zero (ZF=1)
SMP_fprintf(OutFile, "ERROR");
break;
case NN_sgdt: // Store Global Descriptor Table Register
case NN_sidt: // Store Interrupt Descriptor Table Register
SMP_fprintf(OutFile, "ERROR");
break;
case NN_shld: // Double Precision Shift Left
case NN_shrd: // Double Precision Shift Right
SMP_fprintf(OutFile, "ERROR");
break;
case NN_sldt: // Store Local Descriptor Table Register
case NN_smsw: // Store Machine Status Word
case NN_stc: // Set Carry Flag
case NN_std: // Set Direction Flag
case NN_sti: // Set Interrupt Flag
SMP_fprintf(OutFile, "ERROR");
break;
case NN_stos: // Store String
case NN_str: // Store Task Register
SMP_fprintf(OutFile, "ERROR");
break;
case NN_sub: // Integer Subtraction
SMP_fprintf(OutFile, "sub");
break;
case NN_test: // Logical Compare
SMP_fprintf(OutFile, "test");
break;
case NN_verr: // Verify a Segment for Reading
case NN_verw: // Verify a Segment for Writing
case NN_wait: // Wait until BUSY# Pin is Inactive (HIGH)
SMP_fprintf(OutFile, "ERROR");
break;
case NN_xchg: // Exchange Register/Memory with Register
case NN_xlat: // Table Lookup Translation
SMP_fprintf(OutFile, "ERROR");
break;
case NN_xor: // Logical Exclusive OR
SMP_fprintf(OutFile, "xor");
break;
//
// 486 instructions
//
case NN_cmpxchg: // Compare and Exchange
case NN_bswap: // Swap bits in EAX
case NN_xadd: // t<-dest; dest<-src+dest; src<-t
case NN_invd: // Invalidate Data Cache
case NN_wbinvd: // Invalidate Data Cache (write changes)
case NN_invlpg: // Invalidate TLB entry
SMP_fprintf(OutFile, "ERROR");
break;
//
// Pentium instructions
//
case NN_rdmsr: // Read Machine Status Register
case NN_wrmsr: // Write Machine Status Register
case NN_cpuid: // Get CPU ID
case NN_cmpxchg8b: // Compare and Exchange Eight Bytes
case NN_rdtsc: // Read Time Stamp Counter
case NN_rsm: // Resume from System Management Mode
SMP_fprintf(OutFile, "ERROR");
break;
//
// Pentium Pro instructions
//
case NN_cmova: // Move if Above (CF=0 & ZF=0)
case NN_cmovb: // Move if Below (CF=1)
case NN_cmovbe: // Move if Below or Equal (CF=1 | ZF=1)
case NN_cmovg: // Move if Greater (ZF=0 & SF=OF)
case NN_cmovge: // Move if Greater or Equal (SF=OF)
case NN_cmovl: // Move if Less (SF!=OF)
case NN_cmovle: // Move if Less or Equal (ZF=1 | SF!=OF)
case NN_cmovnb: // Move if Not Below (CF=0)
case NN_cmovno: // Move if Not Overflow (OF=0)
case NN_cmovnp: // Move if Not Parity (PF=0)
case NN_cmovns: // Move if Not Sign (SF=0)
case NN_cmovnz: // Move if Not Zero (ZF=0)
case NN_cmovo: // Move if Overflow (OF=1)
case NN_cmovp: // Move if Parity (PF=1)
case NN_cmovs: // Move if Sign (SF=1)
case NN_cmovz: // Move if Zero (ZF=1)
case NN_fcmovb: // Floating Move if Below
case NN_fcmove: // Floating Move if Equal
case NN_fcmovbe: // Floating Move if Below or Equal
case NN_fcmovu: // Floating Move if Unordered
case NN_fcmovnb: // Floating Move if Not Below
case NN_fcmovne: // Floating Move if Not Equal
case NN_fcmovnbe: // Floating Move if Not Below or Equal
case NN_fcmovnu: // Floating Move if Not Unordered
case NN_fcomi: // FP Compare, result in EFLAGS
case NN_fucomi: // FP Unordered Compare, result in EFLAGS
case NN_fcomip: // FP Compare, result in EFLAGS, pop stack
case NN_fucomip: // FP Unordered Compare, result in EFLAGS, pop stack
case NN_rdpmc: // Read Performance Monitor Counter
SMP_fprintf(OutFile, "ERROR");
break;
//
// FPP instructions
//
case NN_fld: // Load Real
case NN_fst: // Store Real
case NN_fstp: // Store Real and Pop
case NN_fxch: // Exchange Registers
case NN_fild: // Load Integer
case NN_fist: // Store Integer
case NN_fistp: // Store Integer and Pop
case NN_fbld: // Load BCD
case NN_fbstp: // Store BCD and Pop
case NN_fadd: // Add Real
case NN_faddp: // Add Real and Pop
case NN_fiadd: // Add Integer
case NN_fsub: // Subtract Real
case NN_fsubp: // Subtract Real and Pop
case NN_fisub: // Subtract Integer
case NN_fsubr: // Subtract Real Reversed
case NN_fsubrp: // Subtract Real Reversed and Pop
case NN_fisubr: // Subtract Integer Reversed
case NN_fmul: // Multiply Real
case NN_fmulp: // Multiply Real and Pop
case NN_fimul: // Multiply Integer
case NN_fdiv: // Divide Real
case NN_fdivp: // Divide Real and Pop
case NN_fidiv: // Divide Integer
case NN_fdivr: // Divide Real Reversed
case NN_fdivrp: // Divide Real Reversed and Pop
case NN_fidivr: // Divide Integer Reversed
case NN_fsqrt: // Square Root
case NN_fscale: // Scale: st(0) <- st(0) * 2^st(1)
case NN_fprem: // Partial Remainder
case NN_frndint: // Round to Integer
case NN_fxtract: // Extract exponent and significand
case NN_fabs: // Absolute value
case NN_fchs: // Change Sign
case NN_fcom: // Compare Real
case NN_fcomp: // Compare Real and Pop
case NN_fcompp: // Compare Real and Pop Twice
case NN_ficom: // Compare Integer
case NN_ficomp: // Compare Integer and Pop
case NN_ftst: // Test
case NN_fxam: // Examine
case NN_fptan: // Partial tangent
case NN_fpatan: // Partial arctangent
case NN_f2xm1: // 2^x - 1
case NN_fyl2x: // Y * lg2(X)
case NN_fyl2xp1: // Y * lg2(X+1)
case NN_fldz: // Load +0.0
case NN_fld1: // Load +1.0
case NN_fldpi: // Load PI=3.14...
case NN_fldl2t: // Load lg2(10)
case NN_fldl2e: // Load lg2(e)
case NN_fldlg2: // Load lg10(2)
case NN_fldln2: // Load ln(2)
case NN_finit: // Initialize Processor
case NN_fninit: // Initialize Processor (no wait)
case NN_fsetpm: // Set Protected Mode
case NN_fldcw: // Load Control Word
case NN_fstcw: // Store Control Word
case NN_fnstcw: // Store Control Word (no wait)
case NN_fstsw: // Store Status Word
case NN_fnstsw: // Store Status Word (no wait)
case NN_fclex: // Clear Exceptions
case NN_fnclex: // Clear Exceptions (no wait)
case NN_fstenv: // Store Environment
case NN_fnstenv: // Store Environment (no wait)
case NN_fldenv: // Load Environment
case NN_fsave: // Save State
case NN_fnsave: // Save State (no wait)
case NN_frstor: // Restore State
case NN_fincstp: // Increment Stack Pointer
case NN_fdecstp: // Decrement Stack Pointer
case NN_ffree: // Free Register
case NN_fnop: // No Operation
case NN_feni: // (8087 only)
case NN_fneni: // (no wait) (8087 only)
case NN_fdisi: // (8087 only)
case NN_fndisi: // (no wait) (8087 only)
SMP_fprintf(OutFile, "ERROR");
break;
//
// 80387 instructions
//
case NN_fprem1: // Partial Remainder ( < half )
case NN_fsincos: // t<-cos(st); st<-sin(st); push t
case NN_fsin: // Sine
case NN_fcos: // Cosine
case NN_fucom: // Compare Unordered Real
case NN_fucomp: // Compare Unordered Real and Pop
case NN_fucompp: // Compare Unordered Real and Pop Twice
SMP_fprintf(OutFile, "ERROR");
break;
//
// Instructions added 28.02.96
//
case NN_setalc: // Set AL to Carry Flag
case NN_svdc: // Save Register and Descriptor
case NN_rsdc: // Restore Register and Descriptor
case NN_svldt: // Save LDTR and Descriptor
case NN_rsldt: // Restore LDTR and Descriptor
case NN_svts: // Save TR and Descriptor
case NN_rsts: // Restore TR and Descriptor
case NN_icebp: // ICE Break Point
case NN_loadall: // Load the entire CPU state from ES:EDI
SMP_fprintf(OutFile, "ERROR");
break;
//
// MMX instructions
//
case NN_emms: // Empty MMX state
case NN_movd: // Move 32 bits
case NN_movq: // Move 64 bits
case NN_packsswb: // Pack with Signed Saturation (Word->Byte)
case NN_packssdw: // Pack with Signed Saturation (Dword->Word)
case NN_packuswb: // Pack with Unsigned Saturation (Word->Byte)
case NN_paddb: // Packed Add Byte
case NN_paddw: // Packed Add Word
case NN_paddd: // Packed Add Dword
case NN_paddsb: // Packed Add with Saturation (Byte)
case NN_paddsw: // Packed Add with Saturation (Word)
case NN_paddusb: // Packed Add Unsigned with Saturation (Byte)
case NN_paddusw: // Packed Add Unsigned with Saturation (Word)
case NN_pand: // Bitwise Logical And
case NN_pandn: // Bitwise Logical And Not
case NN_pcmpeqb: // Packed Compare for Equal (Byte)
case NN_pcmpeqw: // Packed Compare for Equal (Word)
case NN_pcmpeqd: // Packed Compare for Equal (Dword)
case NN_pcmpgtb: // Packed Compare for Greater Than (Byte)
case NN_pcmpgtw: // Packed Compare for Greater Than (Word)
case NN_pcmpgtd: // Packed Compare for Greater Than (Dword)
case NN_pmaddwd: // Packed Multiply and Add
case NN_pmulhw: // Packed Multiply High
case NN_pmullw: // Packed Multiply Low
case NN_por: // Bitwise Logical Or
case NN_psllw: // Packed Shift Left Logical (Word)
case NN_pslld: // Packed Shift Left Logical (Dword)
case NN_psllq: // Packed Shift Left Logical (Qword)
case NN_psraw: // Packed Shift Right Arithmetic (Word)
case NN_psrad: // Packed Shift Right Arithmetic (Dword)
case NN_psrlw: // Packed Shift Right Logical (Word)
case NN_psrld: // Packed Shift Right Logical (Dword)
case NN_psrlq: // Packed Shift Right Logical (Qword)
case NN_psubb: // Packed Subtract Byte
case NN_psubw: // Packed Subtract Word
case NN_psubd: // Packed Subtract Dword
case NN_psubsb: // Packed Subtract with Saturation (Byte)
case NN_psubsw: // Packed Subtract with Saturation (Word)
case NN_psubusb: // Packed Subtract Unsigned with Saturation (Byte)
case NN_psubusw: // Packed Subtract Unsigned with Saturation (Word)
case NN_punpckhbw: // Unpack High Packed Data (Byte->Word)
case NN_punpckhwd: // Unpack High Packed Data (Word->Dword)
case NN_punpckhdq: // Unpack High Packed Data (Dword->Qword)
case NN_punpcklbw: // Unpack Low Packed Data (Byte->Word)
case NN_punpcklwd: // Unpack Low Packed Data (Word->Dword)
case NN_punpckldq: // Unpack Low Packed Data (Dword->Qword)
case NN_pxor: // Bitwise Logical Exclusive Or
SMP_fprintf(OutFile, "ERROR");
break;
//
// Undocumented Deschutes processor instructions
//
case NN_fxsave: // Fast save FP context
case NN_fxrstor: // Fast restore FP context
SMP_fprintf(OutFile, "ERROR");
break;
// Pentium II instructions
case NN_sysenter: // Fast Transition to System Call Entry Point
case NN_sysexit: // Fast Transition from System Call Entry Point
SMP_fprintf(OutFile, "ERROR");
break;
// 3DNow! instructions
case NN_pavgusb: // Packed 8-bit Unsigned Integer Averaging
case NN_pfadd: // Packed Floating-Point Addition
case NN_pfsub: // Packed Floating-Point Subtraction
case NN_pfsubr: // Packed Floating-Point Reverse Subtraction
case NN_pfacc: // Packed Floating-Point Accumulate
case NN_pfcmpge: // Packed Floating-Point Comparison, Greater or Equal
case NN_pfcmpgt: // Packed Floating-Point Comparison, Greater
case NN_pfcmpeq: // Packed Floating-Point Comparison, Equal
case NN_pfmin: // Packed Floating-Point Minimum
case NN_pfmax: // Packed Floating-Point Maximum
case NN_pi2fd: // Packed 32-bit Integer to Floating-Point
case NN_pf2id: // Packed Floating-Point to 32-bit Integer
case NN_pfrcp: // Packed Floating-Point Reciprocal Approximation
case NN_pfrsqrt: // Packed Floating-Point Reciprocal Square Root Approximation
case NN_pfmul: // Packed Floating-Point Multiplication
case NN_pfrcpit1: // Packed Floating-Point Reciprocal First Iteration Step
case NN_pfrsqit1: // Packed Floating-Point Reciprocal Square Root First Iteration Step
case NN_pfrcpit2: // Packed Floating-Point Reciprocal Second Iteration Step
case NN_pmulhrw: // Packed Floating-Point 16-bit Integer Multiply with rounding
case NN_femms: // Faster entry/exit of the MMX or floating-point state
case NN_prefetch: // Prefetch at least a 32-byte line into L1 data cache
case NN_prefetchw: // Prefetch processor cache line into L1 data cache (mark as modified)
SMP_fprintf(OutFile, "ERROR");
break;
// Pentium III instructions
case NN_addps: // Packed Single-FP Add
case NN_addss: // Scalar Single-FP Add
case NN_andnps: // Bitwise Logical And Not for Single-FP
case NN_andps: // Bitwise Logical And for Single-FP
case NN_cmpps: // Packed Single-FP Compare
case NN_cmpss: // Scalar Single-FP Compare
case NN_comiss: // Scalar Ordered Single-FP Compare and Set EFLAGS
case NN_cvtpi2ps: // Packed signed INT32 to Packed Single-FP conversion
case NN_cvtps2pi: // Packed Single-FP to Packed INT32 conversion
case NN_cvtsi2ss: // Scalar signed INT32 to Single-FP conversion
case NN_cvtss2si: // Scalar Single-FP to signed INT32 conversion
case NN_cvttps2pi: // Packed Single-FP to Packed INT32 conversion (truncate)
case NN_cvttss2si: // Scalar Single-FP to signed INT32 conversion (truncate)
case NN_divps: // Packed Single-FP Divide
case NN_divss: // Scalar Single-FP Divide
case NN_ldmxcsr: // Load Streaming SIMD Extensions Technology Control/Status Register
case NN_maxps: // Packed Single-FP Maximum
case NN_maxss: // Scalar Single-FP Maximum
case NN_minps: // Packed Single-FP Minimum
case NN_minss: // Scalar Single-FP Minimum
case NN_movaps: // Move Aligned Four Packed Single-FP
case NN_movhlps: // Move High to Low Packed Single-FP
case NN_movhps: // Move High Packed Single-FP
case NN_movlhps: // Move Low to High Packed Single-FP
case NN_movlps: // Move Low Packed Single-FP
case NN_movmskps: // Move Mask to Register
case NN_movss: // Move Scalar Single-FP
case NN_movups: // Move Unaligned Four Packed Single-FP
case NN_mulps: // Packed Single-FP Multiply
case NN_mulss: // Scalar Single-FP Multiply
case NN_orps: // Bitwise Logical OR for Single-FP Data
case NN_rcpps: // Packed Single-FP Reciprocal
case NN_rcpss: // Scalar Single-FP Reciprocal
case NN_rsqrtps: // Packed Single-FP Square Root Reciprocal
case NN_rsqrtss: // Scalar Single-FP Square Root Reciprocal
case NN_shufps: // Shuffle Single-FP
case NN_sqrtps: // Packed Single-FP Square Root
case NN_sqrtss: // Scalar Single-FP Square Root
case NN_stmxcsr: // Store Streaming SIMD Extensions Technology Control/Status Register
case NN_subps: // Packed Single-FP Subtract
case NN_subss: // Scalar Single-FP Subtract
case NN_ucomiss: // Scalar Unordered Single-FP Compare and Set EFLAGS
case NN_unpckhps: // Unpack High Packed Single-FP Data
case NN_unpcklps: // Unpack Low Packed Single-FP Data
case NN_xorps: // Bitwise Logical XOR for Single-FP Data
case NN_pavgb: // Packed Average (Byte)
case NN_pavgw: // Packed Average (Word)
case NN_pextrw: // Extract Word
case NN_pinsrw: // Insert Word
case NN_pmaxsw: // Packed Signed Integer Word Maximum
case NN_pmaxub: // Packed Unsigned Integer Byte Maximum
case NN_pminsw: // Packed Signed Integer Word Minimum
case NN_pminub: // Packed Unsigned Integer Byte Minimum
case NN_pmovmskb: // Move Byte Mask to Integer
case NN_pmulhuw: // Packed Multiply High Unsigned
case NN_psadbw: // Packed Sum of Absolute Differences
case NN_pshufw: // Packed Shuffle Word
case NN_maskmovq: // Byte Mask write
case NN_movntps: // Move Aligned Four Packed Single-FP Non Temporal
case NN_movntq: // Move 64 Bits Non Temporal
case NN_prefetcht0: // Prefetch to all cache levels
case NN_prefetcht1: // Prefetch to all cache levels
case NN_prefetcht2: // Prefetch to L2 cache
case NN_prefetchnta: // Prefetch to L1 cache
case NN_sfence: // Store Fence
SMP_fprintf(OutFile, "ERROR");
break;
// Pentium III Pseudo instructions
case NN_cmpeqps: // Packed Single-FP Compare EQ
case NN_cmpltps: // Packed Single-FP Compare LT
case NN_cmpleps: // Packed Single-FP Compare LE
case NN_cmpunordps: // Packed Single-FP Compare UNORD
case NN_cmpneqps: // Packed Single-FP Compare NOT EQ
case NN_cmpnltps: // Packed Single-FP Compare NOT LT
case NN_cmpnleps: // Packed Single-FP Compare NOT LE
case NN_cmpordps: // Packed Single-FP Compare ORDERED
case NN_cmpeqss: // Scalar Single-FP Compare EQ
case NN_cmpltss: // Scalar Single-FP Compare LT
case NN_cmpless: // Scalar Single-FP Compare LE
case NN_cmpunordss: // Scalar Single-FP Compare UNORD
case NN_cmpneqss: // Scalar Single-FP Compare NOT EQ
case NN_cmpnltss: // Scalar Single-FP Compare NOT LT
case NN_cmpnless: // Scalar Single-FP Compare NOT LE
case NN_cmpordss: // Scalar Single-FP Compare ORDERED
SMP_fprintf(OutFile, "ERROR");
break;
// AMD K7 instructions
case NN_pf2iw: // Packed Floating-Point to Integer with Sign Extend
case NN_pfnacc: // Packed Floating-Point Negative Accumulate
case NN_pfpnacc: // Packed Floating-Point Mixed Positive-Negative Accumulate
case NN_pi2fw: // Packed 16-bit Integer to Floating-Point
case NN_pswapd: // Packed Swap Double Word
SMP_fprintf(OutFile, "ERROR");
break;
// Undocumented FP instructions (thanks to norbert.juffa@adm.com)
case NN_fstp1: // Alias of Store Real and Pop
case NN_fcom2: // Alias of Compare Real
case NN_fcomp3: // Alias of Compare Real and Pop
case NN_fxch4: // Alias of Exchange Registers
case NN_fcomp5: // Alias of Compare Real and Pop
case NN_ffreep: // Free Register and Pop
case NN_fxch7: // Alias of Exchange Registers
case NN_fstp8: // Alias of Store Real and Pop
case NN_fstp9: // Alias of Store Real and Pop
SMP_fprintf(OutFile, "ERROR");
break;
// Pentium 4 instructions
case NN_addpd: // Add Packed Double-Precision Floating-Point Values
case NN_addsd: // Add Scalar Double-Precision Floating-Point Values
case NN_andnpd: // Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
case NN_andpd: // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
case NN_clflush: // Flush Cache Line
case NN_cmppd: // Compare Packed Double-Precision Floating-Point Values
case NN_cmpsd: // Compare Scalar Double-Precision Floating-Point Values
case NN_comisd: // Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
case NN_cvtdq2pd: // Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
case NN_cvtdq2ps: // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
case NN_cvtpd2dq: // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
case NN_cvtpd2pi: // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
case NN_cvtpd2ps: // Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
case NN_cvtpi2pd: // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
case NN_cvtps2dq: // Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
case NN_cvtps2pd: // Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
case NN_cvtsd2si: // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
case NN_cvtsd2ss: // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
case NN_cvtsi2sd: // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
case NN_cvtss2sd: // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
case NN_cvttpd2dq: // Convert With Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
case NN_cvttpd2pi: // Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
case NN_cvttps2dq: // Convert With Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
case NN_cvttsd2si: // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
case NN_divpd: // Divide Packed Double-Precision Floating-Point Values
case NN_divsd: // Divide Scalar Double-Precision Floating-Point Values
case NN_lfence: // Load Fence
case NN_maskmovdqu: // Store Selected Bytes of Double Quadword
case NN_maxpd: // Return Maximum Packed Double-Precision Floating-Point Values
case NN_maxsd: // Return Maximum Scalar Double-Precision Floating-Point Value
case NN_mfence: // Memory Fence
case NN_minpd: // Return Minimum Packed Double-Precision Floating-Point Values
case NN_minsd: // Return Minimum Scalar Double-Precision Floating-Point Value
case NN_movapd: // Move Aligned Packed Double-Precision Floating-Point Values
case NN_movdq2q: // Move Quadword from XMM to MMX Register
case NN_movdqa: // Move Aligned Double Quadword
case NN_movdqu: // Move Unaligned Double Quadword
case NN_movhpd: // Move High Packed Double-Precision Floating-Point Values
case NN_movlpd: // Move Low Packed Double-Precision Floating-Point Values
case NN_movmskpd: // Extract Packed Double-Precision Floating-Point Sign Mask
case NN_movntdq: // Store Double Quadword Using Non-Temporal Hint
case NN_movnti: // Store Doubleword Using Non-Temporal Hint
case NN_movntpd: // Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
case NN_movq2dq: // Move Quadword from MMX to XMM Register
case NN_movsd: // Move Scalar Double-Precision Floating-Point Values
case NN_movupd: // Move Unaligned Packed Double-Precision Floating-Point Values
case NN_mulpd: // Multiply Packed Double-Precision Floating-Point Values
case NN_mulsd: // Multiply Scalar Double-Precision Floating-Point Values
case NN_orpd: // Bitwise Logical OR of Double-Precision Floating-Point Values
case NN_paddq: // Add Packed Quadword Integers
case NN_pause: // Spin Loop Hint
case NN_pmuludq: // Multiply Packed Unsigned Doubleword Integers
case NN_pshufd: // Shuffle Packed Doublewords
case NN_pshufhw: // Shuffle Packed High Words
case NN_pshuflw: // Shuffle Packed Low Words
case NN_pslldq: // Shift Double Quadword Left Logical
case NN_psrldq: // Shift Double Quadword Right Logical
case NN_psubq: // Subtract Packed Quadword Integers
case NN_punpckhqdq: // Unpack High Data
case NN_punpcklqdq: // Unpack Low Data
case NN_shufpd: // Shuffle Packed Double-Precision Floating-Point Values
case NN_sqrtpd: // Compute Square Roots of Packed Double-Precision Floating-Point Values
case NN_sqrtsd: // Compute Square Rootof Scalar Double-Precision Floating-Point Value
case NN_subpd: // Subtract Packed Double-Precision Floating-Point Values
case NN_subsd: // Subtract Scalar Double-Precision Floating-Point Values
case NN_ucomisd: // Unordered Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
case NN_unpckhpd: // Unpack and Interleave High Packed Double-Precision Floating-Point Values
case NN_unpcklpd: // Unpack and Interleave Low Packed Double-Precision Floating-Point Values
case NN_xorpd: // Bitwise Logical OR of Double-Precision Floating-Point Values
SMP_fprintf(OutFile, "ERROR");
break;
// AMD syscall/sysret instructions
case NN_syscall: // Low latency system call
case NN_sysret: // Return from system call
SMP_fprintf(OutFile, "ERROR");
break;
// AMD64 instructions
case NN_swapgs: // Exchange GS base with KernelGSBase MSR
SMP_fprintf(OutFile, "ERROR");
break;
// New Pentium instructions (SSE3)
case NN_movddup: // Move One Double-FP and Duplicate
case NN_movshdup: // Move Packed Single-FP High and Duplicate
case NN_movsldup: // Move Packed Single-FP Low and Duplicate
SMP_fprintf(OutFile, "ERROR");
break;
// Missing AMD64 instructions
case NN_movsxd: // Move with Sign-Extend Doubleword
case NN_cmpxchg16b: // Compare and Exchange 16 Bytes
SMP_fprintf(OutFile, "ERROR");
break;
// SSE3 instructions
case NN_addsubpd: // Add /Sub packed DP FP numbers
case NN_addsubps: // Add /Sub packed SP FP numbers
case NN_haddpd: // Add horizontally packed DP FP numbers
case NN_haddps: // Add horizontally packed SP FP numbers
case NN_hsubpd: // Sub horizontally packed DP FP numbers
case NN_hsubps: // Sub horizontally packed SP FP numbers
case NN_monitor: // Set up a linear address range to be monitored by hardware
case NN_mwait: // Wait until write-back store performed within the range specified by the MONITOR instruction
case NN_fisttp: // Store ST in intXX (chop) and pop
case NN_lddqu: // Load unaligned integer 128-bit
SMP_fprintf(OutFile, "ERROR");
break;
// SSSE3 instructions
case NN_psignb: // Packed SIGN Byte
case NN_psignw: // Packed SIGN Word
case NN_psignd: // Packed SIGN Doubleword
case NN_pshufb: // Packed Shuffle Bytes
case NN_pmulhrsw: // Packed Multiply High with Round and Scale
case NN_pmaddubsw: // Multiply and Add Packed Signed and Unsigned Bytes
case NN_phsubsw: // Packed Horizontal Subtract and Saturate
case NN_phaddsw: // Packed Horizontal Add and Saturate
case NN_phaddw: // Packed Horizontal Add Word
case NN_phaddd: // Packed Horizontal Add Doubleword
case NN_phsubw: // Packed Horizontal Subtract Word
case NN_phsubd: // Packed Horizontal Subtract Doubleword
case NN_palignr: // Packed Align Right
case NN_pabsb: // Packed Absolute Value Byte
case NN_pabsw: // Packed Absolute Value Word
case NN_pabsd: // Packed Absolute Value Doubleword
SMP_fprintf(OutFile, "ERROR");
break;
// VMX instructions
case NN_vmcall: // Call to VM Monitor
case NN_vmclear: // Clear Virtual Machine Control Structure
case NN_vmlaunch: // Launch Virtual Machine
case NN_vmresume: // Resume Virtual Machine
case NN_vmptrld: // Load Pointer to Virtual Machine Control Structure
case NN_vmptrst: // Store Pointer to Virtual Machine Control Structure
case NN_vmread: // Read Field from Virtual Machine Control Structure
case NN_vmwrite: // Write Field from Virtual Machine Control Structure
case NN_vmxoff: // Leave VMX Operation
case NN_vmxon: // Enter VMX Operation
SMP_fprintf(OutFile, "ERROR");
break;
// Undefined Instruction
case NN_ud2: // Undefined Instruction
SMP_fprintf(OutFile, "ERROR");
break;
// Added with x86-64
case NN_rdtscp: // Read Time-Stamp Counter and Processor ID
SMP_fprintf(OutFile, "ERROR");
break;
// Geode LX 3DNow! extensions
case NN_pfrcpv: // Reciprocal Approximation for a Pair of 32-bit Floats
case NN_pfrsqrtv: // Reciprocal Square Root Approximation for a Pair of 32-bit Floats
SMP_fprintf(OutFile, "ERROR");
break;
// SSE2 pseudoinstructions
case NN_cmpeqpd: // Packed Double-FP Compare EQ
case NN_cmpltpd: // Packed Double-FP Compare LT
case NN_cmplepd: // Packed Double-FP Compare LE
case NN_cmpunordpd: // Packed Double-FP Compare UNORD
case NN_cmpneqpd: // Packed Double-FP Compare NOT EQ
case NN_cmpnltpd: // Packed Double-FP Compare NOT LT
case NN_cmpnlepd: // Packed Double-FP Compare NOT LE
case NN_cmpordpd: // Packed Double-FP Compare ORDERED
case NN_cmpeqsd: // Scalar Double-FP Compare EQ
case NN_cmpltsd: // Scalar Double-FP Compare LT
case NN_cmplesd: // Scalar Double-FP Compare LE
case NN_cmpunordsd: // Scalar Double-FP Compare UNORD
case NN_cmpneqsd: // Scalar Double-FP Compare NOT EQ
case NN_cmpnltsd: // Scalar Double-FP Compare NOT LT
case NN_cmpnlesd: // Scalar Double-FP Compare NOT LE
case NN_cmpordsd: // Scalar Double-FP Compare ORDERED
SMP_fprintf(OutFile, "ERROR");
break;
// SSSE4.1 instructions
case NN_blendpd: // Blend Packed Double Precision Floating-Point Values
case NN_blendps: // Blend Packed Single Precision Floating-Point Values
case NN_blendvpd: // Variable Blend Packed Double Precision Floating-Point Values
case NN_blendvps: // Variable Blend Packed Single Precision Floating-Point Values
case NN_dppd: // Dot Product of Packed Double Precision Floating-Point Values
case NN_dpps: // Dot Product of Packed Single Precision Floating-Point Values
case NN_extractps: // Extract Packed Single Precision Floating-Point Value
case NN_insertps: // Insert Packed Single Precision Floating-Point Value
case NN_movntdqa: // Load Double Quadword Non-Temporal Aligned Hint
case NN_mpsadbw: // Compute Multiple Packed Sums of Absolute Difference
case NN_packusdw: // Pack with Unsigned Saturation
case NN_pblendvb: // Variable Blend Packed Bytes
case NN_pblendw: // Blend Packed Words
case NN_pcmpeqq: // Compare Packed Qword Data for Equal
case NN_pextrb: // Extract Byte
case NN_pextrd: // Extract Dword
case NN_pextrq: // Extract Qword
case NN_phminposuw: // Packed Horizontal Word Minimum
case NN_pinsrb: // Insert Byte
case NN_pinsrd: // Insert Dword
case NN_pinsrq: // Insert Qword
case NN_pmaxsb: // Maximum of Packed Signed Byte Integers
case NN_pmaxsd: // Maximum of Packed Signed Dword Integers
case NN_pmaxud: // Maximum of Packed Unsigned Dword Integers
case NN_pmaxuw: // Maximum of Packed Word Integers
case NN_pminsb: // Minimum of Packed Signed Byte Integers
case NN_pminsd: // Minimum of Packed Signed Dword Integers
case NN_pminud: // Minimum of Packed Unsigned Dword Integers
case NN_pminuw: // Minimum of Packed Word Integers
case NN_pmovsxbw: // Packed Move with Sign Extend
case NN_pmovsxbd: // Packed Move with Sign Extend
case NN_pmovsxbq: // Packed Move with Sign Extend
case NN_pmovsxwd: // Packed Move with Sign Extend
case NN_pmovsxwq: // Packed Move with Sign Extend
case NN_pmovsxdq: // Packed Move with Sign Extend
case NN_pmovzxbw: // Packed Move with Zero Extend
case NN_pmovzxbd: // Packed Move with Zero Extend
case NN_pmovzxbq: // Packed Move with Zero Extend
case NN_pmovzxwd: // Packed Move with Zero Extend
case NN_pmovzxwq: // Packed Move with Zero Extend
case NN_pmovzxdq: // Packed Move with Zero Extend
case NN_pmuldq: // Multiply Packed Signed Dword Integers
case NN_pmulld: // Multiply Packed Signed Dword Integers and Store Low Result
case NN_ptest: // Logical Compare
case NN_roundpd: // Round Packed Double Precision Floating-Point Values
case NN_roundps: // Round Packed Single Precision Floating-Point Values
case NN_roundsd: // Round Scalar Double Precision Floating-Point Values
case NN_roundss: // Round Scalar Single Precision Floating-Point Values
SMP_fprintf(OutFile, "ERROR");
break;
// SSSE4.2 instructions
case NN_crc32: // Accumulate CRC32 Value
case NN_pcmpestri: // Packed Compare Explicit Length Strings: Return Index
case NN_pcmpestrm: // Packed Compare Explicit Length Strings: Return Mask
case NN_pcmpistri: // Packed Compare Implicit Length Strings: Return Index
case NN_pcmpistrm: // Packed Compare Implicit Length Strings: Return Mask
case NN_pcmpgtq: // Compare Packed Data for Greater Than
case NN_popcnt: // Return the Count of Number of Bits Set to 1
SMP_fprintf(OutFile, "ERROR");
break;
// AMD SSE4a instructions
case NN_extrq: // Extract Field From Register
case NN_insertq: // Insert Field
case NN_movntsd: // Move Non-Temporal Scalar Double-Precision Floating-Point
case NN_movntss: // Move Non-Temporal Scalar Single-Precision Floating-Point
case NN_lzcnt: // Leading Zero Count
SMP_fprintf(OutFile, "ERROR");
break;
// xsave/xrstor instructions
case NN_xgetbv: // Get Value of Extended Control Register
case NN_xrstor: // Restore Processor Extended States
case NN_xsave: // Save Processor Extended States
case NN_xsetbv: // Set Value of Extended Control Register
SMP_fprintf(OutFile, "ERROR");
break;
// Intel Safer Mode Extensions (SMX)
case NN_getsec: // Safer Mode Extensions (SMX) Instruction
SMP_fprintf(OutFile, "ERROR");
break;
// AMD-V Virtualization ISA Extension
case NN_clgi: // Clear Global Interrupt Flag
case NN_invlpga: // Invalidate TLB Entry in a Specified ASID
case NN_skinit: // Secure Init and Jump with Attestation
case NN_stgi: // Set Global Interrupt Flag
case NN_vmexit: // Stop Executing Guest: Begin Executing Host
case NN_vmload: // Load State from VMCB
case NN_vmmcall: // Call VMM
case NN_vmrun: // Run Virtual Machine
case NN_vmsave: // Save State to VMCB
SMP_fprintf(OutFile, "ERROR");
break;
// VMX+ instructions
case NN_invept: // Invalidate Translations Derived from EPT
case NN_invvpid: // Invalidate Translations Based on VPID
SMP_fprintf(OutFile, "ERROR");
break;
// Intel Atom instructions
case NN_movbe: // Move Data After Swapping Bytes
SMP_fprintf(OutFile, "ERROR");
break;
// Intel AES instructions
case NN_aesenc: // Perform One Round of an AES Encryption Flow
case NN_aesenclast: // Perform the Last Round of an AES Encryption Flow
case NN_aesdec: // Perform One Round of an AES Decryption Flow
case NN_aesdeclast: // Perform the Last Round of an AES Decryption Flow
case NN_aesimc: // Perform the AES InvMixColumn Transformation
case NN_aeskeygenassist: // AES Round Key Generation Assist
SMP_fprintf(OutFile, "ERROR");
break;
// Carryless multiplication
case NN_pclmulqdq: // Carry-Less Multiplication Quadword
SMP_fprintf(OutFile, "ERROR");
break;
// Returns modifies by operand size prefixes
case NN_retnw: // Return Near from Procedure (use16)
case NN_retnd: // Return Near from Procedure (use32)
case NN_retnq: // Return Near from Procedure (use64)
case NN_retfw: // Return Far from Procedure (use16)
case NN_retfd: // Return Far from Procedure (use32)
case NN_retfq: // Return Far from Procedure (use64)
SMP_fprintf(OutFile, "return");
break;
// RDRAND support
case NN_rdrand: // Read Random Number
SMP_fprintf(OutFile, "ERROR");
break;
// new GPR instructions
case NN_adcx: // Unsigned Integer Addition of Two Operands with Carry Flag
case NN_adox: // Unsigned Integer Addition of Two Operands with Overflow Flag
case NN_andn: // Logical AND NOT
case NN_bextr: // Bit Field Extract
case NN_blsi: // Extract Lowest Set Isolated Bit
case NN_blsmsk: // Get Mask Up to Lowest Set Bit
case NN_blsr: // Reset Lowest Set Bit
case NN_bzhi: // Zero High Bits Starting with Specified Bit Position
case NN_clac: // Clear AC Flag in EFLAGS Register
case NN_mulx: // Unsigned Multiply Without Affecting Flags
case NN_pdep: // Parallel Bits Deposit
case NN_pext: // Parallel Bits Extract
case NN_rorx: // Rotate Right Logical Without Affecting Flags
case NN_sarx: // Shift Arithmetically Right Without Affecting Flags
case NN_shlx: // Shift Logically Left Without Affecting Flags
case NN_shrx: // Shift Logically Right Without Affecting Flags
case NN_stac: // Set AC Flag in EFLAGS Register
case NN_tzcnt: // Count the Number of Trailing Zero Bits
case NN_xsaveopt: // Save Processor Extended States Optimized
case NN_invpcid: // Invalidate Processor Context ID
case NN_rdseed: // Read Random Seed
case NN_rdfsbase: // Read FS Segment Base
case NN_rdgsbase: // Read GS Segment Base
case NN_wrfsbase: // Write FS Segment Base
case NN_wrgsbase: // Write GS Segment Base
SMP_fprintf(OutFile, "ERROR");
break;
// new AVX instructions
case NN_vaddpd: // Add Packed Double-Precision Floating-Point Values
case NN_vaddps: // Packed Single-FP Add
case NN_vaddsd: // Add Scalar Double-Precision Floating-Point Values
case NN_vaddss: // Scalar Single-FP Add
case NN_vaddsubpd: // Add /Sub packed DP FP numbers
case NN_vaddsubps: // Add /Sub packed SP FP numbers
case NN_vaesdec: // Perform One Round of an AES Decryption Flow
case NN_vaesdeclast: // Perform the Last Round of an AES Decryption Flow
case NN_vaesenc: // Perform One Round of an AES Encryption Flow
case NN_vaesenclast: // Perform the Last Round of an AES Encryption Flow
case NN_vaesimc: // Perform the AES InvMixColumn Transformation
case NN_vaeskeygenassist: // AES Round Key Generation Assist
case NN_vandnpd: // Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
case NN_vandnps: // Bitwise Logical And Not for Single-FP
case NN_vandpd: // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
case NN_vandps: // Bitwise Logical And for Single-FP
case NN_vblendpd: // Blend Packed Double Precision Floating-Point Values
case NN_vblendps: // Blend Packed Single Precision Floating-Point Values
case NN_vblendvpd: // Variable Blend Packed Double Precision Floating-Point Values
case NN_vblendvps: // Variable Blend Packed Single Precision Floating-Point Values
case NN_vbroadcastf128: // Broadcast 128 Bits of Floating-Point Data
case NN_vbroadcasti128: // Broadcast 128 Bits of Integer Data
case NN_vbroadcastsd: // Broadcast Double-Precision Floating-Point Element
case NN_vbroadcastss: // Broadcast Single-Precision Floating-Point Element
case NN_vcmppd: // Compare Packed Double-Precision Floating-Point Values
case NN_vcmpps: // Packed Single-FP Compare
case NN_vcmpsd: // Compare Scalar Double-Precision Floating-Point Values
case NN_vcmpss: // Scalar Single-FP Compare
case NN_vcomisd: // Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
case NN_vcomiss: // Scalar Ordered Single-FP Compare and Set EFLAGS
case NN_vcvtdq2pd: // Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
case NN_vcvtdq2ps: // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
case NN_vcvtpd2dq: // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
case NN_vcvtpd2ps: // Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
case NN_vcvtph2ps: // Convert 16-bit FP Values to Single-Precision FP Values
case NN_vcvtps2dq: // Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
case NN_vcvtps2pd: // Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
case NN_vcvtps2ph: // Convert Single-Precision FP value to 16-bit FP value
case NN_vcvtsd2si: // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
case NN_vcvtsd2ss: // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
case NN_vcvtsi2sd: // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
case NN_vcvtsi2ss: // Scalar signed INT32 to Single-FP conversion
case NN_vcvtss2sd: // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
case NN_vcvtss2si: // Scalar Single-FP to signed INT32 conversion
case NN_vcvttpd2dq: // Convert With Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
case NN_vcvttps2dq: // Convert With Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
case NN_vcvttsd2si: // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
case NN_vcvttss2si: // Scalar Single-FP to signed INT32 conversion (truncate)
case NN_vdivpd: // Divide Packed Double-Precision Floating-Point Values
case NN_vdivps: // Packed Single-FP Divide
case NN_vdivsd: // Divide Scalar Double-Precision Floating-Point Values
case NN_vdivss: // Scalar Single-FP Divide
case NN_vdppd: // Dot Product of Packed Double Precision Floating-Point Values
case NN_vdpps: // Dot Product of Packed Single Precision Floating-Point Values
case NN_vextractf128: // Extract Packed Floating-Point Values
case NN_vextracti128: // Extract Packed Integer Values
case NN_vextractps: // Extract Packed Floating-Point Values
case NN_vfmadd132pd: // Fused Multiply-Add of Packed Double-Precision Floating-Point Values
case NN_vfmadd132ps: // Fused Multiply-Add of Packed Single-Precision Floating-Point Values
case NN_vfmadd132sd: // Fused Multiply-Add of Scalar Double-Precision Floating-Point Values
case NN_vfmadd132ss: // Fused Multiply-Add of Scalar Single-Precision Floating-Point Values
case NN_vfmadd213pd: // Fused Multiply-Add of Packed Double-Precision Floating-Point Values
case NN_vfmadd213ps: // Fused Multiply-Add of Packed Single-Precision Floating-Point Values
case NN_vfmadd213sd: // Fused Multiply-Add of Scalar Double-Precision Floating-Point Values
case NN_vfmadd213ss: // Fused Multiply-Add of Scalar Single-Precision Floating-Point Values
case NN_vfmadd231pd: // Fused Multiply-Add of Packed Double-Precision Floating-Point Values
case NN_vfmadd231ps: // Fused Multiply-Add of Packed Single-Precision Floating-Point Values
case NN_vfmadd231sd: // Fused Multiply-Add of Scalar Double-Precision Floating-Point Values
case NN_vfmadd231ss: // Fused Multiply-Add of Scalar Single-Precision Floating-Point Values
case NN_vfmaddsub132pd: // Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values
case NN_vfmaddsub132ps: // Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
case NN_vfmaddsub213pd: // Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values
case NN_vfmaddsub213ps: // Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
case NN_vfmaddsub231pd: // Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values
case NN_vfmaddsub231ps: // Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
case NN_vfmsub132pd: // Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
case NN_vfmsub132ps: // Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
case NN_vfmsub132sd: // Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
case NN_vfmsub132ss: // Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
case NN_vfmsub213pd: // Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
case NN_vfmsub213ps: // Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
case NN_vfmsub213sd: // Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
case NN_vfmsub213ss: // Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
case NN_vfmsub231pd: // Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
case NN_vfmsub231ps: // Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
case NN_vfmsub231sd: // Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
case NN_vfmsub231ss: // Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
case NN_vfmsubadd132pd: // Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
case NN_vfmsubadd132ps: // Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
case NN_vfmsubadd213pd: // Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
case NN_vfmsubadd213ps: // Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
case NN_vfmsubadd231pd: // Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
case NN_vfmsubadd231ps: // Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
case NN_vfnmadd132pd: // Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
case NN_vfnmadd132ps: // Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
case NN_vfnmadd132sd: // Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
case NN_vfnmadd132ss: // Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
case NN_vfnmadd213pd: // Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
case NN_vfnmadd213ps: // Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
case NN_vfnmadd213sd: // Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
case NN_vfnmadd213ss: // Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
case NN_vfnmadd231pd: // Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
case NN_vfnmadd231ps: // Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
case NN_vfnmadd231sd: // Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
case NN_vfnmadd231ss: // Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
case NN_vfnmsub132pd: // Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values
case NN_vfnmsub132ps: // Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values
case NN_vfnmsub132sd: // Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values
case NN_vfnmsub132ss: // Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values
case NN_vfnmsub213pd: // Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values
case NN_vfnmsub213ps: // Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values
case NN_vfnmsub213sd: // Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values
case NN_vfnmsub213ss: // Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values
case NN_vfnmsub231pd: // Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values
case NN_vfnmsub231ps: // Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values
case NN_vfnmsub231sd: // Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values
case NN_vfnmsub231ss: // Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values
case NN_vgatherdps: // Gather Packed SP FP Values Using Signed Dword Indices
case NN_vgatherdpd: // Gather Packed DP FP Values Using Signed Dword Indices
case NN_vgatherqps: // Gather Packed SP FP Values Using Signed Qword Indices
case NN_vgatherqpd: // Gather Packed DP FP Values Using Signed Qword Indices
case NN_vhaddpd: // Add horizontally packed DP FP numbers
case NN_vhaddps: // Add horizontally packed SP FP numbers
case NN_vhsubpd: // Sub horizontally packed DP FP numbers
case NN_vhsubps: // Sub horizontally packed SP FP numbers
case NN_vinsertf128: // Insert Packed Floating-Point Values
case NN_vinserti128: // Insert Packed Integer Values
case NN_vinsertps: // Insert Packed Single Precision Floating-Point Value
case NN_vlddqu: // Load Unaligned Packed Integer Values
case NN_vldmxcsr: // Load Streaming SIMD Extensions Technology Control/Status Register
case NN_vmaskmovdqu: // Store Selected Bytes of Double Quadword with NT Hint
case NN_vmaskmovpd: // Conditionally Load Packed Double-Precision Floating-Point Values
case NN_vmaskmovps: // Conditionally Load Packed Single-Precision Floating-Point Values
case NN_vmaxpd: // Return Maximum Packed Double-Precision Floating-Point Values
case NN_vmaxps: // Packed Single-FP Maximum
case NN_vmaxsd: // Return Maximum Scalar Double-Precision Floating-Point Value
case NN_vmaxss: // Scalar Single-FP Maximum
case NN_vminpd: // Return Minimum Packed Double-Precision Floating-Point Values
case NN_vminps: // Packed Single-FP Minimum
case NN_vminsd: // Return Minimum Scalar Double-Precision Floating-Point Value
case NN_vminss: // Scalar Single-FP Minimum
case NN_vmovapd: // Move Aligned Packed Double-Precision Floating-Point Values
case NN_vmovaps: // Move Aligned Four Packed Single-FP
case NN_vmovd: // Move 32 bits
case NN_vmovddup: // Move One Double-FP and Duplicate
case NN_vmovdqa: // Move Aligned Double Quadword
case NN_vmovdqu: // Move Unaligned Double Quadword
case NN_vmovhlps: // Move High to Low Packed Single-FP
case NN_vmovhpd: // Move High Packed Double-Precision Floating-Point Values
case NN_vmovhps: // Move High Packed Single-FP
case NN_vmovlhps: // Move Low to High Packed Single-FP
case NN_vmovlpd: // Move Low Packed Double-Precision Floating-Point Values
case NN_vmovlps: // Move Low Packed Single-FP
case NN_vmovmskpd: // Extract Packed Double-Precision Floating-Point Sign Mask
case NN_vmovmskps: // Move Mask to Register
case NN_vmovntdq: // Store Double Quadword Using Non-Temporal Hint
case NN_vmovntdqa: // Load Double Quadword Non-Temporal Aligned Hint
case NN_vmovntpd: // Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
case NN_vmovntps: // Move Aligned Four Packed Single-FP Non Temporal
case NN_vmovntsd: // Move Non-Temporal Scalar Double-Precision Floating-Point
case NN_vmovntss: // Move Non-Temporal Scalar Single-Precision Floating-Point
case NN_vmovq: // Move 64 bits
case NN_vmovsd: // Move Scalar Double-Precision Floating-Point Values
case NN_vmovshdup: // Move Packed Single-FP High and Duplicate
case NN_vmovsldup: // Move Packed Single-FP Low and Duplicate
case NN_vmovss: // Move Scalar Single-FP
case NN_vmovupd: // Move Unaligned Packed Double-Precision Floating-Point Values
case NN_vmovups: // Move Unaligned Four Packed Single-FP
case NN_vmpsadbw: // Compute Multiple Packed Sums of Absolute Difference
case NN_vmulpd: // Multiply Packed Double-Precision Floating-Point Values
case NN_vmulps: // Packed Single-FP Multiply
case NN_vmulsd: // Multiply Scalar Double-Precision Floating-Point Values
case NN_vmulss: // Scalar Single-FP Multiply
case NN_vorpd: // Bitwise Logical OR of Double-Precision Floating-Point Values
case NN_vorps: // Bitwise Logical OR for Single-FP Data
case NN_vpabsb: // Packed Absolute Value Byte
case NN_vpabsd: // Packed Absolute Value Doubleword
case NN_vpabsw: // Packed Absolute Value Word
case NN_vpackssdw: // Pack with Signed Saturation (Dword->Word)
case NN_vpacksswb: // Pack with Signed Saturation (Word->Byte)
case NN_vpackusdw: // Pack with Unsigned Saturation
case NN_vpackuswb: // Pack with Unsigned Saturation (Word->Byte)
case NN_vpaddb: // Packed Add Byte
case NN_vpaddd: // Packed Add Dword
case NN_vpaddq: // Add Packed Quadword Integers
case NN_vpaddsb: // Packed Add with Saturation (Byte)
case NN_vpaddsw: // Packed Add with Saturation (Word)
case NN_vpaddusb: // Packed Add Unsigned with Saturation (Byte)
case NN_vpaddusw: // Packed Add Unsigned with Saturation (Word)
case NN_vpaddw: // Packed Add Word
case NN_vpalignr: // Packed Align Right
case NN_vpand: // Bitwise Logical And
case NN_vpandn: // Bitwise Logical And Not
case NN_vpavgb: // Packed Average (Byte)
case NN_vpavgw: // Packed Average (Word)
case NN_vpblendd: // Blend Packed Dwords
case NN_vpblendvb: // Variable Blend Packed Bytes
case NN_vpblendw: // Blend Packed Words
case NN_vpbroadcastb: // Broadcast a Byte Integer
case NN_vpbroadcastd: // Broadcast a Dword Integer
case NN_vpbroadcastq: // Broadcast a Qword Integer
case NN_vpbroadcastw: // Broadcast a Word Integer
case NN_vpclmulqdq: // Carry-Less Multiplication Quadword
case NN_vpcmpeqb: // Packed Compare for Equal (Byte)
case NN_vpcmpeqd: // Packed Compare for Equal (Dword)
case NN_vpcmpeqq: // Compare Packed Qword Data for Equal
case NN_vpcmpeqw: // Packed Compare for Equal (Word)
case NN_vpcmpestri: // Packed Compare Explicit Length Strings: Return Index
case NN_vpcmpestrm: // Packed Compare Explicit Length Strings: Return Mask
case NN_vpcmpgtb: // Packed Compare for Greater Than (Byte)
case NN_vpcmpgtd: // Packed Compare for Greater Than (Dword)
case NN_vpcmpgtq: // Compare Packed Data for Greater Than
case NN_vpcmpgtw: // Packed Compare for Greater Than (Word)
case NN_vpcmpistri: // Packed Compare Implicit Length Strings: Return Index
case NN_vpcmpistrm: // Packed Compare Implicit Length Strings: Return Mask
case NN_vperm2f128: // Permute Floating-Point Values
case NN_vperm2i128: // Permute Integer Values
case NN_vpermd: // Full Doublewords Element Permutation
case NN_vpermilpd: // Permute Double-Precision Floating-Point Values
case NN_vpermilps: // Permute Single-Precision Floating-Point Values
case NN_vpermpd: // Permute Double-Precision Floating-Point Elements
case NN_vpermps: // Permute Single-Precision Floating-Point Elements
case NN_vpermq: // Qwords Element Permutation
case NN_vpextrb: // Extract Byte
case NN_vpextrd: // Extract Dword
case NN_vpextrq: // Extract Qword
case NN_vpextrw: // Extract Word
case NN_vpgatherdd: // Gather Packed Dword Values Using Signed Dword Indices
case NN_vpgatherdq: // Gather Packed Qword Values Using Signed Dword Indices
case NN_vpgatherqd: // Gather Packed Dword Values Using Signed Qword Indices
case NN_vpgatherqq: // Gather Packed Qword Values Using Signed Qword Indices
case NN_vphaddd: // Packed Horizontal Add Doubleword
case NN_vphaddsw: // Packed Horizontal Add and Saturate
case NN_vphaddw: // Packed Horizontal Add Word
case NN_vphminposuw: // Packed Horizontal Word Minimum
case NN_vphsubd: // Packed Horizontal Subtract Doubleword
case NN_vphsubsw: // Packed Horizontal Subtract and Saturate
case NN_vphsubw: // Packed Horizontal Subtract Word
case NN_vpinsrb: // Insert Byte
case NN_vpinsrd: // Insert Dword
case NN_vpinsrq: // Insert Qword
case NN_vpinsrw: // Insert Word
case NN_vpmaddubsw: // Multiply and Add Packed Signed and Unsigned Bytes
case NN_vpmaddwd: // Packed Multiply and Add
case NN_vpmaskmovd: // Conditionally Store Dword Values Using Mask
case NN_vpmaskmovq: // Conditionally Store Qword Values Using Mask
case NN_vpmaxsb: // Maximum of Packed Signed Byte Integers
case NN_vpmaxsd: // Maximum of Packed Signed Dword Integers
case NN_vpmaxsw: // Packed Signed Integer Word Maximum
case NN_vpmaxub: // Packed Unsigned Integer Byte Maximum
case NN_vpmaxud: // Maximum of Packed Unsigned Dword Integers
case NN_vpmaxuw: // Maximum of Packed Word Integers
case NN_vpminsb: // Minimum of Packed Signed Byte Integers
case NN_vpminsd: // Minimum of Packed Signed Dword Integers
case NN_vpminsw: // Packed Signed Integer Word Minimum
case NN_vpminub: // Packed Unsigned Integer Byte Minimum
case NN_vpminud: // Minimum of Packed Unsigned Dword Integers
case NN_vpminuw: // Minimum of Packed Word Integers
case NN_vpmovmskb: // Move Byte Mask to Integer
case NN_vpmovsxbd: // Packed Move with Sign Extend
case NN_vpmovsxbq: // Packed Move with Sign Extend
case NN_vpmovsxbw: // Packed Move with Sign Extend
case NN_vpmovsxdq: // Packed Move with Sign Extend
case NN_vpmovsxwd: // Packed Move with Sign Extend
case NN_vpmovsxwq: // Packed Move with Sign Extend
case NN_vpmovzxbd: // Packed Move with Zero Extend
case NN_vpmovzxbq: // Packed Move with Zero Extend
case NN_vpmovzxbw: // Packed Move with Zero Extend
case NN_vpmovzxdq: // Packed Move with Zero Extend
case NN_vpmovzxwd: // Packed Move with Zero Extend
case NN_vpmovzxwq: // Packed Move with Zero Extend
case NN_vpmuldq: // Multiply Packed Signed Dword Integers
case NN_vpmulhrsw: // Packed Multiply High with Round and Scale
case NN_vpmulhuw: // Packed Multiply High Unsigned
case NN_vpmulhw: // Packed Multiply High
case NN_vpmulld: // Multiply Packed Signed Dword Integers and Store Low Result
case NN_vpmullw: // Packed Multiply Low
case NN_vpmuludq: // Multiply Packed Unsigned Doubleword Integers
case NN_vpor: // Bitwise Logical Or
case NN_vpsadbw: // Packed Sum of Absolute Differences
case NN_vpshufb: // Packed Shuffle Bytes
case NN_vpshufd: // Shuffle Packed Doublewords
case NN_vpshufhw: // Shuffle Packed High Words
case NN_vpshuflw: // Shuffle Packed Low Words
case NN_vpsignb: // Packed SIGN Byte
case NN_vpsignd: // Packed SIGN Doubleword
case NN_vpsignw: // Packed SIGN Word
case NN_vpslld: // Packed Shift Left Logical (Dword)
case NN_vpslldq: // Shift Double Quadword Left Logical
case NN_vpsllq: // Packed Shift Left Logical (Qword)
case NN_vpsllvd: // Variable Bit Shift Left Logical (Dword)
case NN_vpsllvq: // Variable Bit Shift Left Logical (Qword)
case NN_vpsllw: // Packed Shift Left Logical (Word)
case NN_vpsrad: // Packed Shift Right Arithmetic (Dword)
case NN_vpsravd: // Variable Bit Shift Right Arithmetic
case NN_vpsraw: // Packed Shift Right Arithmetic (Word)
case NN_vpsrld: // Packed Shift Right Logical (Dword)
case NN_vpsrldq: // Shift Double Quadword Right Logical (Qword)
case NN_vpsrlq: // Packed Shift Right Logical (Qword)
case NN_vpsrlvd: // Variable Bit Shift Right Logical (Dword)
case NN_vpsrlvq: // Variable Bit Shift Right Logical (Qword)
case NN_vpsrlw: // Packed Shift Right Logical (Word)
case NN_vpsubb: // Packed Subtract Byte
case NN_vpsubd: // Packed Subtract Dword
case NN_vpsubq: // Subtract Packed Quadword Integers
case NN_vpsubsb: // Packed Subtract with Saturation (Byte)
case NN_vpsubsw: // Packed Subtract with Saturation (Word)
case NN_vpsubusb: // Packed Subtract Unsigned with Saturation (Byte)
case NN_vpsubusw: // Packed Subtract Unsigned with Saturation (Word)
case NN_vpsubw: // Packed Subtract Word
case NN_vptest: // Logical Compare
case NN_vpunpckhbw: // Unpack High Packed Data (Byte->Word)
case NN_vpunpckhdq: // Unpack High Packed Data (Dword->Qword)
case NN_vpunpckhqdq: // Unpack High Packed Data (Qword->Xmmword)
case NN_vpunpckhwd: // Unpack High Packed Data (Word->Dword)
case NN_vpunpcklbw: // Unpack Low Packed Data (Byte->Word)
case NN_vpunpckldq: // Unpack Low Packed Data (Dword->Qword)
case NN_vpunpcklqdq: // Unpack Low Packed Data (Qword->Xmmword)
case NN_vpunpcklwd: // Unpack Low Packed Data (Word->Dword)
case NN_vpxor: // Bitwise Logical Exclusive Or
case NN_vrcpps: // Packed Single-FP Reciprocal
case NN_vrcpss: // Scalar Single-FP Reciprocal
case NN_vroundpd: // Round Packed Double Precision Floating-Point Values
case NN_vroundps: // Round Packed Single Precision Floating-Point Values
case NN_vroundsd: // Round Scalar Double Precision Floating-Point Values
case NN_vroundss: // Round Scalar Single Precision Floating-Point Values
case NN_vrsqrtps: // Packed Single-FP Square Root Reciprocal
case NN_vrsqrtss: // Scalar Single-FP Square Root Reciprocal
case NN_vshufpd: // Shuffle Packed Double-Precision Floating-Point Values
case NN_vshufps: // Shuffle Single-FP
case NN_vsqrtpd: // Compute Square Roots of Packed Double-Precision Floating-Point Values
case NN_vsqrtps: // Packed Single-FP Square Root
case NN_vsqrtsd: // Compute Square Rootof Scalar Double-Precision Floating-Point Value
case NN_vsqrtss: // Scalar Single-FP Square Root
case NN_vstmxcsr: // Store Streaming SIMD Extensions Technology Control/Status Register
case NN_vsubpd: // Subtract Packed Double-Precision Floating-Point Values
case NN_vsubps: // Packed Single-FP Subtract
case NN_vsubsd: // Subtract Scalar Double-Precision Floating-Point Values
case NN_vsubss: // Scalar Single-FP Subtract
case NN_vtestpd: // Packed Double-Precision Floating-Point Bit Test
case NN_vtestps: // Packed Single-Precision Floating-Point Bit Test
case NN_vucomisd: // Unordered Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
case NN_vucomiss: // Scalar Unordered Single-FP Compare and Set EFLAGS
case NN_vunpckhpd: // Unpack and Interleave High Packed Double-Precision Floating-Point Values
case NN_vunpckhps: // Unpack High Packed Single-FP Data
case NN_vunpcklpd: // Unpack and Interleave Low Packed Double-Precision Floating-Point Values
case NN_vunpcklps: // Unpack Low Packed Single-FP Data
case NN_vxorpd: // Bitwise Logical OR of Double-Precision Floating-Point Values
case NN_vxorps: // Bitwise Logical XOR for Single-FP Data
case NN_vzeroall: // Zero All YMM Registers
case NN_vzeroupper: // Zero Upper Bits of YMM Registers
SMP_fprintf(OutFile, "ERROR");
break;
// Transactional Synchronization Extensions
case NN_xabort: // Transaction Abort
case NN_xbegin: // Transaction Begin
case NN_xend: // Transaction End
case NN_xtest: // Test If In Transactional Execution
SMP_fprintf(OutFile, "ERROR");
break;
// Virtual PC synthetic instructions
case NN_vmgetinfo: // Virtual PC - Get VM Information
case NN_vmsetinfo: // Virtual PC - Set VM Information
case NN_vmdxdsbl: // Virtual PC - Disable Direct Execution
case NN_vmdxenbl: // Virtual PC - Enable Direct Execution
case NN_vmcpuid: // Virtual PC - Virtualized CPU Information
case NN_vmhlt: // Virtual PC - Halt
case NN_vmsplaf: // Virtual PC - Spin Lock Acquisition Failed
case NN_vmpushfd: // Virtual PC - Push virtualized flags register
case NN_vmpopfd: // Virtual PC - Pop virtualized flags register
case NN_vmcli: // Virtual PC - Clear Interrupt Flag
case NN_vmsti: // Virtual PC - Set Interrupt Flag
case NN_vmiretd: // Virtual PC - Return From Interrupt
case NN_vmsgdt: // Virtual PC - Store Global Descriptor Table
case NN_vmsidt: // Virtual PC - Store Interrupt Descriptor Table
case NN_vmsldt: // Virtual PC - Store Local Descriptor Table
case NN_vmstr: // Virtual PC - Store Task Register
case NN_vmsdte: // Virtual PC - Store to Descriptor Table Entry
case NN_vpcext: // Virtual PC - ISA extension
SMP_fprintf(OutFile, "ERROR");
break;
case NN_last:
SMP_fprintf(OutFile, "ERROR");
break;
default:
SMP_fprintf(OutFile, "ERROR");
break;
}
return;
} // end of PrintOpcode()
// MACHINE DEPENDENT: Is operand type a known type that we want to analyze?
bool MDKnownOperandType(STARSOpndType TempOp) {
bool GoodOpType = ((TempOp.type >= o_reg) && (TempOp.type <= o_xmmreg));
#if SMP_DEBUG_OPERAND_TYPES
if (!GoodOpType && (o_void != TempOp.type)) {
SMP_msg("WARNING: Operand type %d \n", TempOp.type);
}
#endif
return GoodOpType;
}
// Meet function over any two types in the type lattice.
SMPOperandType SMPTypeMeet(SMPOperandType Type1, SMPOperandType Type2) {
SMPOperandType MeetType = UNKNOWN;
bool ProfDerived = IsProfDerived(Type1) || IsProfDerived(Type2);
if (IsEqType(UNINIT, Type1))
MeetType = Type2;
else if (IsEqType(UNINIT, Type2) || IsEqType(Type1, Type2)
|| IsUnknown(Type1))
MeetType = Type1;
else if (IsNumeric(Type1)) {
if (IsNumeric(Type2)) // one is NUMERIC, one is CODEPTR
MeetType = NUMERIC;
else if (IsDataPtr(Type2) || IsUnknown(Type2))
MeetType = UNKNOWN;
else
SMP_msg("ERROR #1 in SMPTypeMeet.\n");
}
else if (IsDataPtr(Type1)) {
if (IsDataPtr(Type2)) // two different POINTER subtypes
MeetType = POINTER;
else if (IsNumeric(Type2) || IsUnknown(Type2))
MeetType = UNKNOWN;
else
SMP_msg("ERROR #2 in SMPTypeMeet.\n");
}
if (ProfDerived && IsNotEqType(UNINIT, MeetType))
MeetType = MakeProfDerived(MeetType);
return MeetType;
} // end of SMPTypeMeet()
// Meet function for SCCP constant propagation; updates NewConstStruct
void STARSConstantTypeMeet(struct STARS_SCCP_Const_Struct OldConstStruct, struct STARS_SCCP_Const_Struct &NewConstStruct) {
if ((OldConstStruct.ConstType != STARS_CONST_BOTTOM) && (NewConstStruct.ConstType != STARS_CONST_TOP)) {
// We have four possibilities. Three of them have NewConstStruct lower in the type lattice, which means the final
// result is simply the NewConstStruct (i.e. if Old == TOP, New == CONST or BOTTOM; or Old == CONST, New == BOTTOM).
// The fourth possibility is that Old == CONST, New == CONST, and we have to check the const values for consistency,
// lowering NewConstStruct to BOTTOM if they are inconsistent.
if ((OldConstStruct.ConstType == STARS_CONST_HAS_VALUE) && (NewConstStruct.ConstType == STARS_CONST_HAS_VALUE)) {
if (OldConstStruct.ConstValue != NewConstStruct.ConstValue) { // inconsistent const values
NewConstStruct.ConstType = STARS_CONST_BOTTOM;
}
}
}
else {
NewConstStruct = OldConstStruct;
}
return;
} // end of STARSConstantTypeMeet()
// *****************************************************************
// Class DisAsmString
// *****************************************************************
DisAsmString::DisAsmString(void) {
this->CurrAddr = BADADDR;
this->StringLen = 0;
this->CachedDisAsm[0] = '\0';
return;
}
char *DisAsmString::GetDisAsm(ea_t InstAddr, bool MarkerInst) {
if (InstAddr != this->CurrAddr) {
this->CurrAddr = InstAddr;
if (MarkerInst) {
this->SetMarkerInstText(InstAddr);
}
else {
bool IDAsuccess = SMP_generate_disasm_line(InstAddr, this->CachedDisAsm, sizeof(this->CachedDisAsm) - 1);
if (IDAsuccess) {
// Remove interactive color-coding tags.
this->StringLen = SMP_tag_remove(this->CachedDisAsm, this->CachedDisAsm, 0);
if (-1 >= StringLen) {
SMP_msg("ERROR: tag_remove failed at addr %lx \n", (unsigned long) InstAddr);
this->CachedDisAsm[0] = '\0';
}
}
else {
SMP_msg("ERROR: generate_disasm_line failed at addr %lx \n", (unsigned long) InstAddr);
this->CachedDisAsm[0] = '\0';
}
}
}
return (char *) this->CachedDisAsm;
} // end of DisAsmString::GetDisasm()
// Set the disasm text for the SSA marker instructions, which have no IDA Pro disasm because
// they are pseudo-instructions that we add at the top of each function to hold LiveIn name info.
void DisAsmString::SetMarkerInstText(ea_t InstAddr) {
if (InstAddr != this->CurrAddr) {
this->CurrAddr = InstAddr;
SMP_strncpy(this->CachedDisAsm, "\tfnop\t; Top of function SSA marker for SMP",
sizeof(this->CachedDisAsm) - 1);
this->StringLen = (ssize_t) strlen(this->CachedDisAsm);
}
return;
} // end of DisAsmString::SetMarkerInstText()
// *****************************************************************
// Class DefOrUse
// *****************************************************************
// Default constructor to make the compilers happy.
DefOrUse::DefOrUse(void) {
this->Operand.type = o_void;
this->SSANumber = -2;
this->OpType = UNINIT;
this->NonSpeculativeOpType = UNINIT;
this->MetadataStatus = DEF_METADATA_UNANALYZED;
this->booleans1 = 0;
return;
}
// Constructor.
DefOrUse::DefOrUse(STARSOpndType Ref, SMPOperandType Type, int SSASub) {
if (o_reg == Ref.type) {
// We want to map AH, AL, and AX to EAX, etc. throughout our data flow analysis
// and type inference systems.
CanonicalizeOpnd(Ref);
}
this->Operand = Ref;
this->SSANumber = SSASub;
this->OpType = Type;
assert(!IsProfDerived(Type));
this->NonSpeculativeOpType = Type;
this->MetadataStatus = DEF_METADATA_UNANALYZED;
this->booleans1 = 0;
return;
}
// Copy constructor.
DefOrUse::DefOrUse(const DefOrUse &CopyIn) {
*this = CopyIn;
return;
}
// Assignment operator for copy constructor use.
DefOrUse &DefOrUse::operator=(const DefOrUse &rhs) {
this->Operand = rhs.Operand;
this->OpType = rhs.OpType;
this->NonSpeculativeOpType = rhs.NonSpeculativeOpType;
this->SSANumber = rhs.SSANumber;
this->MetadataStatus = rhs.MetadataStatus;
this->booleans1 = rhs.booleans1;
return *this;
}
// Set the operand type for this DEF or USE - don't forget to take
// into account the speculative (profiler) status.
void DefOrUse::SetType(SMPOperandType Type, const SMPInstr *Instr) {
SMPOperandType OldType = this->OpType;
SMPOperandType NewType = Type;
if (Instr->GetBlock()->GetFunc()->GetIsSpeculative()) {
NewType = (SMPOperandType)(((int)NewType) | PROF_BASE);
if (!IsProfDerived(OldType))
this->NonSpeculativeOpType = OldType;
}
this->OpType = NewType;
}
void DefOrUse::SetMetadataStatus(SMPMetadataType NewStatus) {
// See if we are just updating explanation codes.
bool OldUsed = ((this->MetadataStatus >= DEF_METADATA_USED) && (this->MetadataStatus < DEF_METADATA_REDUNDANT));
if (OldUsed) {
bool NewUsed = ((NewStatus >= DEF_METADATA_USED) && (NewStatus < DEF_METADATA_REDUNDANT));
if (NewUsed) {
// Union the explanation codes.
int TempInt = (int) this->GetMetadataStatus();
TempInt |= (int) NewStatus;
this->MetadataStatus = (SMPMetadataType) TempInt;
return;
}
}
this->MetadataStatus = NewStatus;
return;
}
// Debug printing.
void DefOrUse::Dump(void) const {
PrintListOperand(this->Operand, this->SSANumber);
if (IsEqType(this->OpType , NUMERIC))
SMP_msg("N ");
else if (IsEqType(this->OpType , CODEPTR))
SMP_msg("C ");
else if (IsEqType(this->OpType , POINTER))
SMP_msg("P ");
else if (IsEqType(this->OpType , STACKPTR))
SMP_msg("S ");
else if (IsEqType(this->OpType , GLOBALPTR))
SMP_msg("G ");
else if (IsEqType(this->OpType , HEAPPTR))
SMP_msg("H ");
else if (IsEqType(this->OpType , PTROFFSET))
SMP_msg("O ");
else if (IsEqType(this->OpType , NEGATEDPTR))
SMP_msg("NegP ");
else if (IsEqType(this->OpType , UNKNOWN))
SMP_msg("U ");
/* emit the profile bit */
if (IsProfDerived(this->OpType))
SMP_msg("Pr ");
// Don't write anything for UNINIT OpType
// Emit the metadata status.
if (DEF_METADATA_UNUSED == this->MetadataStatus)
SMP_msg("Mn ");
else if (DEF_METADATA_USED == this->MetadataStatus)
SMP_msg("Mu ");
else if (DEF_METADATA_REDUNDANT == this->MetadataStatus)
SMP_msg("Mr ");
// Is the DEF possibly aliased because of an indirect write in
// the DEF-USE chain?
if (this->HasIndirectWrite())
SMP_msg("Al* ");
return;
} // end of DefOrUse::Dump()
// *****************************************************************
// Class DefOrUseSet
// *****************************************************************
// Default constructor.
DefOrUseSet::DefOrUseSet(void) {
this->Refs.clear();
return;
}
// Destructor.
DefOrUseSet::~DefOrUseSet() {
this->Refs.clear();
return;
}
// Find the reference for a given operand type.
set<DefOrUse, LessDefUse>::iterator DefOrUseSet::FindRef(STARSOpndType SearchOp) {
set<DefOrUse, LessDefUse>::iterator CurrRef;
DefOrUse DummyRef(SearchOp);
CurrRef = this->Refs.find(DummyRef);
return CurrRef;
}
// Insert a new DEF or USE; must be new, insert must succeed else we assert.
set<DefOrUse, LessDefUse>::iterator DefOrUseSet::InsertRef(DefOrUse Ref) {
pair<set<DefOrUse, LessDefUse>::iterator, bool> InsertResult;
InsertResult = this->Refs.insert(Ref);
assert(InsertResult.second);
return InsertResult.first;
}
// Set a Def or Use into the list, along with its type.
void DefOrUseSet::SetRef(STARSOpndType Ref, SMPOperandType Type, int SSASub) {
pair<set<DefOrUse, LessDefUse>::iterator, bool> InsertResult;
DefOrUse CurrRef(Ref, Type, SSASub);
InsertResult = this->Refs.insert(CurrRef);
if ((!(InsertResult.second)) && (o_reg != Ref.type)) {
SMP_msg("ERROR: Inserted duplicate DEF or USE.\n");
}
return;
}
// Change the indirect write status for a reference.
set<DefOrUse, LessDefUse>::iterator DefOrUseSet::SetOp(set<DefOrUse, LessDefUse>::iterator CurrRef, STARSOpndType NewOp) {
// To change a field within a set, we must grab a copy, change the copy,
// delete the old set member, and insert the updated copy as a new member.
assert(CurrRef != this->Refs.end());
DefOrUse NewCopy = (*CurrRef);
NewCopy.SetOp(NewOp);
this->Refs.erase(CurrRef);
pair<set<DefOrUse, LessDefUse>::iterator, bool> InsertResult;
InsertResult = this->Refs.insert(NewCopy);
assert(InsertResult.second);
return InsertResult.first;
} // end of DefOrUseSet::SetOp()
// Change the SSA subscript for a reference.
set<DefOrUse, LessDefUse>::iterator DefOrUseSet::SetSSANum(STARSOpndType CurrOp, int NewSSASub) {
// To change a field within a set, we must grab a copy, change the copy,
// delete the old set member, and insert the updated copy as a new member.
set<DefOrUse, LessDefUse>::iterator CurrRef = this->FindRef(CurrOp);
assert(CurrRef != this->Refs.end());
set<DefOrUse, LessDefUse>::iterator NextRef = CurrRef;
++NextRef;
DefOrUse NewCopy = (*CurrRef);
NewCopy.SetSSANum(NewSSASub);
this->Refs.erase(CurrRef);
CurrRef = this->Refs.insert(NextRef, NewCopy);
return CurrRef;
} // end of DefOrUseSet::SetSSANum()
// Change the operand type for a reference.
set<DefOrUse, LessDefUse>::iterator DefOrUseSet::SetType(STARSOpndType CurrOp, SMPOperandType Type, const SMPInstr* Instr) {
// To change a field within a set, we must grab a copy, change the copy,
// delete the old set member, and insert the updated copy as a new member.
set<DefOrUse, LessDefUse>::iterator CurrRef = this->FindRef(CurrOp);
assert(CurrRef != this->Refs.end());
#if 1
if (o_imm == CurrOp.type) {
if (UNINIT != CurrRef->GetType() && Type != CurrRef->GetType()) {
SMP_msg("ERROR: Changing type of immediate from %d to %d at %lx: ", CurrRef->GetType(), Type, (unsigned long) Instr->GetAddr());
CurrRef->Dump();
SMP_msg("\n");
SMPInstr InstCopy = (*Instr);
InstCopy.Dump();
}
}
#endif
DefOrUse NewCopy = (*CurrRef);
NewCopy.SetType(Type,Instr);
this->Refs.erase(CurrRef);
pair<set<DefOrUse, LessDefUse>::iterator, bool> InsertResult;
InsertResult = this->Refs.insert(NewCopy);
assert(InsertResult.second);
CurrRef = InsertResult.first;
return CurrRef;
} // end of DefOrUseSet::SetType()
// Change the Metadata type for a reference.
set<DefOrUse, LessDefUse>::iterator DefOrUseSet::SetMetadata(STARSOpndType CurrOp, SMPMetadataType Status) {
// To change a field within a set, we must grab a copy, change the copy,
// delete the old set member, and insert the updated copy as a new member.
set<DefOrUse, LessDefUse>::iterator CurrRef = this->FindRef(CurrOp);
assert(CurrRef != this->Refs.end());
DefOrUse NewCopy = (*CurrRef);
NewCopy.SetMetadataStatus(Status);
this->Refs.erase(CurrRef);
pair<set<DefOrUse, LessDefUse>::iterator, bool> InsertResult;
InsertResult = this->Refs.insert(NewCopy);
assert(InsertResult.second);
CurrRef = InsertResult.first;
return CurrRef;
} // end of DefOrUseSet::SetMetadata()
// Change the indirect write status for a reference.
set<DefOrUse, LessDefUse>::iterator DefOrUseSet::SetIndWrite(STARSOpndType CurrOp, bool IndWriteFlag) {
// To change a field within a set, we must grab a copy, change the copy,
// delete the old set member, and insert the updated copy as a new member.
set<DefOrUse, LessDefUse>::iterator CurrRef = this->FindRef(CurrOp);
assert(CurrRef != this->Refs.end());
DefOrUse NewCopy = (*CurrRef);
NewCopy.SetIndWrite(IndWriteFlag);
this->Refs.erase(CurrRef);
pair<set<DefOrUse, LessDefUse>::iterator, bool> InsertResult;
InsertResult = this->Refs.insert(NewCopy);
assert(InsertResult.second);
CurrRef = InsertResult.first;
return CurrRef;
} // end of DefOrUseSet::SetIndWrite()
// Change the ignore apparent truncation flag for a reference.
set<DefOrUse, LessDefUse>::iterator DefOrUseSet::SetNoTruncation(STARSOpndType CurrOp, bool NoTruncFlag) {
// To change a field within a set, we must grab a copy, change the copy,
// delete the old set member, and insert the updated copy as a new member.
set<DefOrUse, LessDefUse>::iterator CurrRef = this->FindRef(CurrOp);
assert(CurrRef != this->Refs.end());
DefOrUse NewCopy = (*CurrRef);
NewCopy.SetNoTruncation(NoTruncFlag);
this->Refs.erase(CurrRef);
pair<set<DefOrUse, LessDefUse>::iterator, bool> InsertResult;
InsertResult = this->Refs.insert(NewCopy);
assert(InsertResult.second);
CurrRef = InsertResult.first;
return CurrRef;
} // end of DefOrUseSet::SetNoTruncation()
// Change the ignore apparent overflow flag for a reference.
set<DefOrUse, LessDefUse>::iterator DefOrUseSet::SetNoOverflow(STARSOpndType CurrOp, bool NoOverflowFlag) {
// To change a field within a set, we must grab a copy, change the copy,
// delete the old set member, and insert the updated copy as a new member.
set<DefOrUse, LessDefUse>::iterator CurrRef = this->FindRef(CurrOp);
assert(CurrRef != this->Refs.end());
DefOrUse NewCopy = (*CurrRef);
NewCopy.SetNoOverflow(NoOverflowFlag);
this->Refs.erase(CurrRef);
pair<set<DefOrUse, LessDefUse>::iterator, bool> InsertResult;
InsertResult = this->Refs.insert(NewCopy);
assert(InsertResult.second);
CurrRef = InsertResult.first;
return CurrRef;
} // end of DefOrUseSet::SetNoOverflow()
// Debug printing.
void DefOrUseSet::Dump(void) const {
set<DefOrUse, LessDefUse>::iterator CurrRef;
for (CurrRef = this->Refs.begin(); CurrRef != this->Refs.end(); ++CurrRef) {
CurrRef->Dump();
}
SMP_msg("\n");
return;
}
// Do all types agree, ignoring any flags registers in the set? This is used
// for conditional move instructions; if all types agree, it does not matter
// whether the move happens or not.
bool DefOrUseSet::TypesAgreeNoFlags(void) {
bool FoundFirstUse = false;
set<DefOrUse, LessDefUse>::iterator CurrUse;
SMPOperandType UseType = UNINIT;
for (CurrUse = this->Refs.begin(); CurrUse != this->Refs.end(); ++CurrUse) {
if (!(CurrUse->GetOp().is_reg(X86_FLAGS_REG))) { // ignore flags
if (!FoundFirstUse) {
FoundFirstUse = true;
UseType = CurrUse->GetType();
}
else {
if (IsNotEqType(CurrUse->GetType(), UseType)) {
return false; // inconsistent types
}
}
}
}
return true;
} // end of DefOrUseSet::TypesAgreeNoFlags()
// *****************************************************************
// Class DefOrUseList
// *****************************************************************
// Default constructor.
DefOrUseList::DefOrUseList(void) {
this->Refs.clear();
return;
}
// Set a Def or Use into the list, along with its type.
void DefOrUseList::SetRef(STARSOpndType Ref, SMPOperandType Type, int SSASub) {
DefOrUse CurrRef(Ref, Type, SSASub);
this->Refs.push_back(CurrRef);
return;
}
// Get a reference by index.
DefOrUse DefOrUseList::GetRef(size_t index) const {
return Refs[index];
}
// Change the SSA subscript for a reference.
void DefOrUseList::SetSSANum(size_t index, int NewSSASub) {
this->Refs[index].SetSSANum(NewSSASub);
return;
}
// Change the operand type for a reference.
void DefOrUseList::SetType(size_t index, SMPOperandType Type, const SMPInstr* Instr) {
this->Refs[index].SetType(Type,Instr);
return;
}
// Debug printing.
void DefOrUseList::Dump(void) const {
for (size_t index = 0; index < this->Refs.size(); ++index) {
Refs[index].Dump();
}
SMP_msg("\n");
return;
}
// Erase duplicate entries, in case SMPInstr::MDFixupDefUseLists() adds one.
void DefOrUseList::EraseDuplicates(void) {
set<STARSOpndType, LessOp> TempRefs; // Use STL set to find duplicates
set<STARSOpndType, LessOp>::iterator TempIter;
vector<DefOrUse>::iterator RefIter;
RefIter = this->Refs.begin();
while (RefIter != this->Refs.end()) {
TempIter = TempRefs.find(RefIter->GetOp());
if (TempIter == TempRefs.end()) { // not already in set
TempRefs.insert(RefIter->GetOp());
++RefIter;
}
else { // found it in set already
RefIter = this->Refs.erase(RefIter);
}
}
return;
} // end of DefOrUseList::EraseDuplicates()
// *****************************************************************
// Class SMPPhiFunction
// *****************************************************************
// Constructor
SMPPhiFunction::SMPPhiFunction(int GlobIndex, const DefOrUse &Def) {
this->index = GlobIndex;
this->DefName = Def;
this->SubscriptedOps.clear();
return;
}
DefOrUse SMPPhiFunction::GetDefCopy(void) const {
DefOrUse DefCopy(this->DefName);
return DefCopy;
}
// Add a phi item to the list
void SMPPhiFunction::PushBack(DefOrUse Ref) {
this->SubscriptedOps.SetRef(Ref.GetOp(), Ref.GetType(), Ref.GetSSANum());
return;
}
// Set the SSA number of the defined variable.
void SMPPhiFunction::SetSSADef(int NewSSASub) {
this->DefName.SetSSANum(NewSSASub);
return;
}
// Set the SSA number of the input variable.
void SMPPhiFunction::SetSSARef(size_t index, int NewSSASub) {
this->SubscriptedOps.SetSSANum(index, NewSSASub);
return;
}
// Set the type of the defined variable.
void SMPPhiFunction::SetDefType(SMPOperandType Type, const SMPInstr* Instr) {
this->DefName.SetType(Type, Instr);
return;
}
// Set the type of the input variable.
void SMPPhiFunction::SetRefType(size_t index, SMPOperandType Type, const SMPInstr* Instr) {
this->SubscriptedOps.SetType(index, Type, Instr);
return;
}
// Set the metadata status of the DEF variable.
void SMPPhiFunction::SetDefMetadata(SMPMetadataType Status) {
this->DefName.SetMetadataStatus(Status);
return;
} // end of SMPPhiFunction::SetDefMetadata()
// Does at least one USE have a type other than UNINIT?
bool SMPPhiFunction::HasTypedUses(void) {
size_t index;
for (index = 0; index < this->GetPhiListSize(); ++index) {
if (UNINIT != this->GetUseType(index))
return true;
}
return false;
} // end of SMPPhiFunction::HasTypedUses()
// Return the result of applying the conditional type propagation meet operator
// over all the USE types.
SMPOperandType SMPPhiFunction::ConditionalMeetType(SMPBasicBlock *CurrBlock) const {
SMPOperandType MeetType;
SMPOperandType PtrType = UNINIT;
SMPOperandType NumericType = UNINIT; // can end up NUMERIC or CODEPTR
bool FoundUNINIT = false; // any USE type UNINIT?
bool FoundNUMERIC = false; // any USE type NUMERIC?
bool FoundZero = false; // was DEF to zero? (could be POINTER or NUMERIC
bool FoundPOINTER = false; // includes all POINTER subtypes
bool FoundUNKNOWN = false; // any USE type UNKNOWN?
bool FoundPTROFFSET = false; // any USE type PTROFFSET?
bool FoundNEGATEDPTR = false; // any USE type NEGATEDPTR?
bool ProfilerDerived = false; // was any USE type Profiler-derived?
list<size_t> ZeroConstIndices;
ea_t BlockStartAddr = CurrBlock->GetFirstAddr(); // for debugging
STARSOpndType PhiOp = this->GetAnyOp();
for (size_t index = 0; index < this->GetPhiListSize(); ++index) {
SMPOperandType UseType = this->GetUseType(index);
if (IsEqType(UseType, UNINIT))
FoundUNINIT = true;
else if (IsNumeric(UseType)) {
// Check for possibility that we aggressively declared NUMERIC when register was set to zero.
int UseSSANum = this->GetUseSSANum(index);
bool CurrentUseZeroCase = false;
if (MDIsDataFlowOpnd(PhiOp, false)) {
ea_t DefAddr = CurrBlock->GetFunc()->GetGlobalDefAddr(PhiOp, UseSSANum);
// Handle simple case: DEF is in an instruction.
if ((BADADDR != DefAddr) && (DefAddr < STARS_PSEUDO_ID_MIN)) {
SMPInstr *DefInst = CurrBlock->GetFunc()->GetInstFromAddr(DefAddr);
CurrentUseZeroCase = DefInst->IsSetToZero();
}
}
if (CurrentUseZeroCase) {
FoundZero = true;
ZeroConstIndices.push_back(index);
}
else {
FoundNUMERIC = true;
if (IsEqType(NumericType, CODEPTR)) {
// Already refined. If current type agrees, leave it
// alone, else revert to generic type NUMERIC.
if (IsNotEqType(UseType, NumericType))
NumericType = NUMERIC;
}
else {
// Have not yet refined NumericType; might still be UNINIT.
if (IsEqType(UNINIT, NumericType))
NumericType = UseType;
else { // NumericType is NUMERIC; leave it as NUMERIC.
assert(IsEqType(NUMERIC, NumericType));
}
}
}
}
else if (IsDataPtr(UseType)) {
FoundPOINTER = true;
// Perform a meet over the pointer types.
if (IsRefinedDataPtr(PtrType)) {
// Already refined. If current type agrees, leave it
// alone, else revert to generic type POINTER.
if (IsNotEqType(UseType, PtrType))
PtrType = POINTER;
}
else {
// Have not yet refined PtrType; might still be UNINIT.
if (IsEqType(UNINIT, PtrType))
PtrType = UseType;
else { // PtrType is POINTER because we saw POINTER or
// had a conflict between pointer refinements; leave
// it as POINTER.
assert(IsEqType(POINTER, PtrType));
}
}
}
else if (IsEqType(PTROFFSET, UseType))
FoundPTROFFSET = true;
else if (IsEqType(NEGATEDPTR, UseType))
FoundNEGATEDPTR = true;
else if (IsUnknown(UseType))
FoundUNKNOWN = true;
if (IsProfDerived(UseType))
ProfilerDerived = true;
}
// Use the boolean flags to compute the meet function.
if (FoundUNKNOWN || (FoundNUMERIC && FoundPOINTER)
|| ((FoundNUMERIC || FoundPOINTER || FoundNEGATEDPTR) && FoundPTROFFSET)
|| ((FoundNUMERIC || FoundPOINTER || FoundPTROFFSET) && FoundNEGATEDPTR))
MeetType = UNKNOWN;
else if (FoundNUMERIC)
MeetType = NumericType;
else if (FoundPOINTER) {
MeetType = PtrType;
if (FoundZero) { // mixture of POINTER and const zero DEFs, i.e. ptr := NULL;
// Undo the aggressive NUMERIC inference when registers are set to zero.
// NOTE: There cannot be any alterations to the reg between the zero DEF and
// the current block on at least one path, or it would not show up in the Phi function with the
// current SSA number.
do {
size_t ZeroConstIndex = ZeroConstIndices.front();
int UseSSANum = this->GetUseSSANum(ZeroConstIndex);
ea_t DefAddr = CurrBlock->GetFunc()->GetGlobalDefAddr(PhiOp, UseSSANum);
// Handle simple case: DEF is in an instruction.
if ((BADADDR != DefAddr) && (DefAddr < STARS_PSEUDO_ID_MIN)) {
SMPInstr *DefInst = CurrBlock->GetFunc()->GetInstFromAddr(DefAddr);
set<DefOrUse, LessDefUse>::iterator DefIter = DefInst->SetDefType(PhiOp, PtrType);
#if 0
SMP_msg("INFO: Converting zeroed reg from NUMERIC to POINTER at %lx for Block at %lx\n",
(unsigned long) DefAddr, (unsigned long) BlockStartAddr);
#endif
CurrBlock->GetFunc()->ResetProcessedBlocks();
SMPBasicBlock *DefBlock = CurrBlock->GetFunc()->GetBlockFromInstAddr(DefAddr);
#if 0 // Causes infinite loops, crashes; need to debug !!!!****!!!!
DefBlock->PropagateGlobalDefType(PhiOp, PtrType, UseSSANum, false, true);
#else
DefBlock->PropagateGlobalDefType(PhiOp, PtrType, UseSSANum, false, false);
#endif
}
ZeroConstIndices.pop_front();
} while (!ZeroConstIndices.empty());
}
}
else if (FoundPTROFFSET)
MeetType = PTROFFSET;
else if (FoundNEGATEDPTR)
MeetType = NEGATEDPTR;
else if (FoundZero && (!FoundUNINIT)) // nothing but zeroes
MeetType = NUMERIC;
else {
assert(FoundUNINIT);
MeetType = UNINIT;
}
if (ProfilerDerived)
MeetType = MakeProfDerived(MeetType);
return MeetType;
} // end of SMPPhiFunction::ConditionalMeetType()
// Debug printing.
void SMPPhiFunction::Dump(void) const {
SMP_msg(" DEF: ");
this->DefName.Dump();
SMP_msg(" USEs: ");
this->SubscriptedOps.Dump();
return;
}
// *****************************************************************
// Class SMPDefUseChain
// *****************************************************************
// Constructors
SMPDefUseChain::SMPDefUseChain(void) {
this->SSAName.type = o_void;
this->RefInstrs.clear();
this->RefInstrs.push_back((unsigned short) BADADDR);
this->IndWrite = false;
return;
}
SMPDefUseChain::SMPDefUseChain(STARSOpndType Name, ea_t Def) {
this->SetName(Name);
this->RefInstrs.push_back(Def);
this->IndWrite = false;
return;
}
// Set the variable name.
void SMPDefUseChain::SetName(STARSOpndType Name) {
if (o_reg == Name.type) {
// We want to map AH, AL, and AX to EAX, etc. throughout our data flow analysis
// and type inference systems.
CanonicalizeOpnd(Name);
}
this->SSAName = Name;
return;
}
// Set the DEF instruction.
void SMPDefUseChain::SetDef(ea_t Def) {
this->RefInstrs[0] = (unsigned short) Def;
return;
}
// Push a USE onto the list
void SMPDefUseChain::PushUse(ea_t Use) {
this->RefInstrs.push_back((unsigned short) Use);
return;
}
// Set the indirect memory write flag.
void SMPDefUseChain::SetIndWrite(bool IndMemWrite) {
this->IndWrite = IndMemWrite;
return;
}
// DEBUG dump.
void SMPDefUseChain::Dump(int SSANum) const {
SMP_msg("DEF-USE chain for: ");
PrintListOperand(this->SSAName, SSANum);
if (this->RefInstrs.size() < 1) {
SMP_msg(" no references.\n");
return;
}
SMP_msg("\n DEF: %x USEs: ", this->RefInstrs.at(0));
size_t index;
for (index = 1; index < this->RefInstrs.size(); ++index)
SMP_msg("%x ", this->RefInstrs.at(index));
SMP_msg("\n");
return;
} // end of SMPDefUseChain::Dump()
// *****************************************************************
// Class SMPDUChainArray
// *****************************************************************
SMPDUChainArray::SMPDUChainArray(void) {
this->SSAName.type = o_void;
this->DUChains.clear();
return;
}
SMPDUChainArray::SMPDUChainArray(STARSOpndType Name, ea_t FirstAddrMinusOne) {
if (o_reg == Name.type) {
// We want to map AH, AL, and AX to EAX, etc. throughout our data flow analysis
// and type inference systems.
CanonicalizeOpnd(Name);
}
this->SSAName = Name;
this->BaseAddr = FirstAddrMinusOne;
this->DUChains.clear();
return;
}
ea_t SMPDUChainArray::GetLastUse(int SSANum) const {
ea_t TempAddr = DUChains.at(SSANum).GetLastUse();
if (BADADDR != TempAddr) {
// If BADADDR, leave it as BADADDR. Otherwise, add in BaseAddr.
TempAddr += this->BaseAddr;
}
return TempAddr;
}
void SMPDUChainArray::SetName(STARSOpndType Name, ea_t FirstAddrMinusOne) {
if (o_reg == Name.type) {
// We want to map AH, AL, and AX to EAX, etc. throughout our data flow analysis
// and type inference systems.
CanonicalizeOpnd(Name);
}
this->SSAName = Name;
this->BaseAddr = FirstAddrMinusOne;
return;
}
// DEBUG dump.
void SMPDUChainArray::Dump(void) const {
size_t index;
for (index = 0; index < this->GetSize(); ++index) {
this->DUChains.at(index).Dump((int) index);
}
return;
}
// *****************************************************************
// Class SMPCompleteDUChains
// *****************************************************************
// DEBUG dump.
void SMPCompleteDUChains::Dump(void) const {
size_t index;
for (index = 0; index < this->ChainsByName.size(); ++index) {
this->ChainsByName.at(index).Dump();
}
return;
} // end of SMPCompleteDUChains::Dump()
// *****************************************************************
// Class STARSBitSet
// *****************************************************************
// Constructors.
STARSBitSet::STARSBitSet() {
this->BitLimit = 0;
}
// Get methods
bool STARSBitSet::GetBit(size_t BitIndex) const {
size_t ByteIndex = BitIndex / 8;
size_t BitNumber = BitIndex % 8;
assert(BitIndex <= this->BitLimit);
return (0 != (this->STARSBits.at(ByteIndex) & STARSBitMasks[BitNumber]));
}
// Set methods
void STARSBitSet::AllocateBits(size_t Size) {
size_t Bytes = Size / 8;
size_t ExtraBits = Size % 8;
this->BitLimit = Size;
if (0 != ExtraBits) {
this->STARSBits.resize(1 + Bytes);
}
else {
this->STARSBits.resize(Bytes);
}
for (Bytes = 0; Bytes < this->STARSBits.size(); ++Bytes) {
this->STARSBits[Bytes] = 0;
}
}
void STARSBitSet::SetBit(size_t BitIndex) {
size_t ByteIndex = BitIndex / 8;
size_t BitNumber = BitIndex % 8;
assert(BitIndex <= this->BitLimit);
this->STARSBits[ByteIndex] |= STARSBitMasks[BitNumber];
return;
}
void STARSBitSet::ResetBit(size_t BitIndex) {
size_t ByteIndex = BitIndex / 8;
size_t BitNumber = BitIndex % 8;
assert(BitIndex <= this->BitLimit);
this->STARSBits[ByteIndex] &= (~STARSBitMasks[BitNumber]);
return;
}
// Query methods
// Returns false if all bits are zero, true otherwise.
bool STARSBitSet::IsAnyBitSet(void) const {
bool FoundSetBit = false;
size_t ByteIndex;
for (ByteIndex = 0; ByteIndex < this->STARSBits.size(); ++ByteIndex) {
if (0 != this->STARSBits[ByteIndex]) {
FoundSetBit = true;
break;
}
}
return FoundSetBit;
}
// Map system or library call name to FG info about its return value.
static map<string, struct FineGrainedInfo> ReturnRegisterTypeMap;
// Map system or library call name to the annotation substring that
// guides saturating arithmetic or other continuation policies in
// the case of integer error detection of a value passed to that call.
// If we don't care about a certain call, we return an empty string.
static map<string, string> IntegerErrorCallSinkMap;
void InitIntegerErrorCallSinkMap(void) {
pair<string, string> MapEntry;
pair<map<string, string>::iterator, bool> InsertResult;
MapEntry.first = string("malloc");
MapEntry.second = string("SINKMALLOC");
InsertResult = IntegerErrorCallSinkMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("calloc");
MapEntry.second = string("SINKMALLOC");
InsertResult = IntegerErrorCallSinkMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("realloc");
MapEntry.second = string("SINKMALLOC");
InsertResult = IntegerErrorCallSinkMap.insert(MapEntry);
assert(InsertResult.second);
return;
}
// Return sink string for call name from the sink map.
// If we don't care find the call name, we return an empty string.
void GetSinkStringForCallName(string CalleeName, string &SinkString) {
map<string, string>::iterator MapIter;
SinkString.clear(); // empty string, append map string if found later
MapIter = IntegerErrorCallSinkMap.find(CalleeName);
if (MapIter != IntegerErrorCallSinkMap.end()) { // found it
SinkString.append(MapIter->second);
}
return;
}
// Map system or library call name to the argument number that
// should have an unsigned value and should be guarded from the
// signedness error that results from copying a signed value
// into the outgoing argument. Argument numbers are zero-based.
// We will return 0 when there is no argument to worry about
// for a particular library or system call name.
static map<string, unsigned int> UnsignedArgPositionMap;
void InitUnsignedArgPositionMap(void) {
pair<string, unsigned int> MapEntry;
pair<map<string, unsigned int>::iterator, bool> InsertResult;
// <string.h>
MapEntry.first = string("memchr");
MapEntry.second = STARS_ARG_POS_2;
InsertResult = UnsignedArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("memcmp");
MapEntry.second = STARS_ARG_POS_2;
InsertResult = UnsignedArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("memcpy");
MapEntry.second = STARS_ARG_POS_2;
InsertResult = UnsignedArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("memmove");
MapEntry.second = STARS_ARG_POS_2;
InsertResult = UnsignedArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("memset");
MapEntry.second = STARS_ARG_POS_2;
InsertResult = UnsignedArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strncat");
MapEntry.second = STARS_ARG_POS_2;
InsertResult = UnsignedArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strncmp");
MapEntry.second = STARS_ARG_POS_2;
InsertResult = UnsignedArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strncpy");
MapEntry.second = STARS_ARG_POS_2;
InsertResult = UnsignedArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strxfrm");
MapEntry.second = STARS_ARG_POS_2;
InsertResult = UnsignedArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
// <stdlib.h>
MapEntry.first = string("malloc");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = UnsignedArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("calloc");
MapEntry.second = (STARS_ARG_POS_0 | STARS_ARG_POS_1);
InsertResult = UnsignedArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("realloc");
MapEntry.second = STARS_ARG_POS_1;
InsertResult = UnsignedArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("bsearch");
MapEntry.second = (STARS_ARG_POS_2 | STARS_ARG_POS_3);
InsertResult = UnsignedArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("qsort");
MapEntry.second = (STARS_ARG_POS_1 | STARS_ARG_POS_2);
InsertResult = UnsignedArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("mblen");
MapEntry.second = STARS_ARG_POS_1;
InsertResult = UnsignedArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("mbtowc");
MapEntry.second = STARS_ARG_POS_2;
InsertResult = UnsignedArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("mbstowcs");
MapEntry.second = STARS_ARG_POS_2;
InsertResult = UnsignedArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("wcstombs");
MapEntry.second = STARS_ARG_POS_2;
InsertResult = UnsignedArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
// <stdio.h>
MapEntry.first = string("setvbuf");
MapEntry.second = STARS_ARG_POS_3;
InsertResult = UnsignedArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
// <time.h>
MapEntry.first = string("strftime");
MapEntry.second = STARS_ARG_POS_1;
InsertResult = UnsignedArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
return;
} // end of InitUnsignedArgPositionMap()
// Return unsigned arg position bitset for call name from the unsigned arg map.
// If we don't find the call name, we return 0 in ArgPosBits.
void GetUnsignedArgPositionsForCallName(string CalleeName, unsigned int &ArgPosBits) {
map<string, unsigned int>::iterator MapIter;
ArgPosBits = 0; // Change if found later
MapIter = UnsignedArgPositionMap.find(CalleeName);
if (MapIter != UnsignedArgPositionMap.end()) { // found it
ArgPosBits = MapIter->second;
}
return;
}
// Map of function names to arguments that are dangerous to supply
// with user-tainted input values.
static map<string, unsigned int> TaintWarningArgPositionMap;
void InitTaintWarningArgPositionMap(void) {
pair<string, unsigned int> MapEntry;
pair<map<string, unsigned int>::iterator, bool> InsertResult;
// <string.h>
MapEntry.first = string("memchr");
MapEntry.second = STARS_ARG_POS_2;
InsertResult = TaintWarningArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("memcmp");
MapEntry.second = STARS_ARG_POS_2;
InsertResult = TaintWarningArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("memcpy");
MapEntry.second = STARS_ARG_POS_2;
InsertResult = TaintWarningArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("memmove");
MapEntry.second = STARS_ARG_POS_2;
InsertResult = TaintWarningArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("memset");
MapEntry.second = STARS_ARG_POS_2;
InsertResult = TaintWarningArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strncat");
MapEntry.second = STARS_ARG_POS_2;
InsertResult = TaintWarningArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strncmp");
MapEntry.second = STARS_ARG_POS_2;
InsertResult = TaintWarningArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strncpy");
MapEntry.second = STARS_ARG_POS_2;
InsertResult = TaintWarningArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strxfrm");
MapEntry.second = STARS_ARG_POS_2;
InsertResult = TaintWarningArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
// <stdlib.h>
MapEntry.first = string("malloc");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = TaintWarningArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("calloc");
MapEntry.second = (STARS_ARG_POS_0 | STARS_ARG_POS_1);
InsertResult = TaintWarningArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("realloc");
MapEntry.second = STARS_ARG_POS_1;
InsertResult = TaintWarningArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("bsearch");
MapEntry.second = (STARS_ARG_POS_2 | STARS_ARG_POS_3);
InsertResult = TaintWarningArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("qsort");
MapEntry.second = (STARS_ARG_POS_1 | STARS_ARG_POS_2);
InsertResult = TaintWarningArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("mblen");
MapEntry.second = STARS_ARG_POS_1;
InsertResult = TaintWarningArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("mbtowc");
MapEntry.second = STARS_ARG_POS_2;
InsertResult = TaintWarningArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("mbstowcs");
MapEntry.second = STARS_ARG_POS_2;
InsertResult = TaintWarningArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("wcstombs");
MapEntry.second = STARS_ARG_POS_2;
InsertResult = TaintWarningArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
// <stdio.h>
MapEntry.first = string("setvbuf");
MapEntry.second = STARS_ARG_POS_3;
InsertResult = TaintWarningArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
return;
} // end of InitTaintWarningArgPositionMap()
// Return dangerous-to-taint arg position bitset for call name from the taint warning map.
// If we don't find the call name, we return 0 in ArgPosBits.
void GetTaintWarningArgPositionsForCallName(string CalleeName, unsigned int &ArgPosBits) {
map<string, unsigned int>::iterator MapIter;
ArgPosBits = 0; // Change if found later
MapIter = TaintWarningArgPositionMap.find(CalleeName);
if (MapIter != TaintWarningArgPositionMap.end()) { // found it
ArgPosBits = MapIter->second;
}
return;
}
// Map of function names to POINTER argument positions.
static map<string, unsigned int> PointerArgPositionMap;
// Init map of system or library call name to the argument number that
// should have a POINTER value.
void InitPointerArgPositionMap(void) {
pair<string, unsigned int> MapEntry;
pair<map<string, unsigned int>::iterator, bool> InsertResult;
// <locale.h>
MapEntry.first = string("setlocale");
MapEntry.second = STARS_ARG_POS_1;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
// <math.h>
MapEntry.first = string("modf");
MapEntry.second = STARS_ARG_POS_1;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
// <string.h>
MapEntry.first = string("memchr");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("memcmp");
MapEntry.second = STARS_ARG_POS_0 | STARS_ARG_POS_1;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("memcpy");
MapEntry.second = STARS_ARG_POS_0 | STARS_ARG_POS_1;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("memmove");
MapEntry.second = STARS_ARG_POS_0 | STARS_ARG_POS_1;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("memset");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strcat");
MapEntry.second = STARS_ARG_POS_0 | STARS_ARG_POS_1;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strncat");
MapEntry.second = STARS_ARG_POS_0 | STARS_ARG_POS_1;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strcmp");
MapEntry.second = STARS_ARG_POS_0 | STARS_ARG_POS_1;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strncmp");
MapEntry.second = STARS_ARG_POS_0 | STARS_ARG_POS_1;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strcpy");
MapEntry.second = STARS_ARG_POS_0 | STARS_ARG_POS_1;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strncpy");
MapEntry.second = STARS_ARG_POS_0 | STARS_ARG_POS_1;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strcoll");
MapEntry.second = STARS_ARG_POS_0 | STARS_ARG_POS_1;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strxfrm");
MapEntry.second = STARS_ARG_POS_0 | STARS_ARG_POS_1;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strchr");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strcspn");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strpbrk");
MapEntry.second = STARS_ARG_POS_0 | STARS_ARG_POS_1;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strrchr");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strspn");
MapEntry.second = STARS_ARG_POS_0 | STARS_ARG_POS_1;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strstr");
MapEntry.second = STARS_ARG_POS_0 | STARS_ARG_POS_1;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strtok");
MapEntry.second = STARS_ARG_POS_0 | STARS_ARG_POS_1;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strlen");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
// <stdlib.h>
MapEntry.first = string("atof");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("atoi");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("atol");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strtod");
MapEntry.second = STARS_ARG_POS_0 | STARS_ARG_POS_1;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strtol");
MapEntry.second = STARS_ARG_POS_0 | STARS_ARG_POS_1;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strtoul");
MapEntry.second = STARS_ARG_POS_0 | STARS_ARG_POS_1;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("free");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("realloc");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("getenv");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("system");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("bsearch");
MapEntry.second = (STARS_ARG_POS_0 | STARS_ARG_POS_1);
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("qsort");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("mblen");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("mbtowc");
MapEntry.second = (STARS_ARG_POS_0 | STARS_ARG_POS_1);
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("wctomb");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("mbstowcs");
MapEntry.second = (STARS_ARG_POS_0 | STARS_ARG_POS_1);
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("wcstombs");
MapEntry.second = (STARS_ARG_POS_0 | STARS_ARG_POS_1);
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
// <stdio.h>
MapEntry.first = string("remove");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("rename");
MapEntry.second = (STARS_ARG_POS_0 | STARS_ARG_POS_1);
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("tmpnam");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("fclose");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("fflush");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("fopen");
MapEntry.second = (STARS_ARG_POS_0 | STARS_ARG_POS_1);
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("freopen");
MapEntry.second = (STARS_ARG_POS_0 | STARS_ARG_POS_1 | STARS_ARG_POS_2);
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("setbuf");
MapEntry.second = (STARS_ARG_POS_0 | STARS_ARG_POS_1);
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("setvbuf");
MapEntry.second = (STARS_ARG_POS_0 | STARS_ARG_POS_1);
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("fprintf");
MapEntry.second = (STARS_ARG_POS_0 | STARS_ARG_POS_1);
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("fscanf");
MapEntry.second = (STARS_ARG_POS_0 | STARS_ARG_POS_1);
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("printf");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("scanf");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("sprintf");
MapEntry.second = (STARS_ARG_POS_0 | STARS_ARG_POS_1);
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("sscanf");
MapEntry.second = (STARS_ARG_POS_0 | STARS_ARG_POS_1);
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("vfprintf");
MapEntry.second = (STARS_ARG_POS_0 | STARS_ARG_POS_1);
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("vprintf");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("vsprintf");
MapEntry.second = (STARS_ARG_POS_0 | STARS_ARG_POS_1);
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("fgetc");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("fgets");
MapEntry.second = (STARS_ARG_POS_0 | STARS_ARG_POS_2);
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("fputc");
MapEntry.second = STARS_ARG_POS_1;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("fputs");
MapEntry.second = (STARS_ARG_POS_0 | STARS_ARG_POS_1);
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("getc");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("gets");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("putc");
MapEntry.second = STARS_ARG_POS_1;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("puts");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("ungetc");
MapEntry.second = STARS_ARG_POS_1;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("fread");
MapEntry.second = (STARS_ARG_POS_0 | STARS_ARG_POS_3);
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("fwrite");
MapEntry.second = (STARS_ARG_POS_0 | STARS_ARG_POS_3);
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("fgetpos");
MapEntry.second = (STARS_ARG_POS_0 | STARS_ARG_POS_1);
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("fseek");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("fsetpos");
MapEntry.second = (STARS_ARG_POS_0 | STARS_ARG_POS_1);
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("ftell");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("rewind");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("clearerr");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("feof");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("ferror");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("perror");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
// <time.h>
MapEntry.first = string("mktime");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("time");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("asctime");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("ctime");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("gmtime");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("localtime");
MapEntry.second = STARS_ARG_POS_0;
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = string("strftime");
MapEntry.second = (STARS_ARG_POS_0 | STARS_ARG_POS_2 | STARS_ARG_POS_3);
InsertResult = PointerArgPositionMap.insert(MapEntry);
assert(InsertResult.second);
return;
} // end of InitPointerArgPositionMap()
// Return POINTER arg position bitset for call name from the POINTER arg map.
// If we don't find the call name, we return 0 in ArgPosBits.
void GetPointerArgPositionsForCallName(string CalleeName, unsigned int &ArgPosBits) {
map<string, unsigned int>::iterator MapIter;
ArgPosBits = 0; // Change if found later
MapIter = PointerArgPositionMap.find(CalleeName);
if (MapIter != PointerArgPositionMap.end()) { // found it
ArgPosBits = MapIter->second;
}
return;
}
// Utility to count bits set in an unsigned int, e.g. ArgPosBits.
unsigned int CountBitsSet(unsigned int ArgPosBits) {
unsigned int count; // count accumulates the total bits set in ArgPosBits
for (count = 0; ArgPosBits; ++count) {
ArgPosBits &= (ArgPosBits - 1); // clear the least significant bit set
}
// Brian Kernighan's method goes through as many iterations as there are set bits.
// So if we have a 32-bit word with only the high bit set, then it will only go once through the loop.
// Published in 1988, the C Programming Language 2nd Ed. (by Brian W. Kernighan and Dennis M. Ritchie) mentions this in exercise 2-9.
// On April 19, 2006 Don Knuth pointed out to me that this method "was first published by Peter Wegner in CACM 3 (1960), 322.
// (Also discovered independently by Derrick Lehmer and published in 1964 in a book edited by Beckenbach.)"
return count;
}
// Initialize the FG info for the return register from any library function
// whose name implies that we know certain return values (e.g. atoi() returns
// a signed integer, while strtoul() returns an unsigned long).
void GetLibFuncFGInfo(string FuncName, struct FineGrainedInfo &InitFGInfo) {
map<string, struct FineGrainedInfo>::iterator FindIter;
FindIter = ReturnRegisterTypeMap.find(FuncName);
if (FindIter == ReturnRegisterTypeMap.end()) { // not found
InitFGInfo.SignMiscInfo = 0;
InitFGInfo.SizeInfo = 0;
}
else { // found
InitFGInfo = FindIter->second;
}
return;
} // end of GetLibFuncFGInfo()
// Initialize the lookup maps that are used to define the FG info that can
// be inferred from a library function name.
void InitLibFuncFGInfoMaps(void) {
STARSOpndType DummyOp = InitOp;
struct FineGrainedInfo FGEntry;
pair<string, struct FineGrainedInfo> MapEntry;
pair<map<string, struct FineGrainedInfo>::iterator, bool> InsertResult;
// Add functions that return signed integers.
FGEntry.SignMiscInfo = FG_MASK_SIGNED;
FGEntry.SizeInfo = (FG_MASK_INTEGER | ComputeOperandBitWidthMask(DummyOp, sizeof(int)));
MapEntry.second = FGEntry;
MapEntry.first = "atoi";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "strcmp";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "strcoll";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "strncmp";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "memcmp";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "isalnum";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "isalpha";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "islower";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "isupper";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "isdigit";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "isxdigit";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "iscntrl";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "isgraph";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "isblank";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "isspace";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "isprint";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "ispunct";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
// Functions that return signed longs.
if (sizeof(long int) != sizeof(int)) {
FGEntry.SizeInfo = (FG_MASK_INTEGER | ComputeOperandBitWidthMask(DummyOp, sizeof(long int)));
MapEntry.second = FGEntry;
}
MapEntry.first = "atol";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "strtol";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
// Functions that return signed long longs.
if (sizeof(long long int) != sizeof(long int)) {
FGEntry.SizeInfo = (FG_MASK_INTEGER | ComputeOperandBitWidthMask(DummyOp, sizeof(long long int)));
MapEntry.second = FGEntry;
}
MapEntry.first = "atoll";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "strtoll";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
// Functions that return unsigned long longs.
FGEntry.SignMiscInfo = FG_MASK_UNSIGNED;
MapEntry.second = FGEntry;
MapEntry.first = "strtoull";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
// Functions that return unsigned longs.
if (sizeof(long long int) != sizeof(long int)) {
FGEntry.SizeInfo = (FG_MASK_INTEGER | ComputeOperandBitWidthMask(DummyOp, sizeof(long int)));
MapEntry.second = FGEntry;
}
MapEntry.first = "strtoul";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
// Functions that return size_t.
FGEntry.SizeInfo = (FG_MASK_INTEGER | ComputeOperandBitWidthMask(DummyOp, sizeof(size_t)));
FGEntry.SignMiscInfo = FG_MASK_UNSIGNED;
MapEntry.second = FGEntry;
MapEntry.first = "strlen";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "strxfrm";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "strspn";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "strcspn";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "strftime";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
// Functions that return (char *).
FGEntry.SizeInfo = (FG_MASK_DATAPOINTER | ComputeOperandBitWidthMask(DummyOp, sizeof(char *)));
FGEntry.SignMiscInfo = FG_MASK_UNSIGNED;
MapEntry.second = FGEntry;
MapEntry.first = "strcpy";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "strncpy";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "strcat";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "strncat";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "strchr";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "strrchr";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "strpbrk";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "strstr";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "strtok";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "strerror";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "asctime";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "ctime";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
// Functions that return (void *) or a similar data pointer.
FGEntry.SizeInfo = (FG_MASK_DATAPOINTER | ComputeOperandBitWidthMask(DummyOp, sizeof(void *)));
FGEntry.SignMiscInfo = FG_MASK_UNSIGNED;
MapEntry.second = FGEntry;
MapEntry.first = "setlocale";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "localeconv";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "malloc";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "calloc";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "realloc";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "memchr";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "memcpy";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "mempcpy"; // non-standard, found in glibc
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "memmove";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "memset";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "gmtime";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
MapEntry.first = "localtime";
InsertResult = ReturnRegisterTypeMap.insert(MapEntry);
assert(InsertResult.second);
// Functions that return bool.
FGEntry.SizeInfo = (FG_MASK_INTEGER | ComputeOperandBitWidthMask(DummyOp, sizeof(bool)));
FGEntry.SignMiscInfo = FG_MASK_UNSIGNED;
MapEntry.second = FGEntry;
// NOTE: Add <math.h> functions later.
return;
} // end of InitLibFuncFGInfoMaps()
// Initialize the DFACategory[] array to define instruction classes
// for the purposes of data flow analysis.
void InitDFACategory(void) {
// Default category is 0, not the start or end of a basic block.
(void) memset(DFACategory, 0, sizeof(DFACategory));
DFACategory[NN_call] = CALL; // Call Procedure
DFACategory[NN_callfi] = INDIR_CALL; // Indirect Call Far Procedure
DFACategory[NN_callni] = INDIR_CALL; // Indirect Call Near Procedure
DFACategory[NN_hlt] = HALT; // Halt
DFACategory[NN_int] = INDIR_CALL; // Call to Interrupt Procedure
DFACategory[NN_into] = INDIR_CALL; // Call to Interrupt Procedure if Overflow Flag = 1
DFACategory[NN_int3] = INDIR_CALL; // Trap to Debugger
DFACategory[NN_iretw] = RETURN; // Interrupt Return
DFACategory[NN_iret] = RETURN; // Interrupt Return
DFACategory[NN_iretd] = RETURN; // Interrupt Return (use32)
DFACategory[NN_iretq] = RETURN; // Interrupt Return (use64)
DFACategory[NN_ja] = COND_BRANCH; // Jump if Above (CF=0 & ZF=0)
DFACategory[NN_jae] = COND_BRANCH; // Jump if Above or Equal (CF=0)
DFACategory[NN_jb] = COND_BRANCH; // Jump if Below (CF=1)
DFACategory[NN_jbe] = COND_BRANCH; // Jump if Below or Equal (CF=1 | ZF=1)
DFACategory[NN_jc] = COND_BRANCH; // Jump if Carry (CF=1)
DFACategory[NN_jcxz] = COND_BRANCH; // Jump if CX is 0
DFACategory[NN_jecxz] = COND_BRANCH; // Jump if ECX is 0
DFACategory[NN_jrcxz] = COND_BRANCH; // Jump if RCX is 0
DFACategory[NN_je] = COND_BRANCH; // Jump if Equal (ZF=1)
DFACategory[NN_jg] = COND_BRANCH; // Jump if Greater (ZF=0 & SF=OF)
DFACategory[NN_jge] = COND_BRANCH; // Jump if Greater or Equal (SF=OF)
DFACategory[NN_jl] = COND_BRANCH; // Jump if Less (SF!=OF)
DFACategory[NN_jle] = COND_BRANCH; // Jump if Less or Equal (ZF=1 | SF!=OF)
DFACategory[NN_jna] = COND_BRANCH; // Jump if Not Above (CF=1 | ZF=1)
DFACategory[NN_jnae] = COND_BRANCH; // Jump if Not Above or Equal (CF=1)
DFACategory[NN_jnb] = COND_BRANCH; // Jump if Not Below (CF=0)
DFACategory[NN_jnbe] = COND_BRANCH; // Jump if Not Below or Equal (CF=0 & ZF=0)
DFACategory[NN_jnc] = COND_BRANCH; // Jump if Not Carry (CF=0)
DFACategory[NN_jne] = COND_BRANCH; // Jump if Not Equal (ZF=0)
DFACategory[NN_jng] = COND_BRANCH; // Jump if Not Greater (ZF=1 | SF!=OF)
DFACategory[NN_jnge] = COND_BRANCH; // Jump if Not Greater or Equal (SF!=OF)
DFACategory[NN_jnl] = COND_BRANCH; // Jump if Not Less (SF=OF)
DFACategory[NN_jnle] = COND_BRANCH; // Jump if Not Less or Equal (ZF=0 & SF=OF)
DFACategory[NN_jno] = COND_BRANCH; // Jump if Not Overflow (OF=0)
DFACategory[NN_jnp] = COND_BRANCH; // Jump if Not Parity (PF=0)
DFACategory[NN_jns] = COND_BRANCH; // Jump if Not Sign (SF=0)
DFACategory[NN_jnz] = COND_BRANCH; // Jump if Not Zero (ZF=0)
DFACategory[NN_jo] = COND_BRANCH; // Jump if Overflow (OF=1)
DFACategory[NN_jp] = COND_BRANCH; // Jump if Parity (PF=1)
DFACategory[NN_jpe] = COND_BRANCH; // Jump if Parity Even (PF=1)
DFACategory[NN_jpo] = COND_BRANCH; // Jump if Parity Odd (PF=0)
DFACategory[NN_js] = COND_BRANCH; // Jump if Sign (SF=1)
DFACategory[NN_jz] = COND_BRANCH; // Jump if Zero (ZF=1)
DFACategory[NN_jmp] = JUMP; // Jump
DFACategory[NN_jmpfi] = INDIR_JUMP; // Indirect Far Jump
DFACategory[NN_jmpni] = INDIR_JUMP; // Indirect Near Jump
DFACategory[NN_jmpshort] = JUMP; // Jump Short (only in 64-bit mode)
DFACategory[NN_loopw] = COND_BRANCH; // Loop while ECX != 0
DFACategory[NN_loop] = COND_BRANCH; // Loop while CX != 0
DFACategory[NN_loopd] = COND_BRANCH; // Loop while ECX != 0
DFACategory[NN_loopq] = COND_BRANCH; // Loop while RCX != 0
DFACategory[NN_loopwe] = COND_BRANCH; // Loop while CX != 0 and ZF=1
DFACategory[NN_loope] = COND_BRANCH; // Loop while rCX != 0 and ZF=1
DFACategory[NN_loopde] = COND_BRANCH; // Loop while ECX != 0 and ZF=1
DFACategory[NN_loopqe] = COND_BRANCH; // Loop while RCX != 0 and ZF=1
DFACategory[NN_loopwne] = COND_BRANCH; // Loop while CX != 0 and ZF=0
DFACategory[NN_loopne] = COND_BRANCH; // Loop while rCX != 0 and ZF=0
DFACategory[NN_loopdne] = COND_BRANCH; // Loop while ECX != 0 and ZF=0
DFACategory[NN_loopqne] = COND_BRANCH; // Loop while RCX != 0 and ZF=0
DFACategory[NN_retn] = RETURN; // Return Near from Procedure
DFACategory[NN_retf] = RETURN; // Return Far from Procedure
//
// Pentium instructions
//
DFACategory[NN_rsm] = HALT; // Resume from System Management Mode
// Pentium II instructions
DFACategory[NN_sysenter] = CALL; // Fast Transition to System Call Entry Point
DFACategory[NN_sysexit] = CALL; // Fast Transition from System Call Entry Point
// AMD syscall/sysret instructions NOTE: not AMD, found in Intel manual
DFACategory[NN_syscall] = CALL; // Low latency system call
DFACategory[NN_sysret] = CALL; // Return from system call
// VMX instructions
DFACategory[NN_vmcall] = INDIR_CALL; // Call to VM Monitor
// Added with x86-64
// Geode LX 3DNow! extensions
// SSE2 pseudoinstructions
// SSSE4.1 instructions
// SSSE4.2 instructions
// AMD SSE4a instructions
// xsave/xrstor instructions
// Intel Safer Mode Extensions (SMX)
// AMD-V Virtualization ISA Extension
// VMX+ instructions
// Intel Atom instructions
// Intel AES instructions
// Carryless multiplication
// Returns modified by operand size prefixes
DFACategory[NN_retnw] = RETURN; // Return Near from Procedure (use16)
DFACategory[NN_retnd] = RETURN; // Return Near from Procedure (use32)
DFACategory[NN_retnq] = RETURN; // Return Near from Procedure (use64)
DFACategory[NN_retfw] = RETURN; // Return Far from Procedure (use16)
DFACategory[NN_retfd] = RETURN; // Return Far from Procedure (use32)
DFACategory[NN_retfq] = RETURN; // Return Far from Procedure (use64)
// RDRAND support
// new GPR instructions
// new AVX instructions
// Transactional Synchronization Extensions
// Virtual PC synthetic instructions
return;
} // end InitDFACategory()
// Initialize the SMPDefsFlags[] array to define how we emit
// optimizing annotations.
void InitSMPDefsFlags(void) {
// Default value is true. Many instructions set the flags.
(void) memset(SMPDefsFlags, true, sizeof(SMPDefsFlags));
SMPDefsFlags[NN_null] = false; // Unknown Operation
SMPDefsFlags[NN_bound] = false; // Check Array Index Against Bounds
SMPDefsFlags[NN_call] = false; // Call Procedure
SMPDefsFlags[NN_callfi] = false; // Indirect Call Far Procedure
SMPDefsFlags[NN_callni] = false; // Indirect Call Near Procedure
SMPDefsFlags[NN_cbw] = false; // AL -> AX (with sign)
SMPDefsFlags[NN_cwde] = false; // AX -> EAX (with sign)
SMPDefsFlags[NN_cdqe] = false; // EAX -> RAX (with sign)
SMPDefsFlags[NN_clts] = false; // Clear Task-Switched Flag in CR0
SMPDefsFlags[NN_cwd] = false; // AX -> DX:AX (with sign)
SMPDefsFlags[NN_cdq] = false; // EAX -> EDX:EAX (with sign)
SMPDefsFlags[NN_cqo] = false; // RAX -> RDX:RAX (with sign)
SMPDefsFlags[NN_enterw] = false; // Make Stack Frame for Procedure Parameters
SMPDefsFlags[NN_enter] = false; // Make Stack Frame for Procedure Parameters
SMPDefsFlags[NN_enterd] = false; // Make Stack Frame for Procedure Parameters
SMPDefsFlags[NN_enterq] = false; // Make Stack Frame for Procedure Parameters
SMPDefsFlags[NN_hlt] = false; // Halt
SMPDefsFlags[NN_in] = false; // Input from Port
SMPDefsFlags[NN_ins] = false; // Input Byte(s) from Port to String
SMPDefsFlags[NN_iretw] = false; // Interrupt Return
SMPDefsFlags[NN_iret] = false; // Interrupt Return
SMPDefsFlags[NN_iretd] = false; // Interrupt Return (use32)
SMPDefsFlags[NN_iretq] = false; // Interrupt Return (use64)
SMPDefsFlags[NN_ja] = false; // Jump if Above (CF=0 & ZF=0)
SMPDefsFlags[NN_jae] = false; // Jump if Above or Equal (CF=0)
SMPDefsFlags[NN_jb] = false; // Jump if Below (CF=1)
SMPDefsFlags[NN_jbe] = false; // Jump if Below or Equal (CF=1 | ZF=1)
SMPDefsFlags[NN_jc] = false; // Jump if Carry (CF=1)
SMPDefsFlags[NN_jcxz] = false; // Jump if CX is 0
SMPDefsFlags[NN_jecxz] = false; // Jump if ECX is 0
SMPDefsFlags[NN_jrcxz] = false; // Jump if RCX is 0
SMPDefsFlags[NN_je] = false; // Jump if Equal (ZF=1)
SMPDefsFlags[NN_jg] = false; // Jump if Greater (ZF=0 & SF=OF)
SMPDefsFlags[NN_jge] = false; // Jump if Greater or Equal (SF=OF)
SMPDefsFlags[NN_jl] = false; // Jump if Less (SF!=OF)
SMPDefsFlags[NN_jle] = false; // Jump if Less or Equal (ZF=1 | SF!=OF)
SMPDefsFlags[NN_jna] = false; // Jump if Not Above (CF=1 | ZF=1)
SMPDefsFlags[NN_jnae] = false; // Jump if Not Above or Equal (CF=1)
SMPDefsFlags[NN_jnb] = false; // Jump if Not Below (CF=0)
SMPDefsFlags[NN_jnbe] = false; // Jump if Not Below or Equal (CF=0 & ZF=0)
SMPDefsFlags[NN_jnc] = false; // Jump if Not Carry (CF=0)
SMPDefsFlags[NN_jne] = false; // Jump if Not Equal (ZF=0)
SMPDefsFlags[NN_jng] = false; // Jump if Not Greater (ZF=1 | SF!=OF)
SMPDefsFlags[NN_jnge] = false; // Jump if Not Greater or Equal (SF!=OF)
SMPDefsFlags[NN_jnl] = false; // Jump if Not Less (SF=OF)
SMPDefsFlags[NN_jnle] = false; // Jump if Not Less or Equal (ZF=0 & SF=OF)
SMPDefsFlags[NN_jno] = false; // Jump if Not Overflow (OF=0)
SMPDefsFlags[NN_jnp] = false; // Jump if Not Parity (PF=0)
SMPDefsFlags[NN_jns] = false; // Jump if Not Sign (SF=0)
SMPDefsFlags[NN_jnz] = false; // Jump if Not Zero (ZF=0)
SMPDefsFlags[NN_jo] = false; // Jump if Overflow (OF=1)
SMPDefsFlags[NN_jp] = false; // Jump if Parity (PF=1)
SMPDefsFlags[NN_jpe] = false; // Jump if Parity Even (PF=1)
SMPDefsFlags[NN_jpo] = false; // Jump if Parity Odd (PF=0)
SMPDefsFlags[NN_js] = false; // Jump if Sign (SF=1)
SMPDefsFlags[NN_jz] = false; // Jump if Zero (ZF=1)
SMPDefsFlags[NN_jmp] = false; // Jump
SMPDefsFlags[NN_jmpfi] = false; // Indirect Far Jump
SMPDefsFlags[NN_jmpni] = false; // Indirect Near Jump
SMPDefsFlags[NN_jmpshort] = false; // Jump Short (not used)
SMPDefsFlags[NN_lahf] = false; // Load Flags into AH Register
SMPDefsFlags[NN_lea] = false; // Load Effective Address
SMPDefsFlags[NN_leavew] = false; // High Level Procedure Exit
SMPDefsFlags[NN_leave] = false; // High Level Procedure Exit
SMPDefsFlags[NN_leaved] = false; // High Level Procedure Exit
SMPDefsFlags[NN_leaveq] = false; // High Level Procedure Exit
SMPDefsFlags[NN_lgdt] = false; // Load Global Descriptor Table Register
SMPDefsFlags[NN_lidt] = false; // Load Interrupt Descriptor Table Register
SMPDefsFlags[NN_lgs] = false; // Load Full Pointer to GS:xx
SMPDefsFlags[NN_lss] = false; // Load Full Pointer to SS:xx
SMPDefsFlags[NN_lds] = false; // Load Full Pointer to DS:xx
SMPDefsFlags[NN_les] = false; // Load Full Pointer to ES:xx
SMPDefsFlags[NN_lfs] = false; // Load Full Pointer to FS:xx
SMPDefsFlags[NN_loopw] = false; // Loop while ECX != 0
SMPDefsFlags[NN_loop] = false; // Loop while ECX != 0
SMPDefsFlags[NN_loopwe] = false; // Loop while CX != 0 and ZF=1
SMPDefsFlags[NN_loope] = false; // Loop while rCX != 0 and ZF=1
SMPDefsFlags[NN_loopde] = false; // Loop while ECX != 0 and ZF=1
SMPDefsFlags[NN_loopqe] = false; // Loop while RCX != 0 and ZF=1
SMPDefsFlags[NN_loopwne] = false; // Loop while CX != 0 and ZF=0
SMPDefsFlags[NN_loopne] = false; // Loop while rCX != 0 and ZF=0
SMPDefsFlags[NN_loopdne] = false; // Loop while ECX != 0 and ZF=0
SMPDefsFlags[NN_loopqne] = false; // Loop while RCX != 0 and ZF=0
SMPDefsFlags[NN_ltr] = false; // Load Task Register
SMPDefsFlags[NN_mov] = false; // Move Data
SMPDefsFlags[NN_movsp] = true; // Move to/from Special Registers
SMPDefsFlags[NN_movs] = false; // Move Byte(s) from String to String
SMPDefsFlags[NN_movsx] = false; // Move with Sign-Extend
SMPDefsFlags[NN_movzx] = false; // Move with Zero-Extend
SMPDefsFlags[NN_nop] = false; // No Operation
SMPDefsFlags[NN_not] = false; // One's Complement Negation
SMPDefsFlags[NN_out] = false; // Output to Port
SMPDefsFlags[NN_outs] = false; // Output Byte(s) to Port
SMPDefsFlags[NN_pop] = false; // Pop a word from the Stack
SMPDefsFlags[NN_popaw] = false; // Pop all General Registers
SMPDefsFlags[NN_popa] = false; // Pop all General Registers
SMPDefsFlags[NN_popad] = false; // Pop all General Registers (use32)
SMPDefsFlags[NN_popaq] = false; // Pop all General Registers (use64)
SMPDefsFlags[NN_push] = false; // Push Operand onto the Stack
SMPDefsFlags[NN_pushaw] = false; // Push all General Registers
SMPDefsFlags[NN_pusha] = false; // Push all General Registers
SMPDefsFlags[NN_pushad] = false; // Push all General Registers (use32)
SMPDefsFlags[NN_pushaq] = false; // Push all General Registers (use64)
SMPDefsFlags[NN_pushfw] = false; // Push Flags Register onto the Stack
SMPDefsFlags[NN_pushf] = false; // Push Flags Register onto the Stack
SMPDefsFlags[NN_pushfd] = false; // Push Flags Register onto the Stack (use32)
SMPDefsFlags[NN_pushfq] = false; // Push Flags Register onto the Stack (use64)
SMPDefsFlags[NN_rep] = false; // Repeat String Operation
SMPDefsFlags[NN_repe] = false; // Repeat String Operation while ZF=1
SMPDefsFlags[NN_repne] = false; // Repeat String Operation while ZF=0
SMPDefsFlags[NN_retn] = false; // Return Near from Procedure
SMPDefsFlags[NN_retf] = false; // Return Far from Procedure
SMPDefsFlags[NN_sahf] = true; // Store AH into flags
SMPDefsFlags[NN_shl] = true; // Shift Logical Left
SMPDefsFlags[NN_shr] = true; // Shift Logical Right
SMPDefsFlags[NN_seta] = false; // Set Byte if Above (CF=0 & ZF=0)
SMPDefsFlags[NN_setae] = false; // Set Byte if Above or Equal (CF=0)
SMPDefsFlags[NN_setb] = false; // Set Byte if Below (CF=1)
SMPDefsFlags[NN_setbe] = false; // Set Byte if Below or Equal (CF=1 | ZF=1)
SMPDefsFlags[NN_setc] = false; // Set Byte if Carry (CF=1)
SMPDefsFlags[NN_sete] = false; // Set Byte if Equal (ZF=1)
SMPDefsFlags[NN_setg] = false; // Set Byte if Greater (ZF=0 & SF=OF)
SMPDefsFlags[NN_setge] = false; // Set Byte if Greater or Equal (SF=OF)
SMPDefsFlags[NN_setl] = false; // Set Byte if Less (SF!=OF)
SMPDefsFlags[NN_setle] = false; // Set Byte if Less or Equal (ZF=1 | SF!=OF)
SMPDefsFlags[NN_setna] = false; // Set Byte if Not Above (CF=1 | ZF=1)
SMPDefsFlags[NN_setnae] = false; // Set Byte if Not Above or Equal (CF=1)
SMPDefsFlags[NN_setnb] = false; // Set Byte if Not Below (CF=0)
SMPDefsFlags[NN_setnbe] = false; // Set Byte if Not Below or Equal (CF=0 & ZF=0)
SMPDefsFlags[NN_setnc] = false; // Set Byte if Not Carry (CF=0)
SMPDefsFlags[NN_setne] = false; // Set Byte if Not Equal (ZF=0)
SMPDefsFlags[NN_setng] = false; // Set Byte if Not Greater (ZF=1 | SF!=OF)
SMPDefsFlags[NN_setnge] = false; // Set Byte if Not Greater or Equal (SF!=OF)
SMPDefsFlags[NN_setnl] = false; // Set Byte if Not Less (SF=OF)
SMPDefsFlags[NN_setnle] = false; // Set Byte if Not Less or Equal (ZF=0 & SF=OF)
SMPDefsFlags[NN_setno] = false; // Set Byte if Not Overflow (OF=0)
SMPDefsFlags[NN_setnp] = false; // Set Byte if Not Parity (PF=0)
SMPDefsFlags[NN_setns] = false; // Set Byte if Not Sign (SF=0)
SMPDefsFlags[NN_setnz] = false; // Set Byte if Not Zero (ZF=0)
SMPDefsFlags[NN_seto] = false; // Set Byte if Overflow (OF=1)
SMPDefsFlags[NN_setp] = false; // Set Byte if Parity (PF=1)
SMPDefsFlags[NN_setpe] = false; // Set Byte if Parity Even (PF=1)
SMPDefsFlags[NN_setpo] = false; // Set Byte if Parity Odd (PF=0)
SMPDefsFlags[NN_sets] = false; // Set Byte if Sign (SF=1)
SMPDefsFlags[NN_setz] = false; // Set Byte if Zero (ZF=1)
SMPDefsFlags[NN_sgdt] = false; // Store Global Descriptor Table Register
SMPDefsFlags[NN_sidt] = false; // Store Interrupt Descriptor Table Register
SMPDefsFlags[NN_sldt] = false; // Store Local Descriptor Table Register
SMPDefsFlags[NN_str] = false; // Store Task Register
SMPDefsFlags[NN_wait] = false; // Wait until BUSY# Pin is Inactive (HIGH)
SMPDefsFlags[NN_xchg] = false; // Exchange Register/Memory with Register
SMPDefsFlags[NN_xlat] = false; // Table Lookup Translation
//
// 486 instructions
//
SMPDefsFlags[NN_bswap] = false; // Swap bytes in register
SMPDefsFlags[NN_invd] = false; // Invalidate Data Cache
SMPDefsFlags[NN_wbinvd] = false; // Invalidate Data Cache (write changes)
SMPDefsFlags[NN_invlpg] = false; // Invalidate TLB entry
//
// Pentium instructions
//
SMPDefsFlags[NN_rdmsr] = false; // Read Machine Status Register
SMPDefsFlags[NN_wrmsr] = false; // Write Machine Status Register
SMPDefsFlags[NN_cpuid] = false; // Get CPU ID
SMPDefsFlags[NN_rdtsc] = false; // Read Time Stamp Counter
//
// Pentium Pro instructions
//
SMPDefsFlags[NN_cmova] = false; // Move if Above (CF=0 & ZF=0)
SMPDefsFlags[NN_cmovb] = false; // Move if Below (CF=1)
SMPDefsFlags[NN_cmovbe] = false; // Move if Below or Equal (CF=1 | ZF=1)
SMPDefsFlags[NN_cmovg] = false; // Move if Greater (ZF=0 & SF=OF)
SMPDefsFlags[NN_cmovge] = false; // Move if Greater or Equal (SF=OF)
SMPDefsFlags[NN_cmovl] = false; // Move if Less (SF!=OF)
SMPDefsFlags[NN_cmovle] = false; // Move if Less or Equal (ZF=1 | SF!=OF)
SMPDefsFlags[NN_cmovnb] = false; // Move if Not Below (CF=0)
SMPDefsFlags[NN_cmovno] = false; // Move if Not Overflow (OF=0)
SMPDefsFlags[NN_cmovnp] = false; // Move if Not Parity (PF=0)
SMPDefsFlags[NN_cmovns] = false; // Move if Not Sign (SF=0)
SMPDefsFlags[NN_cmovnz] = false; // Move if Not Zero (ZF=0)
SMPDefsFlags[NN_cmovo] = false; // Move if Overflow (OF=1)
SMPDefsFlags[NN_cmovp] = false; // Move if Parity (PF=1)
SMPDefsFlags[NN_cmovs] = false; // Move if Sign (SF=1)
SMPDefsFlags[NN_cmovz] = false; // Move if Zero (ZF=1)
SMPDefsFlags[NN_fcmovb] = false; // Floating Move if Below
SMPDefsFlags[NN_fcmove] = false; // Floating Move if Equal
SMPDefsFlags[NN_fcmovbe] = false; // Floating Move if Below or Equal
SMPDefsFlags[NN_fcmovu] = false; // Floating Move if Unordered
SMPDefsFlags[NN_fcmovnb] = false; // Floating Move if Not Below
SMPDefsFlags[NN_fcmovne] = false; // Floating Move if Not Equal
SMPDefsFlags[NN_fcmovnbe] = false; // Floating Move if Not Below or Equal
SMPDefsFlags[NN_fcmovnu] = false; // Floating Move if Not Unordered
SMPDefsFlags[NN_rdpmc] = false; // Read Performance Monitor Counter
//
// FPP instructions
//
SMPDefsFlags[NN_fld] = false; // Load Real
SMPDefsFlags[NN_fst] = false; // Store Real
SMPDefsFlags[NN_fstp] = false; // Store Real and Pop
SMPDefsFlags[NN_fxch] = false; // Exchange Registers
SMPDefsFlags[NN_fild] = false; // Load Integer
SMPDefsFlags[NN_fist] = false; // Store Integer
SMPDefsFlags[NN_fistp] = false; // Store Integer and Pop
SMPDefsFlags[NN_fbld] = false; // Load BCD
SMPDefsFlags[NN_fbstp] = false; // Store BCD and Pop
SMPDefsFlags[NN_fadd] = false; // Add Real
SMPDefsFlags[NN_faddp] = false; // Add Real and Pop
SMPDefsFlags[NN_fiadd] = false; // Add Integer
SMPDefsFlags[NN_fsub] = false; // Subtract Real
SMPDefsFlags[NN_fsubp] = false; // Subtract Real and Pop
SMPDefsFlags[NN_fisub] = false; // Subtract Integer
SMPDefsFlags[NN_fsubr] = false; // Subtract Real Reversed
SMPDefsFlags[NN_fsubrp] = false; // Subtract Real Reversed and Pop
SMPDefsFlags[NN_fisubr] = false; // Subtract Integer Reversed
SMPDefsFlags[NN_fmul] = false; // Multiply Real
SMPDefsFlags[NN_fmulp] = false; // Multiply Real and Pop
SMPDefsFlags[NN_fimul] = false; // Multiply Integer
SMPDefsFlags[NN_fdiv] = false; // Divide Real
SMPDefsFlags[NN_fdivp] = false; // Divide Real and Pop
SMPDefsFlags[NN_fidiv] = false; // Divide Integer
SMPDefsFlags[NN_fdivr] = false; // Divide Real Reversed
SMPDefsFlags[NN_fdivrp] = false; // Divide Real Reversed and Pop
SMPDefsFlags[NN_fidivr] = false; // Divide Integer Reversed
SMPDefsFlags[NN_fsqrt] = false; // Square Root
SMPDefsFlags[NN_fscale] = false; // Scale: st(0) <- st(0) * 2^st(1)
SMPDefsFlags[NN_fprem] = false; // Partial Remainder
SMPDefsFlags[NN_frndint] = false; // Round to Integer
SMPDefsFlags[NN_fxtract] = false; // Extract exponent and significand
SMPDefsFlags[NN_fabs] = false; // Absolute value
SMPDefsFlags[NN_fchs] = false; // Change Sign
SMPDefsFlags[NN_ficom] = false; // Compare Integer
SMPDefsFlags[NN_ficomp] = false; // Compare Integer and Pop
SMPDefsFlags[NN_ftst] = false; // Test
SMPDefsFlags[NN_fxam] = false; // Examine
SMPDefsFlags[NN_fptan] = false; // Partial tangent
SMPDefsFlags[NN_fpatan] = false; // Partial arctangent
SMPDefsFlags[NN_f2xm1] = false; // 2^x - 1
SMPDefsFlags[NN_fyl2x] = false; // Y * lg2(X)
SMPDefsFlags[NN_fyl2xp1] = false; // Y * lg2(X+1)
SMPDefsFlags[NN_fldz] = false; // Load +0.0
SMPDefsFlags[NN_fld1] = false; // Load +1.0
SMPDefsFlags[NN_fldpi] = false; // Load PI=3.14...
SMPDefsFlags[NN_fldl2t] = false; // Load lg2(10)
SMPDefsFlags[NN_fldl2e] = false; // Load lg2(e)
SMPDefsFlags[NN_fldlg2] = false; // Load lg10(2)
SMPDefsFlags[NN_fldln2] = false; // Load ln(2)
SMPDefsFlags[NN_finit] = false; // Initialize Processor
SMPDefsFlags[NN_fninit] = false; // Initialize Processor (no wait)
SMPDefsFlags[NN_fsetpm] = false; // Set Protected Mode
SMPDefsFlags[NN_fldcw] = false; // Load Control Word
SMPDefsFlags[NN_fstcw] = false; // Store Control Word
SMPDefsFlags[NN_fnstcw] = false; // Store Control Word (no wait)
SMPDefsFlags[NN_fstsw] = false; // Store Status Word to memory or AX
SMPDefsFlags[NN_fnstsw] = false; // Store Status Word (no wait) to memory or AX
SMPDefsFlags[NN_fclex] = false; // Clear Exceptions
SMPDefsFlags[NN_fnclex] = false; // Clear Exceptions (no wait)
SMPDefsFlags[NN_fstenv] = false; // Store Environment
SMPDefsFlags[NN_fnstenv] = false; // Store Environment (no wait)
SMPDefsFlags[NN_fldenv] = false; // Load Environment
SMPDefsFlags[NN_fsave] = false; // Save State
SMPDefsFlags[NN_fnsave] = false; // Save State (no wait)
SMPDefsFlags[NN_frstor] = false; // Restore State
SMPDefsFlags[NN_fincstp] = false; // Increment Stack Pointer
SMPDefsFlags[NN_fdecstp] = false; // Decrement Stack Pointer
SMPDefsFlags[NN_ffree] = false; // Free Register
SMPDefsFlags[NN_fnop] = false; // No Operation
SMPDefsFlags[NN_feni] = false; // (8087 only)
SMPDefsFlags[NN_fneni] = false; // (no wait) (8087 only)
SMPDefsFlags[NN_fdisi] = false; // (8087 only)
SMPDefsFlags[NN_fndisi] = false; // (no wait) (8087 only)
//
// 80387 instructions
//
SMPDefsFlags[NN_fprem1] = false; // Partial Remainder ( < half )
SMPDefsFlags[NN_fsincos] = false; // t<-cos(st); st<-sin(st); push t
SMPDefsFlags[NN_fsin] = false; // Sine
SMPDefsFlags[NN_fcos] = false; // Cosine
SMPDefsFlags[NN_fucom] = false; // Compare Unordered Real
SMPDefsFlags[NN_fucomp] = false; // Compare Unordered Real and Pop
SMPDefsFlags[NN_fucompp] = false; // Compare Unordered Real and Pop Twice
//
// Instructions added 28.02.96
//
SMPDefsFlags[NN_svdc] = false; // Save Register and Descriptor
SMPDefsFlags[NN_rsdc] = false; // Restore Register and Descriptor
SMPDefsFlags[NN_svldt] = false; // Save LDTR and Descriptor
SMPDefsFlags[NN_rsldt] = false; // Restore LDTR and Descriptor
SMPDefsFlags[NN_svts] = false; // Save TR and Descriptor
SMPDefsFlags[NN_rsts] = false; // Restore TR and Descriptor
SMPDefsFlags[NN_icebp] = false; // ICE Break Point
//
// MMX instructions
//
SMPDefsFlags[NN_emms] = false; // Empty MMX state
SMPDefsFlags[NN_movd] = false; // Move 32 bits
SMPDefsFlags[NN_movq] = false; // Move 64 bits
SMPDefsFlags[NN_packsswb] = false; // Pack with Signed Saturation (Word->Byte)
SMPDefsFlags[NN_packssdw] = false; // Pack with Signed Saturation (Dword->Word)
SMPDefsFlags[NN_packuswb] = false; // Pack with Unsigned Saturation (Word->Byte)
SMPDefsFlags[NN_paddb] = false; // Packed Add Byte
SMPDefsFlags[NN_paddw] = false; // Packed Add Word
SMPDefsFlags[NN_paddd] = false; // Packed Add Dword
SMPDefsFlags[NN_paddsb] = false; // Packed Add with Saturation (Byte)
SMPDefsFlags[NN_paddsw] = false; // Packed Add with Saturation (Word)
SMPDefsFlags[NN_paddusb] = false; // Packed Add Unsigned with Saturation (Byte)
SMPDefsFlags[NN_paddusw] = false; // Packed Add Unsigned with Saturation (Word)
SMPDefsFlags[NN_pand] = false; // Bitwise Logical And
SMPDefsFlags[NN_pandn] = false; // Bitwise Logical And Not
SMPDefsFlags[NN_pcmpeqb] = false; // Packed Compare for Equal (Byte)
SMPDefsFlags[NN_pcmpeqw] = false; // Packed Compare for Equal (Word)
SMPDefsFlags[NN_pcmpeqd] = false; // Packed Compare for Equal (Dword)
SMPDefsFlags[NN_pcmpgtb] = false; // Packed Compare for Greater Than (Byte)
SMPDefsFlags[NN_pcmpgtw] = false; // Packed Compare for Greater Than (Word)
SMPDefsFlags[NN_pcmpgtd] = false; // Packed Compare for Greater Than (Dword)
SMPDefsFlags[NN_pmaddwd] = false; // Packed Multiply and Add
SMPDefsFlags[NN_pmulhw] = false; // Packed Multiply High
SMPDefsFlags[NN_pmullw] = false; // Packed Multiply Low
SMPDefsFlags[NN_por] = false; // Bitwise Logical Or
SMPDefsFlags[NN_psllw] = false; // Packed Shift Left Logical (Word)
SMPDefsFlags[NN_pslld] = false; // Packed Shift Left Logical (Dword)
SMPDefsFlags[NN_psllq] = false; // Packed Shift Left Logical (Qword)
SMPDefsFlags[NN_psraw] = false; // Packed Shift Right Arithmetic (Word)
SMPDefsFlags[NN_psrad] = false; // Packed Shift Right Arithmetic (Dword)
SMPDefsFlags[NN_psrlw] = false; // Packed Shift Right Logical (Word)
SMPDefsFlags[NN_psrld] = false; // Packed Shift Right Logical (Dword)
SMPDefsFlags[NN_psrlq] = false; // Packed Shift Right Logical (Qword)
SMPDefsFlags[NN_psubb] = false; // Packed Subtract Byte
SMPDefsFlags[NN_psubw] = false; // Packed Subtract Word
SMPDefsFlags[NN_psubd] = false; // Packed Subtract Dword
SMPDefsFlags[NN_psubsb] = false; // Packed Subtract with Saturation (Byte)
SMPDefsFlags[NN_psubsw] = false; // Packed Subtract with Saturation (Word)
SMPDefsFlags[NN_psubusb] = false; // Packed Subtract Unsigned with Saturation (Byte)
SMPDefsFlags[NN_psubusw] = false; // Packed Subtract Unsigned with Saturation (Word)
SMPDefsFlags[NN_punpckhbw] = false; // Unpack High Packed Data (Byte->Word)
SMPDefsFlags[NN_punpckhwd] = false; // Unpack High Packed Data (Word->Dword)
SMPDefsFlags[NN_punpckhdq] = false; // Unpack High Packed Data (Dword->Qword)
SMPDefsFlags[NN_punpcklbw] = false; // Unpack Low Packed Data (Byte->Word)
SMPDefsFlags[NN_punpcklwd] = false; // Unpack Low Packed Data (Word->Dword)
SMPDefsFlags[NN_punpckldq] = false; // Unpack Low Packed Data (Dword->Qword)
SMPDefsFlags[NN_pxor] = false; // Bitwise Logical Exclusive Or
//
// Undocumented Deschutes processor instructions
//
SMPDefsFlags[NN_fxsave] = false; // Fast save FP context
SMPDefsFlags[NN_fxrstor] = false; // Fast restore FP context
// Pentium II instructions
SMPDefsFlags[NN_sysexit] = false; // Fast Transition from System Call Entry Point
// 3DNow! instructions
SMPDefsFlags[NN_pavgusb] = false; // Packed 8-bit Unsigned Integer Averaging
SMPDefsFlags[NN_pfadd] = false; // Packed Floating-Point Addition
SMPDefsFlags[NN_pfsub] = false; // Packed Floating-Point Subtraction
SMPDefsFlags[NN_pfsubr] = false; // Packed Floating-Point Reverse Subtraction
SMPDefsFlags[NN_pfacc] = false; // Packed Floating-Point Accumulate
SMPDefsFlags[NN_pfcmpge] = false; // Packed Floating-Point Comparison, Greater or Equal
SMPDefsFlags[NN_pfcmpgt] = false; // Packed Floating-Point Comparison, Greater
SMPDefsFlags[NN_pfcmpeq] = false; // Packed Floating-Point Comparison, Equal
SMPDefsFlags[NN_pfmin] = false; // Packed Floating-Point Minimum
SMPDefsFlags[NN_pfmax] = false; // Packed Floating-Point Maximum
SMPDefsFlags[NN_pi2fd] = false; // Packed 32-bit Integer to Floating-Point
SMPDefsFlags[NN_pf2id] = false; // Packed Floating-Point to 32-bit Integer
SMPDefsFlags[NN_pfrcp] = false; // Packed Floating-Point Reciprocal Approximation
SMPDefsFlags[NN_pfrsqrt] = false; // Packed Floating-Point Reciprocal Square Root Approximation
SMPDefsFlags[NN_pfmul] = false; // Packed Floating-Point Multiplication
SMPDefsFlags[NN_pfrcpit1] = false; // Packed Floating-Point Reciprocal First Iteration Step
SMPDefsFlags[NN_pfrsqit1] = false; // Packed Floating-Point Reciprocal Square Root First Iteration Step
SMPDefsFlags[NN_pfrcpit2] = false; // Packed Floating-Point Reciprocal Second Iteration Step
SMPDefsFlags[NN_pmulhrw] = false; // Packed Floating-Point 16-bit Integer Multiply with rounding
SMPDefsFlags[NN_femms] = false; // Faster entry/exit of the MMX or floating-point state
SMPDefsFlags[NN_prefetch] = false; // Prefetch at least a 32-byte line into L1 data cache
SMPDefsFlags[NN_prefetchw] = false; // Prefetch processor cache line into L1 data cache (mark as modified)
// Pentium III instructions
SMPDefsFlags[NN_addps] = false; // Packed Single-FP Add
SMPDefsFlags[NN_addss] = false; // Scalar Single-FP Add
SMPDefsFlags[NN_andnps] = false; // Bitwise Logical And Not for Single-FP
SMPDefsFlags[NN_andps] = false; // Bitwise Logical And for Single-FP
SMPDefsFlags[NN_cmpps] = false; // Packed Single-FP Compare
SMPDefsFlags[NN_cmpss] = false; // Scalar Single-FP Compare
SMPDefsFlags[NN_cvtpi2ps] = false; // Packed signed INT32 to Packed Single-FP conversion
SMPDefsFlags[NN_cvtps2pi] = false; // Packed Single-FP to Packed INT32 conversion
SMPDefsFlags[NN_cvtsi2ss] = false; // Scalar signed INT32 to Single-FP conversion
SMPDefsFlags[NN_cvtss2si] = false; // Scalar Single-FP to signed INT32 conversion
SMPDefsFlags[NN_cvttps2pi] = false; // Packed Single-FP to Packed INT32 conversion (truncate)
SMPDefsFlags[NN_cvttss2si] = false; // Scalar Single-FP to signed INT32 conversion (truncate)
SMPDefsFlags[NN_divps] = false; // Packed Single-FP Divide
SMPDefsFlags[NN_divss] = false; // Scalar Single-FP Divide
SMPDefsFlags[NN_ldmxcsr] = false; // Load Streaming SIMD Extensions Technology Control/Status Register
SMPDefsFlags[NN_maxps] = false; // Packed Single-FP Maximum
SMPDefsFlags[NN_maxss] = false; // Scalar Single-FP Maximum
SMPDefsFlags[NN_minps] = false; // Packed Single-FP Minimum
SMPDefsFlags[NN_minss] = false; // Scalar Single-FP Minimum
SMPDefsFlags[NN_movaps] = false; // Move Aligned Four Packed Single-FP
SMPDefsFlags[NN_movhlps] = false; // Move High to Low Packed Single-FP
SMPDefsFlags[NN_movhps] = false; // Move High Packed Single-FP
SMPDefsFlags[NN_movlhps] = false; // Move Low to High Packed Single-FP
SMPDefsFlags[NN_movlps] = false; // Move Low Packed Single-FP
SMPDefsFlags[NN_movmskps] = false; // Move Mask to Register
SMPDefsFlags[NN_movss] = false; // Move Scalar Single-FP
SMPDefsFlags[NN_movups] = false; // Move Unaligned Four Packed Single-FP
SMPDefsFlags[NN_mulps] = false; // Packed Single-FP Multiply
SMPDefsFlags[NN_mulss] = false; // Scalar Single-FP Multiply
SMPDefsFlags[NN_orps] = false; // Bitwise Logical OR for Single-FP Data
SMPDefsFlags[NN_rcpps] = false; // Packed Single-FP Reciprocal
SMPDefsFlags[NN_rcpss] = false; // Scalar Single-FP Reciprocal
SMPDefsFlags[NN_rsqrtps] = false; // Packed Single-FP Square Root Reciprocal
SMPDefsFlags[NN_rsqrtss] = false; // Scalar Single-FP Square Root Reciprocal
SMPDefsFlags[NN_shufps] = false; // Shuffle Single-FP
SMPDefsFlags[NN_sqrtps] = false; // Packed Single-FP Square Root
SMPDefsFlags[NN_sqrtss] = false; // Scalar Single-FP Square Root
SMPDefsFlags[NN_stmxcsr] = false; // Store Streaming SIMD Extensions Technology Control/Status Register
SMPDefsFlags[NN_subps] = false; // Packed Single-FP Subtract
SMPDefsFlags[NN_subss] = false; // Scalar Single-FP Subtract
SMPDefsFlags[NN_unpckhps] = false; // Unpack High Packed Single-FP Data
SMPDefsFlags[NN_unpcklps] = false; // Unpack Low Packed Single-FP Data
SMPDefsFlags[NN_xorps] = false; // Bitwise Logical XOR for Single-FP Data
SMPDefsFlags[NN_pavgb] = false; // Packed Average (Byte)
SMPDefsFlags[NN_pavgw] = false; // Packed Average (Word)
SMPDefsFlags[NN_pextrw] = false; // Extract Word
SMPDefsFlags[NN_pinsrw] = false; // Insert Word
SMPDefsFlags[NN_pmaxsw] = false; // Packed Signed Integer Word Maximum
SMPDefsFlags[NN_pmaxub] = false; // Packed Unsigned Integer Byte Maximum
SMPDefsFlags[NN_pminsw] = false; // Packed Signed Integer Word Minimum
SMPDefsFlags[NN_pminub] = false; // Packed Unsigned Integer Byte Minimum
SMPDefsFlags[NN_pmovmskb] = false; // Move Byte Mask to Integer
SMPDefsFlags[NN_pmulhuw] = false; // Packed Multiply High Unsigned
SMPDefsFlags[NN_psadbw] = false; // Packed Sum of Absolute Differences
SMPDefsFlags[NN_pshufw] = false; // Packed Shuffle Word
SMPDefsFlags[NN_maskmovq] = false; // Byte Mask write
SMPDefsFlags[NN_movntps] = false; // Move Aligned Four Packed Single-FP Non Temporal
SMPDefsFlags[NN_movntq] = false; // Move 64 Bits Non Temporal
SMPDefsFlags[NN_prefetcht0] = false; // Prefetch to all cache levels
SMPDefsFlags[NN_prefetcht1] = false; // Prefetch to all cache levels
SMPDefsFlags[NN_prefetcht2] = false; // Prefetch to L2 cache
SMPDefsFlags[NN_prefetchnta] = false; // Prefetch to L1 cache
SMPDefsFlags[NN_sfence] = false; // Store Fence
// Pentium III Pseudo instructions
SMPDefsFlags[NN_cmpeqps] = false; // Packed Single-FP Compare EQ
SMPDefsFlags[NN_cmpltps] = false; // Packed Single-FP Compare LT
SMPDefsFlags[NN_cmpleps] = false; // Packed Single-FP Compare LE
SMPDefsFlags[NN_cmpunordps] = false; // Packed Single-FP Compare UNORD
SMPDefsFlags[NN_cmpneqps] = false; // Packed Single-FP Compare NOT EQ
SMPDefsFlags[NN_cmpnltps] = false; // Packed Single-FP Compare NOT LT
SMPDefsFlags[NN_cmpnleps] = false; // Packed Single-FP Compare NOT LE
SMPDefsFlags[NN_cmpordps] = false; // Packed Single-FP Compare ORDERED
SMPDefsFlags[NN_cmpeqss] = false; // Scalar Single-FP Compare EQ
SMPDefsFlags[NN_cmpltss] = false; // Scalar Single-FP Compare LT
SMPDefsFlags[NN_cmpless] = false; // Scalar Single-FP Compare LE
SMPDefsFlags[NN_cmpunordss] = false; // Scalar Single-FP Compare UNORD
SMPDefsFlags[NN_cmpneqss] = false; // Scalar Single-FP Compare NOT EQ
SMPDefsFlags[NN_cmpnltss] = false; // Scalar Single-FP Compare NOT LT
SMPDefsFlags[NN_cmpnless] = false; // Scalar Single-FP Compare NOT LE
SMPDefsFlags[NN_cmpordss] = false; // Scalar Single-FP Compare ORDERED
// AMD K7 instructions
// Revisit AMD if we port to it.
SMPDefsFlags[NN_pf2iw] = false; // Packed Floating-Point to Integer with Sign Extend
SMPDefsFlags[NN_pfnacc] = false; // Packed Floating-Point Negative Accumulate
SMPDefsFlags[NN_pfpnacc] = false; // Packed Floating-Point Mixed Positive-Negative Accumulate
SMPDefsFlags[NN_pi2fw] = false; // Packed 16-bit Integer to Floating-Point
SMPDefsFlags[NN_pswapd] = false; // Packed Swap Double Word
// Undocumented FP instructions (thanks to norbert.juffa@adm.com)
SMPDefsFlags[NN_fstp1] = false; // Alias of Store Real and Pop
SMPDefsFlags[NN_fxch4] = false; // Alias of Exchange Registers
SMPDefsFlags[NN_ffreep] = false; // Free Register and Pop
SMPDefsFlags[NN_fxch7] = false; // Alias of Exchange Registers
SMPDefsFlags[NN_fstp8] = false; // Alias of Store Real and Pop
SMPDefsFlags[NN_fstp9] = false; // Alias of Store Real and Pop
// Pentium 4 instructions
SMPDefsFlags[NN_addpd] = false; // Add Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_addsd] = false; // Add Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_andnpd] = false; // Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_andpd] = false; // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_clflush] = false; // Flush Cache Line
SMPDefsFlags[NN_cmppd] = false; // Compare Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_cmpsd] = false; // Compare Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_cvtdq2pd] = false; // Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_cvtdq2ps] = false; // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_cvtpd2dq] = false; // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_cvtpd2pi] = false; // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_cvtpd2ps] = false; // Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_cvtpi2pd] = false; // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_cvtps2dq] = false; // Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_cvtps2pd] = false; // Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_cvtsd2si] = false; // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
SMPDefsFlags[NN_cvtsd2ss] = false; // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
SMPDefsFlags[NN_cvtsi2sd] = false; // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_cvtss2sd] = false; // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_cvttpd2dq] = false; // Convert With Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_cvttpd2pi] = false; // Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_cvttps2dq] = false; // Convert With Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_cvttsd2si] = false; // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
SMPDefsFlags[NN_divpd] = false; // Divide Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_divsd] = false; // Divide Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_lfence] = false; // Load Fence
SMPDefsFlags[NN_maskmovdqu] = false; // Store Selected Bytes of Double Quadword
SMPDefsFlags[NN_maxpd] = false; // Return Maximum Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_maxsd] = false; // Return Maximum Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_mfence] = false; // Memory Fence
SMPDefsFlags[NN_minpd] = false; // Return Minimum Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_minsd] = false; // Return Minimum Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_movapd] = false; // Move Aligned Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_movdq2q] = false; // Move Quadword from XMM to MMX Register
SMPDefsFlags[NN_movdqa] = false; // Move Aligned Double Quadword
SMPDefsFlags[NN_movdqu] = false; // Move Unaligned Double Quadword
SMPDefsFlags[NN_movhpd] = false; // Move High Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_movlpd] = false; // Move Low Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_movmskpd] = false; // Extract Packed Double-Precision Floating-Point Sign Mask
SMPDefsFlags[NN_movntdq] = false; // Store Double Quadword Using Non-Temporal Hint
SMPDefsFlags[NN_movnti] = false; // Store Doubleword Using Non-Temporal Hint
SMPDefsFlags[NN_movntpd] = false; // Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
SMPDefsFlags[NN_movq2dq] = false; // Move Quadword from MMX to XMM Register
SMPDefsFlags[NN_movsd] = false; // Move Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_movupd] = false; // Move Unaligned Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_mulpd] = false; // Multiply Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_mulsd] = false; // Multiply Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_orpd] = false; // Bitwise Logical OR of Double-Precision Floating-Point Values
SMPDefsFlags[NN_paddq] = false; // Add Packed Quadword Integers
SMPDefsFlags[NN_pause] = false; // Spin Loop Hint
SMPDefsFlags[NN_pmuludq] = false; // Multiply Packed Unsigned Doubleword Integers
SMPDefsFlags[NN_pshufd] = false; // Shuffle Packed Doublewords
SMPDefsFlags[NN_pshufhw] = false; // Shuffle Packed High Words
SMPDefsFlags[NN_pshuflw] = false; // Shuffle Packed Low Words
SMPDefsFlags[NN_pslldq] = false; // Shift Double Quadword Left Logical
SMPDefsFlags[NN_psrldq] = false; // Shift Double Quadword Right Logical
SMPDefsFlags[NN_psubq] = false; // Subtract Packed Quadword Integers
SMPDefsFlags[NN_punpckhqdq] = false; // Unpack High Data
SMPDefsFlags[NN_punpcklqdq] = false; // Unpack Low Data
SMPDefsFlags[NN_shufpd] = false; // Shuffle Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_sqrtpd] = false; // Compute Square Roots of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_sqrtsd] = false; // Compute Square Rootof Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_subpd] = false; // Subtract Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_subsd] = false; // Subtract Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_unpckhpd] = false; // Unpack and Interleave High Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_unpcklpd] = false; // Unpack and Interleave Low Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_xorpd] = false; // Bitwise Logical OR of Double-Precision Floating-Point Values
// AMD syscall/sysret instructions NOTE: not AMD, found in Intel manual
// AMD64 instructions NOTE: not AMD, found in Intel manual
SMPDefsFlags[NN_swapgs] = false; // Exchange GS base with KernelGSBase MSR
// New Pentium instructions (SSE3)
SMPDefsFlags[NN_movddup] = false; // Move One Double-FP and Duplicate
SMPDefsFlags[NN_movshdup] = false; // Move Packed Single-FP High and Duplicate
SMPDefsFlags[NN_movsldup] = false; // Move Packed Single-FP Low and Duplicate
// Missing AMD64 instructions NOTE: also found in Intel manual
SMPDefsFlags[NN_movsxd] = false; // Move with Sign-Extend Doubleword
// SSE3 instructions
SMPDefsFlags[NN_addsubpd] = false; // Add /Sub packed DP FP numbers
SMPDefsFlags[NN_addsubps] = false; // Add /Sub packed SP FP numbers
SMPDefsFlags[NN_haddpd] = false; // Add horizontally packed DP FP numbers
SMPDefsFlags[NN_haddps] = false; // Add horizontally packed SP FP numbers
SMPDefsFlags[NN_hsubpd] = false; // Sub horizontally packed DP FP numbers
SMPDefsFlags[NN_hsubps] = false; // Sub horizontally packed SP FP numbers
SMPDefsFlags[NN_monitor] = false; // Set up a linear address range to be monitored by hardware
SMPDefsFlags[NN_mwait] = false; // Wait until write-back store performed within the range specified by the MONITOR instruction
SMPDefsFlags[NN_fisttp] = false; // Store ST in intXX (chop) and pop
SMPDefsFlags[NN_lddqu] = false; // Load unaligned integer 128-bit
// SSSE3 instructions
SMPDefsFlags[NN_psignb] = false; // Packed SIGN Byte
SMPDefsFlags[NN_psignw] = false; // Packed SIGN Word
SMPDefsFlags[NN_psignd] = false; // Packed SIGN Doubleword
SMPDefsFlags[NN_pshufb] = false; // Packed Shuffle Bytes
SMPDefsFlags[NN_pmulhrsw] = false; // Packed Multiply High with Round and Scale
SMPDefsFlags[NN_pmaddubsw] = false; // Multiply and Add Packed Signed and Unsigned Bytes
SMPDefsFlags[NN_phsubsw] = false; // Packed Horizontal Subtract and Saturate
SMPDefsFlags[NN_phaddsw] = false; // Packed Horizontal Add and Saturate
SMPDefsFlags[NN_phaddw] = false; // Packed Horizontal Add Word
SMPDefsFlags[NN_phaddd] = false; // Packed Horizontal Add Doubleword
SMPDefsFlags[NN_phsubw] = false; // Packed Horizontal Subtract Word
SMPDefsFlags[NN_phsubd] = false; // Packed Horizontal Subtract Doubleword
SMPDefsFlags[NN_palignr] = false; // Packed Align Right
SMPDefsFlags[NN_pabsb] = false; // Packed Absolute Value Byte
SMPDefsFlags[NN_pabsw] = false; // Packed Absolute Value Word
SMPDefsFlags[NN_pabsd] = false; // Packed Absolute Value Doubleword
// VMX instructions
#if 599 < IDA_SDK_VERSION
SMPDefsFlags[NN_ud2] = false; // Undefined Instruction
// Added with x86-64
SMPDefsFlags[NN_rdtscp] = false; // Read Time-Stamp Counter and Processor ID
// Geode LX 3DNow! extensions
SMPDefsFlags[NN_pfrcpv] = false; // Reciprocal Approximation for a Pair of 32-bit Floats
SMPDefsFlags[NN_pfrsqrtv] = false; // Reciprocal Square Root Approximation for a Pair of 32-bit Floats
// SSE2 pseudoinstructions
SMPDefsFlags[NN_cmpeqpd] = false; // Packed Double-FP Compare EQ
SMPDefsFlags[NN_cmpltpd] = false; // Packed Double-FP Compare LT
SMPDefsFlags[NN_cmplepd] = false; // Packed Double-FP Compare LE
SMPDefsFlags[NN_cmpunordpd] = false; // Packed Double-FP Compare UNORD
SMPDefsFlags[NN_cmpneqpd] = false; // Packed Double-FP Compare NOT EQ
SMPDefsFlags[NN_cmpnltpd] = false; // Packed Double-FP Compare NOT LT
SMPDefsFlags[NN_cmpnlepd] = false; // Packed Double-FP Compare NOT LE
SMPDefsFlags[NN_cmpordpd] = false; // Packed Double-FP Compare ORDERED
SMPDefsFlags[NN_cmpeqsd] = false; // Scalar Double-FP Compare EQ
SMPDefsFlags[NN_cmpltsd] = false; // Scalar Double-FP Compare LT
SMPDefsFlags[NN_cmplesd] = false; // Scalar Double-FP Compare LE
SMPDefsFlags[NN_cmpunordsd] = false; // Scalar Double-FP Compare UNORD
SMPDefsFlags[NN_cmpneqsd] = false; // Scalar Double-FP Compare NOT EQ
SMPDefsFlags[NN_cmpnltsd] = false; // Scalar Double-FP Compare NOT LT
SMPDefsFlags[NN_cmpnlesd] = false; // Scalar Double-FP Compare NOT LE
SMPDefsFlags[NN_cmpordsd] = false; // Scalar Double-FP Compare ORDERED
// SSSE4.1 instructions
SMPDefsFlags[NN_blendpd] = false; // Blend Packed Double Precision Floating-Point Values
SMPDefsFlags[NN_blendps] = false; // Blend Packed Single Precision Floating-Point Values
SMPDefsFlags[NN_blendvpd] = false; // Variable Blend Packed Double Precision Floating-Point Values
SMPDefsFlags[NN_blendvps] = false; // Variable Blend Packed Single Precision Floating-Point Values
SMPDefsFlags[NN_dppd] = false; // Dot Product of Packed Double Precision Floating-Point Values
SMPDefsFlags[NN_dpps] = false; // Dot Product of Packed Single Precision Floating-Point Values
SMPDefsFlags[NN_extractps] = 2; // Extract Packed Single Precision Floating-Point Value
SMPDefsFlags[NN_insertps] = false; // Insert Packed Single Precision Floating-Point Value
SMPDefsFlags[NN_movntdqa] = false; // Load Double Quadword Non-Temporal Aligned Hint
SMPDefsFlags[NN_mpsadbw] = false; // Compute Multiple Packed Sums of Absolute Difference
SMPDefsFlags[NN_packusdw] = false; // Pack with Unsigned Saturation
SMPDefsFlags[NN_pblendvb] = false; // Variable Blend Packed Bytes
SMPDefsFlags[NN_pblendw] = false; // Blend Packed Words
SMPDefsFlags[NN_pcmpeqq] = false; // Compare Packed Qword Data for Equal
SMPDefsFlags[NN_pextrb] = false; // Extract Byte
SMPDefsFlags[NN_pextrd] = false; // Extract Dword
SMPDefsFlags[NN_pextrq] = false; // Extract Qword
SMPDefsFlags[NN_phminposuw] = false; // Packed Horizontal Word Minimum
SMPDefsFlags[NN_pinsrb] = false; // Insert Byte
SMPDefsFlags[NN_pinsrd] = false; // Insert Dword
SMPDefsFlags[NN_pinsrq] = false; // Insert Qword
SMPDefsFlags[NN_pmaxsb] = false; // Maximum of Packed Signed Byte Integers
SMPDefsFlags[NN_pmaxsd] = false; // Maximum of Packed Signed Dword Integers
SMPDefsFlags[NN_pmaxud] = false; // Maximum of Packed Unsigned Dword Integers
SMPDefsFlags[NN_pmaxuw] = false; // Maximum of Packed Word Integers
SMPDefsFlags[NN_pminsb] = false; // Minimum of Packed Signed Byte Integers
SMPDefsFlags[NN_pminsd] = false; // Minimum of Packed Signed Dword Integers
SMPDefsFlags[NN_pminud] = false; // Minimum of Packed Unsigned Dword Integers
SMPDefsFlags[NN_pminuw] = false; // Minimum of Packed Word Integers
SMPDefsFlags[NN_pmovsxbw] = false; // Packed Move with Sign Extend
SMPDefsFlags[NN_pmovsxbd] = false; // Packed Move with Sign Extend
SMPDefsFlags[NN_pmovsxbq] = false; // Packed Move with Sign Extend
SMPDefsFlags[NN_pmovsxwd] = false; // Packed Move with Sign Extend
SMPDefsFlags[NN_pmovsxwq] = false; // Packed Move with Sign Extend
SMPDefsFlags[NN_pmovsxdq] = false; // Packed Move with Sign Extend
SMPDefsFlags[NN_pmovzxbw] = false; // Packed Move with Zero Extend
SMPDefsFlags[NN_pmovzxbd] = false; // Packed Move with Zero Extend
SMPDefsFlags[NN_pmovzxbq] = false; // Packed Move with Zero Extend
SMPDefsFlags[NN_pmovzxwd] = false; // Packed Move with Zero Extend
SMPDefsFlags[NN_pmovzxwq] = false; // Packed Move with Zero Extend
SMPDefsFlags[NN_pmovzxdq] = false; // Packed Move with Zero Extend
SMPDefsFlags[NN_pmuldq] = false; // Multiply Packed Signed Dword Integers
SMPDefsFlags[NN_pmulld] = false; // Multiply Packed Signed Dword Integers and Store Low Result
SMPDefsFlags[NN_roundpd] = false; // Round Packed Double Precision Floating-Point Values
SMPDefsFlags[NN_roundps] = false; // Round Packed Single Precision Floating-Point Values
SMPDefsFlags[NN_roundsd] = false; // Round Scalar Double Precision Floating-Point Values
SMPDefsFlags[NN_roundss] = false; // Round Scalar Single Precision Floating-Point Values
// SSSE4.2 instructions
SMPDefsFlags[NN_crc32] = false; // Accumulate CRC32 Value
SMPDefsFlags[NN_pcmpgtq] = false; // Compare Packed Data for Greater Than
// AMD SSE4a instructions
SMPDefsFlags[NN_extrq] = false; // Extract Field From Register
SMPDefsFlags[NN_insertq] = false; // Insert Field
SMPDefsFlags[NN_movntsd] = false; // Move Non-Temporal Scalar Double-Precision Floating-Point
SMPDefsFlags[NN_movntss] = false; // Move Non-Temporal Scalar Single-Precision Floating-Point
// xsave/xrstor instructions
SMPDefsFlags[NN_xgetbv] = false; // Get Value of Extended Control Register
SMPDefsFlags[NN_xrstor] = false; // Restore Processor Extended States
SMPDefsFlags[NN_xsave] = false; // Save Processor Extended States
SMPDefsFlags[NN_xsetbv] = false; // Set Value of Extended Control Register
// Intel Safer Mode Extensions (SMX)
// AMD-V Virtualization ISA Extension
SMPDefsFlags[NN_invlpga] = false; // Invalidate TLB Entry in a Specified ASID
SMPDefsFlags[NN_skinit] = false; // Secure Init and Jump with Attestation
SMPDefsFlags[NN_vmexit] = false; // Stop Executing Guest, Begin Executing Host
SMPDefsFlags[NN_vmload] = false; // Load State from VMCB
SMPDefsFlags[NN_vmmcall] = false; // Call VMM
SMPDefsFlags[NN_vmrun] = false; // Run Virtual Machine
SMPDefsFlags[NN_vmsave] = false; // Save State to VMCB
// VMX+ instructions
SMPDefsFlags[NN_invept] = false; // Invalidate Translations Derived from EPT
SMPDefsFlags[NN_invvpid] = false; // Invalidate Translations Based on VPID
// Intel Atom instructions
SMPDefsFlags[NN_movbe] = false; // Move Data After Swapping Bytes
// Intel AES instructions
SMPDefsFlags[NN_aesenc] = false; // Perform One Round of an AES Encryption Flow
SMPDefsFlags[NN_aesenclast] = false; // Perform the Last Round of an AES Encryption Flow
SMPDefsFlags[NN_aesdec] = false; // Perform One Round of an AES Decryption Flow
SMPDefsFlags[NN_aesdeclast] = false; // Perform the Last Round of an AES Decryption Flow
SMPDefsFlags[NN_aesimc] = false; // Perform the AES InvMixColumn Transformation
SMPDefsFlags[NN_aeskeygenassist] = false; // AES Round Key Generation Assist
// Carryless multiplication
SMPDefsFlags[NN_pclmulqdq] = false; // Carry-Less Multiplication Quadword
// Returns modified by operand size prefixes
SMPDefsFlags[NN_retnw] = false; // Return Near from Procedure (use16)
SMPDefsFlags[NN_retnd] = false; // Return Near from Procedure (use32)
SMPDefsFlags[NN_retnq] = false; // Return Near from Procedure (use64)
SMPDefsFlags[NN_retfw] = false; // Return Far from Procedure (use16)
SMPDefsFlags[NN_retfd] = false; // Return Far from Procedure (use32)
SMPDefsFlags[NN_retfq] = false; // Return Far from Procedure (use64)
// RDRAND support
// new GPR instructions
SMPDefsFlags[NN_mulx] = false; // Unsigned Multiply Without Affecting Flags
SMPDefsFlags[NN_pdep] = false; // Parallel Bits Deposit
SMPDefsFlags[NN_pext] = false; // Parallel Bits Extract
SMPDefsFlags[NN_rorx] = false; // Rotate Right Logical Without Affecting Flags
SMPDefsFlags[NN_sarx] = false; // Shift Arithmetically Right Without Affecting Flags
SMPDefsFlags[NN_shlx] = false; // Shift Logically Left Without Affecting Flags
SMPDefsFlags[NN_shrx] = false; // Shift Logically Right Without Affecting Flags
SMPDefsFlags[NN_xsaveopt] = false; // Save Processor Extended States Optimized
SMPDefsFlags[NN_invpcid] = false; // Invalidate Processor Context ID
SMPDefsFlags[NN_rdseed] = false; // Read Random Seed
SMPDefsFlags[NN_rdfsbase] = false; // Read FS Segment Base
SMPDefsFlags[NN_rdgsbase] = false; // Read GS Segment Base
SMPDefsFlags[NN_wrfsbase] = false; // Write FS Segment Base
SMPDefsFlags[NN_wrgsbase] = false; // Write GS Segment Base
// new AVX instructions
SMPDefsFlags[NN_vaddpd] = false; // Add Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vaddps] = false; // Packed Single-FP Add
SMPDefsFlags[NN_vaddsd] = false; // Add Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vaddss] = false; // Scalar Single-FP Add
SMPDefsFlags[NN_vaddsubpd] = false; // Add /Sub packed DP FP numbers
SMPDefsFlags[NN_vaddsubps] = false; // Add /Sub packed SP FP numbers
SMPDefsFlags[NN_vaesdec] = false; // Perform One Round of an AES Decryption Flow
SMPDefsFlags[NN_vaesdeclast] = false; // Perform the Last Round of an AES Decryption Flow
SMPDefsFlags[NN_vaesenc] = false; // Perform One Round of an AES Encryption Flow
SMPDefsFlags[NN_vaesenclast] = false; // Perform the Last Round of an AES Encryption Flow
SMPDefsFlags[NN_vaesimc] = false; // Perform the AES InvMixColumn Transformation
SMPDefsFlags[NN_vaeskeygenassist] = false; // AES Round Key Generation Assist
SMPDefsFlags[NN_vandnpd] = false; // Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vandnps] = false; // Bitwise Logical And Not for Single-FP
SMPDefsFlags[NN_vandpd] = false; // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vandps] = false; // Bitwise Logical And for Single-FP
SMPDefsFlags[NN_vblendpd] = false; // Blend Packed Double Precision Floating-Point Values
SMPDefsFlags[NN_vblendps] = false; // Blend Packed Single Precision Floating-Point Values
SMPDefsFlags[NN_vblendvpd] = false; // Variable Blend Packed Double Precision Floating-Point Values
SMPDefsFlags[NN_vblendvps] = false; // Variable Blend Packed Single Precision Floating-Point Values
SMPDefsFlags[NN_vbroadcastf128] = false; // Broadcast 128 Bits of Floating-Point Data
SMPDefsFlags[NN_vbroadcasti128] = false; // Broadcast 128 Bits of Integer Data
SMPDefsFlags[NN_vbroadcastsd] = false; // Broadcast Double-Precision Floating-Point Element
SMPDefsFlags[NN_vbroadcastss] = false; // Broadcast Single-Precision Floating-Point Element
SMPDefsFlags[NN_vcmppd] = false; // Compare Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vcmpps] = false; // Packed Single-FP Compare
SMPDefsFlags[NN_vcmpsd] = false; // Compare Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vcmpss] = false; // Scalar Single-FP Compare
SMPDefsFlags[NN_vcomisd] = false; // Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
SMPDefsFlags[NN_vcomiss] = false; // Scalar Ordered Single-FP Compare and Set EFLAGS
SMPDefsFlags[NN_vcvtdq2pd] = false; // Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vcvtdq2ps] = false; // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vcvtpd2dq] = false; // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_vcvtpd2ps] = false; // Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vcvtph2ps] = false; // Convert 16-bit FP Values to Single-Precision FP Values
SMPDefsFlags[NN_vcvtps2dq] = false; // Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_vcvtps2pd] = false; // Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vcvtps2ph] = false; // Convert Single-Precision FP value to 16-bit FP value
SMPDefsFlags[NN_vcvtsd2si] = false; // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
SMPDefsFlags[NN_vcvtsd2ss] = false; // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
SMPDefsFlags[NN_vcvtsi2sd] = false; // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_vcvtsi2ss] = false; // Scalar signed INT32 to Single-FP conversion
SMPDefsFlags[NN_vcvtss2sd] = false; // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_vcvtss2si] = false; // Scalar Single-FP to signed INT32 conversion
SMPDefsFlags[NN_vcvttpd2dq] = false; // Convert With Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_vcvttps2dq] = false; // Convert With Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_vcvttsd2si] = false; // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
SMPDefsFlags[NN_vcvttss2si] = false; // Scalar Single-FP to signed INT32 conversion (truncate)
SMPDefsFlags[NN_vdivpd] = false; // Divide Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vdivps] = false; // Packed Single-FP Divide
SMPDefsFlags[NN_vdivsd] = false; // Divide Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vdivss] = false; // Scalar Single-FP Divide
SMPDefsFlags[NN_vdppd] = false; // Dot Product of Packed Double Precision Floating-Point Values
SMPDefsFlags[NN_vdpps] = false; // Dot Product of Packed Single Precision Floating-Point Values
SMPDefsFlags[NN_vextractf128] = false; // Extract Packed Floating-Point Values
SMPDefsFlags[NN_vextracti128] = false; // Extract Packed Integer Values
SMPDefsFlags[NN_vextractps] = false; // Extract Packed Floating-Point Values
SMPDefsFlags[NN_vfmadd132pd] = false; // Fused Multiply-Add of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmadd132ps] = false; // Fused Multiply-Add of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmadd132sd] = false; // Fused Multiply-Add of Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmadd132ss] = false; // Fused Multiply-Add of Scalar Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmadd213pd] = false; // Fused Multiply-Add of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmadd213ps] = false; // Fused Multiply-Add of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmadd213sd] = false; // Fused Multiply-Add of Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmadd213ss] = false; // Fused Multiply-Add of Scalar Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmadd231pd] = false; // Fused Multiply-Add of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmadd231ps] = false; // Fused Multiply-Add of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmadd231sd] = false; // Fused Multiply-Add of Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmadd231ss] = false; // Fused Multiply-Add of Scalar Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmaddsub132pd] = false; // Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmaddsub132ps] = false; // Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmaddsub213pd] = false; // Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmaddsub213ps] = false; // Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmaddsub231pd] = false; // Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmaddsub231ps] = false; // Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsub132pd] = false; // Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsub132ps] = false; // Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsub132sd] = false; // Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsub132ss] = false; // Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsub213pd] = false; // Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsub213ps] = false; // Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsub213sd] = false; // Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsub213ss] = false; // Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsub231pd] = false; // Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsub231ps] = false; // Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsub231sd] = false; // Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsub231ss] = false; // Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsubadd132pd] = false; // Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsubadd132ps] = false; // Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsubadd213pd] = false; // Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsubadd213ps] = false; // Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsubadd231pd] = false; // Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsubadd231ps] = false; // Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmadd132pd] = false; // Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmadd132ps] = false; // Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmadd132sd] = false; // Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmadd132ss] = false; // Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmadd213pd] = false; // Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmadd213ps] = false; // Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmadd213sd] = false; // Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmadd213ss] = false; // Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmadd231pd] = false; // Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmadd231ps] = false; // Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmadd231sd] = false; // Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmadd231ss] = false; // Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmsub132pd] = false; // Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmsub132ps] = false; // Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmsub132sd] = false; // Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmsub132ss] = false; // Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmsub213pd] = false; // Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmsub213ps] = false; // Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmsub213sd] = false; // Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmsub213ss] = false; // Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmsub231pd] = false; // Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmsub231ps] = false; // Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmsub231sd] = false; // Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmsub231ss] = false; // Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values
SMPDefsFlags[NN_vgatherdps] = false; // Gather Packed SP FP Values Using Signed Dword Indices
SMPDefsFlags[NN_vgatherdpd] = false; // Gather Packed DP FP Values Using Signed Dword Indices
SMPDefsFlags[NN_vgatherqps] = false; // Gather Packed SP FP Values Using Signed Qword Indices
SMPDefsFlags[NN_vgatherqpd] = false; // Gather Packed DP FP Values Using Signed Qword Indices
SMPDefsFlags[NN_vhaddpd] = false; // Add horizontally packed DP FP numbers
SMPDefsFlags[NN_vhaddps] = false; // Add horizontally packed SP FP numbers
SMPDefsFlags[NN_vhsubpd] = false; // Sub horizontally packed DP FP numbers
SMPDefsFlags[NN_vhsubps] = false; // Sub horizontally packed SP FP numbers
SMPDefsFlags[NN_vinsertf128] = false; // Insert Packed Floating-Point Values
SMPDefsFlags[NN_vinserti128] = false; // Insert Packed Integer Values
SMPDefsFlags[NN_vinsertps] = false; // Insert Packed Single Precision Floating-Point Value
SMPDefsFlags[NN_vlddqu] = false; // Load Unaligned Packed Integer Values
SMPDefsFlags[NN_vldmxcsr] = false; // Load Streaming SIMD Extensions Technology Control/Status Register
SMPDefsFlags[NN_vmaskmovdqu] = false; // Store Selected Bytes of Double Quadword with NT Hint
SMPDefsFlags[NN_vmaskmovpd] = false; // Conditionally Load Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vmaskmovps] = false; // Conditionally Load Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vmaxpd] = false; // Return Maximum Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vmaxps] = false; // Packed Single-FP Maximum
SMPDefsFlags[NN_vmaxsd] = false; // Return Maximum Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_vmaxss] = false; // Scalar Single-FP Maximum
SMPDefsFlags[NN_vminpd] = false; // Return Minimum Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vminps] = false; // Packed Single-FP Minimum
SMPDefsFlags[NN_vminsd] = false; // Return Minimum Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_vminss] = false; // Scalar Single-FP Minimum
SMPDefsFlags[NN_vmovapd] = false; // Move Aligned Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vmovaps] = false; // Move Aligned Four Packed Single-FP
SMPDefsFlags[NN_vmovd] = false; // Move 32 bits
SMPDefsFlags[NN_vmovddup] = false; // Move One Double-FP and Duplicate
SMPDefsFlags[NN_vmovdqa] = false; // Move Aligned Double Quadword
SMPDefsFlags[NN_vmovdqu] = false; // Move Unaligned Double Quadword
SMPDefsFlags[NN_vmovhlps] = false; // Move High to Low Packed Single-FP
SMPDefsFlags[NN_vmovhpd] = false; // Move High Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vmovhps] = false; // Move High Packed Single-FP
SMPDefsFlags[NN_vmovlhps] = false; // Move Low to High Packed Single-FP
SMPDefsFlags[NN_vmovlpd] = false; // Move Low Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vmovlps] = false; // Move Low Packed Single-FP
SMPDefsFlags[NN_vmovmskpd] = false; // Extract Packed Double-Precision Floating-Point Sign Mask
SMPDefsFlags[NN_vmovmskps] = false; // Move Mask to Register
SMPDefsFlags[NN_vmovntdq] = false; // Store Double Quadword Using Non-Temporal Hint
SMPDefsFlags[NN_vmovntdqa] = false; // Load Double Quadword Non-Temporal Aligned Hint
SMPDefsFlags[NN_vmovntpd] = false; // Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
SMPDefsFlags[NN_vmovntps] = false; // Move Aligned Four Packed Single-FP Non Temporal
SMPDefsFlags[NN_vmovntsd] = false; // Move Non-Temporal Scalar Double-Precision Floating-Point
SMPDefsFlags[NN_vmovntss] = false; // Move Non-Temporal Scalar Single-Precision Floating-Point
SMPDefsFlags[NN_vmovq] = false; // Move 64 bits
SMPDefsFlags[NN_vmovsd] = false; // Move Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vmovshdup] = false; // Move Packed Single-FP High and Duplicate
SMPDefsFlags[NN_vmovsldup] = false; // Move Packed Single-FP Low and Duplicate
SMPDefsFlags[NN_vmovss] = false; // Move Scalar Single-FP
SMPDefsFlags[NN_vmovupd] = false; // Move Unaligned Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vmovups] = false; // Move Unaligned Four Packed Single-FP
SMPDefsFlags[NN_vmpsadbw] = false; // Compute Multiple Packed Sums of Absolute Difference
SMPDefsFlags[NN_vmulpd] = false; // Multiply Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vmulps] = false; // Packed Single-FP Multiply
SMPDefsFlags[NN_vmulsd] = false; // Multiply Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vmulss] = false; // Scalar Single-FP Multiply
SMPDefsFlags[NN_vorpd] = false; // Bitwise Logical OR of Double-Precision Floating-Point Values
SMPDefsFlags[NN_vorps] = false; // Bitwise Logical OR for Single-FP Data
SMPDefsFlags[NN_vpabsb] = false; // Packed Absolute Value Byte
SMPDefsFlags[NN_vpabsd] = false; // Packed Absolute Value Doubleword
SMPDefsFlags[NN_vpabsw] = false; // Packed Absolute Value Word
SMPDefsFlags[NN_vpackssdw] = false; // Pack with Signed Saturation (Dword->Word)
SMPDefsFlags[NN_vpacksswb] = false; // Pack with Signed Saturation (Word->Byte)
SMPDefsFlags[NN_vpackusdw] = false; // Pack with Unsigned Saturation
SMPDefsFlags[NN_vpackuswb] = false; // Pack with Unsigned Saturation (Word->Byte)
SMPDefsFlags[NN_vpaddb] = false; // Packed Add Byte
SMPDefsFlags[NN_vpaddd] = false; // Packed Add Dword
SMPDefsFlags[NN_vpaddq] = false; // Add Packed Quadword Integers
SMPDefsFlags[NN_vpaddsb] = false; // Packed Add with Saturation (Byte)
SMPDefsFlags[NN_vpaddsw] = false; // Packed Add with Saturation (Word)
SMPDefsFlags[NN_vpaddusb] = false; // Packed Add Unsigned with Saturation (Byte)
SMPDefsFlags[NN_vpaddusw] = false; // Packed Add Unsigned with Saturation (Word)
SMPDefsFlags[NN_vpaddw] = false; // Packed Add Word
SMPDefsFlags[NN_vpalignr] = false; // Packed Align Right
SMPDefsFlags[NN_vpand] = false; // Bitwise Logical And
SMPDefsFlags[NN_vpandn] = false; // Bitwise Logical And Not
SMPDefsFlags[NN_vpavgb] = false; // Packed Average (Byte)
SMPDefsFlags[NN_vpavgw] = false; // Packed Average (Word)
SMPDefsFlags[NN_vpblendd] = false; // Blend Packed Dwords
SMPDefsFlags[NN_vpblendvb] = false; // Variable Blend Packed Bytes
SMPDefsFlags[NN_vpblendw] = false; // Blend Packed Words
SMPDefsFlags[NN_vpbroadcastb] = false; // Broadcast a Byte Integer
SMPDefsFlags[NN_vpbroadcastd] = false; // Broadcast a Dword Integer
SMPDefsFlags[NN_vpbroadcastq] = false; // Broadcast a Qword Integer
SMPDefsFlags[NN_vpbroadcastw] = false; // Broadcast a Word Integer
SMPDefsFlags[NN_vpclmulqdq] = false; // Carry-Less Multiplication Quadword
SMPDefsFlags[NN_vpcmpeqb] = false; // Packed Compare for Equal (Byte)
SMPDefsFlags[NN_vpcmpeqd] = false; // Packed Compare for Equal (Dword)
SMPDefsFlags[NN_vpcmpeqq] = false; // Compare Packed Qword Data for Equal
SMPDefsFlags[NN_vpcmpeqw] = false; // Packed Compare for Equal (Word)
SMPDefsFlags[NN_vpcmpestri] = false; // Packed Compare Explicit Length Strings, Return Index
SMPDefsFlags[NN_vpcmpestrm] = false; // Packed Compare Explicit Length Strings, Return Mask
SMPDefsFlags[NN_vpcmpgtb] = false; // Packed Compare for Greater Than (Byte)
SMPDefsFlags[NN_vpcmpgtd] = false; // Packed Compare for Greater Than (Dword)
SMPDefsFlags[NN_vpcmpgtq] = false; // Compare Packed Data for Greater Than
SMPDefsFlags[NN_vpcmpgtw] = false; // Packed Compare for Greater Than (Word)
SMPDefsFlags[NN_vpcmpistri] = false; // Packed Compare Implicit Length Strings, Return Index
SMPDefsFlags[NN_vpcmpistrm] = false; // Packed Compare Implicit Length Strings, Return Mask
SMPDefsFlags[NN_vperm2f128] = false; // Permute Floating-Point Values
SMPDefsFlags[NN_vperm2i128] = false; // Permute Integer Values
SMPDefsFlags[NN_vpermd] = false; // Full Doublewords Element Permutation
SMPDefsFlags[NN_vpermilpd] = false; // Permute Double-Precision Floating-Point Values
SMPDefsFlags[NN_vpermilps] = false; // Permute Single-Precision Floating-Point Values
SMPDefsFlags[NN_vpermpd] = false; // Permute Double-Precision Floating-Point Elements
SMPDefsFlags[NN_vpermps] = false; // Permute Single-Precision Floating-Point Elements
SMPDefsFlags[NN_vpermq] = false; // Qwords Element Permutation
SMPDefsFlags[NN_vpextrb] = false; // Extract Byte
SMPDefsFlags[NN_vpextrd] = false; // Extract Dword
SMPDefsFlags[NN_vpextrq] = false; // Extract Qword
SMPDefsFlags[NN_vpextrw] = false; // Extract Word
SMPDefsFlags[NN_vpgatherdd] = false; // Gather Packed Dword Values Using Signed Dword Indices
SMPDefsFlags[NN_vpgatherdq] = false; // Gather Packed Qword Values Using Signed Dword Indices
SMPDefsFlags[NN_vpgatherqd] = false; // Gather Packed Dword Values Using Signed Qword Indices
SMPDefsFlags[NN_vpgatherqq] = false; // Gather Packed Qword Values Using Signed Qword Indices
SMPDefsFlags[NN_vphaddd] = false; // Packed Horizontal Add Doubleword
SMPDefsFlags[NN_vphaddsw] = false; // Packed Horizontal Add and Saturate
SMPDefsFlags[NN_vphaddw] = false; // Packed Horizontal Add Word
SMPDefsFlags[NN_vphminposuw] = false; // Packed Horizontal Word Minimum
SMPDefsFlags[NN_vphsubd] = false; // Packed Horizontal Subtract Doubleword
SMPDefsFlags[NN_vphsubsw] = false; // Packed Horizontal Subtract and Saturate
SMPDefsFlags[NN_vphsubw] = false; // Packed Horizontal Subtract Word
SMPDefsFlags[NN_vpinsrb] = false; // Insert Byte
SMPDefsFlags[NN_vpinsrd] = false; // Insert Dword
SMPDefsFlags[NN_vpinsrq] = false; // Insert Qword
SMPDefsFlags[NN_vpinsrw] = false; // Insert Word
SMPDefsFlags[NN_vpmaddubsw] = false; // Multiply and Add Packed Signed and Unsigned Bytes
SMPDefsFlags[NN_vpmaddwd] = false; // Packed Multiply and Add
SMPDefsFlags[NN_vpmaskmovd] = false; // Conditionally Store Dword Values Using Mask
SMPDefsFlags[NN_vpmaskmovq] = false; // Conditionally Store Qword Values Using Mask
SMPDefsFlags[NN_vpmaxsb] = false; // Maximum of Packed Signed Byte Integers
SMPDefsFlags[NN_vpmaxsd] = false; // Maximum of Packed Signed Dword Integers
SMPDefsFlags[NN_vpmaxsw] = false; // Packed Signed Integer Word Maximum
SMPDefsFlags[NN_vpmaxub] = false; // Packed Unsigned Integer Byte Maximum
SMPDefsFlags[NN_vpmaxud] = false; // Maximum of Packed Unsigned Dword Integers
SMPDefsFlags[NN_vpmaxuw] = false; // Maximum of Packed Word Integers
SMPDefsFlags[NN_vpminsb] = false; // Minimum of Packed Signed Byte Integers
SMPDefsFlags[NN_vpminsd] = false; // Minimum of Packed Signed Dword Integers
SMPDefsFlags[NN_vpminsw] = false; // Packed Signed Integer Word Minimum
SMPDefsFlags[NN_vpminub] = false; // Packed Unsigned Integer Byte Minimum
SMPDefsFlags[NN_vpminud] = false; // Minimum of Packed Unsigned Dword Integers
SMPDefsFlags[NN_vpminuw] = false; // Minimum of Packed Word Integers
SMPDefsFlags[NN_vpmovmskb] = false; // Move Byte Mask to Integer
SMPDefsFlags[NN_vpmovsxbd] = false; // Packed Move with Sign Extend
SMPDefsFlags[NN_vpmovsxbq] = false; // Packed Move with Sign Extend
SMPDefsFlags[NN_vpmovsxbw] = false; // Packed Move with Sign Extend
SMPDefsFlags[NN_vpmovsxdq] = false; // Packed Move with Sign Extend
SMPDefsFlags[NN_vpmovsxwd] = false; // Packed Move with Sign Extend
SMPDefsFlags[NN_vpmovsxwq] = false; // Packed Move with Sign Extend
SMPDefsFlags[NN_vpmovzxbd] = false; // Packed Move with Zero Extend
SMPDefsFlags[NN_vpmovzxbq] = false; // Packed Move with Zero Extend
SMPDefsFlags[NN_vpmovzxbw] = false; // Packed Move with Zero Extend
SMPDefsFlags[NN_vpmovzxdq] = false; // Packed Move with Zero Extend
SMPDefsFlags[NN_vpmovzxwd] = false; // Packed Move with Zero Extend
SMPDefsFlags[NN_vpmovzxwq] = false; // Packed Move with Zero Extend
SMPDefsFlags[NN_vpmuldq] = false; // Multiply Packed Signed Dword Integers
SMPDefsFlags[NN_vpmulhrsw] = false; // Packed Multiply High with Round and Scale
SMPDefsFlags[NN_vpmulhuw] = false; // Packed Multiply High Unsigned
SMPDefsFlags[NN_vpmulhw] = false; // Packed Multiply High
SMPDefsFlags[NN_vpmulld] = false; // Multiply Packed Signed Dword Integers and Store Low Result
SMPDefsFlags[NN_vpmullw] = false; // Packed Multiply Low
SMPDefsFlags[NN_vpmuludq] = false; // Multiply Packed Unsigned Doubleword Integers
SMPDefsFlags[NN_vpor] = false; // Bitwise Logical Or
SMPDefsFlags[NN_vpsadbw] = false; // Packed Sum of Absolute Differences
SMPDefsFlags[NN_vpshufb] = false; // Packed Shuffle Bytes
SMPDefsFlags[NN_vpshufd] = false; // Shuffle Packed Doublewords
SMPDefsFlags[NN_vpshufhw] = false; // Shuffle Packed High Words
SMPDefsFlags[NN_vpshuflw] = false; // Shuffle Packed Low Words
SMPDefsFlags[NN_vpsignb] = false; // Packed SIGN Byte
SMPDefsFlags[NN_vpsignd] = false; // Packed SIGN Doubleword
SMPDefsFlags[NN_vpsignw] = false; // Packed SIGN Word
SMPDefsFlags[NN_vpslld] = false; // Packed Shift Left Logical (Dword)
SMPDefsFlags[NN_vpslldq] = false; // Shift Double Quadword Left Logical
SMPDefsFlags[NN_vpsllq] = false; // Packed Shift Left Logical (Qword)
SMPDefsFlags[NN_vpsllvd] = false; // Variable Bit Shift Left Logical (Dword)
SMPDefsFlags[NN_vpsllvq] = false; // Variable Bit Shift Left Logical (Qword)
SMPDefsFlags[NN_vpsllw] = false; // Packed Shift Left Logical (Word)
SMPDefsFlags[NN_vpsrad] = false; // Packed Shift Right Arithmetic (Dword)
SMPDefsFlags[NN_vpsravd] = false; // Variable Bit Shift Right Arithmetic
SMPDefsFlags[NN_vpsraw] = false; // Packed Shift Right Arithmetic (Word)
SMPDefsFlags[NN_vpsrld] = false; // Packed Shift Right Logical (Dword)
SMPDefsFlags[NN_vpsrldq] = false; // Shift Double Quadword Right Logical (Qword)
SMPDefsFlags[NN_vpsrlq] = false; // Packed Shift Right Logical (Qword)
SMPDefsFlags[NN_vpsrlvd] = false; // Variable Bit Shift Right Logical (Dword)
SMPDefsFlags[NN_vpsrlvq] = false; // Variable Bit Shift Right Logical (Qword)
SMPDefsFlags[NN_vpsrlw] = false; // Packed Shift Right Logical (Word)
SMPDefsFlags[NN_vpsubb] = false; // Packed Subtract Byte
SMPDefsFlags[NN_vpsubd] = false; // Packed Subtract Dword
SMPDefsFlags[NN_vpsubq] = false; // Subtract Packed Quadword Integers
SMPDefsFlags[NN_vpsubsb] = false; // Packed Subtract with Saturation (Byte)
SMPDefsFlags[NN_vpsubsw] = false; // Packed Subtract with Saturation (Word)
SMPDefsFlags[NN_vpsubusb] = false; // Packed Subtract Unsigned with Saturation (Byte)
SMPDefsFlags[NN_vpsubusw] = false; // Packed Subtract Unsigned with Saturation (Word)
SMPDefsFlags[NN_vpsubw] = false; // Packed Subtract Word
SMPDefsFlags[NN_vptest] = false; // Logical Compare
SMPDefsFlags[NN_vpunpckhbw] = false; // Unpack High Packed Data (Byte->Word)
SMPDefsFlags[NN_vpunpckhdq] = false; // Unpack High Packed Data (Dword->Qword)
SMPDefsFlags[NN_vpunpckhqdq] = false; // Unpack High Packed Data (Qword->Xmmword)
SMPDefsFlags[NN_vpunpckhwd] = false; // Unpack High Packed Data (Word->Dword)
SMPDefsFlags[NN_vpunpcklbw] = false; // Unpack Low Packed Data (Byte->Word)
SMPDefsFlags[NN_vpunpckldq] = false; // Unpack Low Packed Data (Dword->Qword)
SMPDefsFlags[NN_vpunpcklqdq] = false; // Unpack Low Packed Data (Qword->Xmmword)
SMPDefsFlags[NN_vpunpcklwd] = false; // Unpack Low Packed Data (Word->Dword)
SMPDefsFlags[NN_vpxor] = false; // Bitwise Logical Exclusive Or
SMPDefsFlags[NN_vrcpps] = false; // Packed Single-FP Reciprocal
SMPDefsFlags[NN_vrcpss] = false; // Scalar Single-FP Reciprocal
SMPDefsFlags[NN_vroundpd] = false; // Round Packed Double Precision Floating-Point Values
SMPDefsFlags[NN_vroundps] = false; // Round Packed Single Precision Floating-Point Values
SMPDefsFlags[NN_vroundsd] = false; // Round Scalar Double Precision Floating-Point Values
SMPDefsFlags[NN_vroundss] = false; // Round Scalar Single Precision Floating-Point Values
SMPDefsFlags[NN_vrsqrtps] = false; // Packed Single-FP Square Root Reciprocal
SMPDefsFlags[NN_vrsqrtss] = false; // Scalar Single-FP Square Root Reciprocal
SMPDefsFlags[NN_vshufpd] = false; // Shuffle Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vshufps] = false; // Shuffle Single-FP
SMPDefsFlags[NN_vsqrtpd] = false; // Compute Square Roots of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vsqrtps] = false; // Packed Single-FP Square Root
SMPDefsFlags[NN_vsqrtsd] = false; // Compute Square Rootof Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_vsqrtss] = false; // Scalar Single-FP Square Root
SMPDefsFlags[NN_vstmxcsr] = false; // Store Streaming SIMD Extensions Technology Control/Status Register
SMPDefsFlags[NN_vsubpd] = false; // Subtract Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vsubps] = false; // Packed Single-FP Subtract
SMPDefsFlags[NN_vsubsd] = false; // Subtract Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vsubss] = false; // Scalar Single-FP Subtract
SMPDefsFlags[NN_vtestpd] = false; // Packed Double-Precision Floating-Point Bit Test
SMPDefsFlags[NN_vtestps] = false; // Packed Single-Precision Floating-Point Bit Test
SMPDefsFlags[NN_vucomisd] = false; // Unordered Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
SMPDefsFlags[NN_vucomiss] = false; // Scalar Unordered Single-FP Compare and Set EFLAGS
SMPDefsFlags[NN_vunpckhpd] = false; // Unpack and Interleave High Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vunpckhps] = false; // Unpack High Packed Single-FP Data
SMPDefsFlags[NN_vunpcklpd] = false; // Unpack and Interleave Low Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vunpcklps] = false; // Unpack Low Packed Single-FP Data
SMPDefsFlags[NN_vxorpd] = false; // Bitwise Logical OR of Double-Precision Floating-Point Values
SMPDefsFlags[NN_vxorps] = false; // Bitwise Logical XOR for Single-FP Data
SMPDefsFlags[NN_vzeroall] = false; // Zero All YMM Registers
SMPDefsFlags[NN_vzeroupper] = false; // Zero Upper Bits of YMM Registers
// Transactional Synchronization Extensions
SMPDefsFlags[NN_xabort] = false; // Transaction Abort
SMPDefsFlags[NN_xbegin] = false; // Transaction Begin
SMPDefsFlags[NN_xend] = false; // Transaction End
SMPDefsFlags[NN_xtest] = false; // Test If In Transactional Execution
// Virtual PC synthetic instructions
SMPDefsFlags[NN_vmgetinfo] = false; // Virtual PC - Get VM Information
SMPDefsFlags[NN_vmsetinfo] = false; // Virtual PC - Set VM Information
SMPDefsFlags[NN_vmdxdsbl] = false; // Virtual PC - Disable Direct Execution
SMPDefsFlags[NN_vmdxenbl] = false; // Virtual PC - Enable Direct Execution
SMPDefsFlags[NN_vmcpuid] = false; // Virtual PC - Virtualized CPU Information
SMPDefsFlags[NN_vmhlt] = false; // Virtual PC - Halt
SMPDefsFlags[NN_vmsplaf] = false; // Virtual PC - Spin Lock Acquisition Failed
SMPDefsFlags[NN_vmpushfd] = false; // Virtual PC - Push virtualized flags register
SMPDefsFlags[NN_vmpopfd] = false; // Virtual PC - Pop virtualized flags register
SMPDefsFlags[NN_vmcli] = false; // Virtual PC - Clear Interrupt Flag
SMPDefsFlags[NN_vmsti] = false; // Virtual PC - Set Interrupt Flag
SMPDefsFlags[NN_vmiretd] = false; // Virtual PC - Return From Interrupt
SMPDefsFlags[NN_vmsgdt] = false; // Virtual PC - Store Global Descriptor Table
SMPDefsFlags[NN_vmsidt] = false; // Virtual PC - Store Interrupt Descriptor Table
SMPDefsFlags[NN_vmsldt] = false; // Virtual PC - Store Local Descriptor Table
SMPDefsFlags[NN_vmstr] = false; // Virtual PC - Store Task Register
SMPDefsFlags[NN_vmsdte] = false; // Virtual PC - Store to Descriptor Table Entry
SMPDefsFlags[NN_vpcext] = false; // Virtual PC - ISA extension
#endif // 599 < IDA_SDK_VERSION
SMPDefsFlags[NN_last] = false;
return;
} // end InitSMPDefsFlags()
// Initialize the SMPUsesFlags[] array to define how we emit
// optimizing annotations.
void InitSMPUsesFlags(void) {
// Default value is false. Few instructions use the flags.
(void) memset(SMPUsesFlags, false, sizeof(SMPUsesFlags));
SMPUsesFlags[NN_null] = true; // Unknown Operation
SMPUsesFlags[NN_aaa] = true; // ASCII adjust after addition
SMPUsesFlags[NN_aas] = true; // ASCII adjust after subtraction
SMPUsesFlags[NN_adc] = true; // Add with Carry
SMPUsesFlags[NN_cmps] = true; // Compare Strings (uses DF direction flag)
SMPUsesFlags[NN_daa] = true; // Decimal Adjust AL after Addition
SMPUsesFlags[NN_das] = true; // Decimal Adjust AL after Subtraction
SMPUsesFlags[NN_ins] = true; // Input Byte(s) from Port to String
SMPUsesFlags[NN_into] = true; // Call to Interrupt Procedure if Overflow Flag = 1
SMPUsesFlags[NN_ja] = true; // Jump if Above (CF=0 & ZF=0)
SMPUsesFlags[NN_jae] = true; // Jump if Above or Equal (CF=0)
SMPUsesFlags[NN_jb] = true; // Jump if Below (CF=1)
SMPUsesFlags[NN_jbe] = true; // Jump if Below or Equal (CF=1 | ZF=1)
SMPUsesFlags[NN_jc] = true; // Jump if Carry (CF=1)
SMPUsesFlags[NN_jcxz] = true; // Jump if CX is 0
SMPUsesFlags[NN_jecxz] = true; // Jump if ECX is 0
SMPUsesFlags[NN_jrcxz] = true; // Jump if RCX is 0
SMPUsesFlags[NN_je] = true; // Jump if Equal (ZF=1)
SMPUsesFlags[NN_jg] = true; // Jump if Greater (ZF=0 & SF=OF)
SMPUsesFlags[NN_jge] = true; // Jump if Greater or Equal (SF=OF)
SMPUsesFlags[NN_jl] = true; // Jump if Less (SF!=OF)
SMPUsesFlags[NN_jle] = true; // Jump if Less or Equal (ZF=1 | SF!=OF)
SMPUsesFlags[NN_jna] = true; // Jump if Not Above (CF=1 | ZF=1)
SMPUsesFlags[NN_jnae] = true; // Jump if Not Above or Equal (CF=1)
SMPUsesFlags[NN_jnb] = true; // Jump if Not Below (CF=0)
SMPUsesFlags[NN_jnbe] = true; // Jump if Not Below or Equal (CF=0 & ZF=0)
SMPUsesFlags[NN_jnc] = true; // Jump if Not Carry (CF=0)
SMPUsesFlags[NN_jne] = true; // Jump if Not Equal (ZF=0)
SMPUsesFlags[NN_jng] = true; // Jump if Not Greater (ZF=1 | SF!=OF)
SMPUsesFlags[NN_jnge] = true; // Jump if Not Greater or Equal (SF!=OF)
SMPUsesFlags[NN_jnl] = true; // Jump if Not Less (SF=OF)
SMPUsesFlags[NN_jnle] = true; // Jump if Not Less or Equal (ZF=0 & SF=OF)
SMPUsesFlags[NN_jno] = true; // Jump if Not Overflow (OF=0)
SMPUsesFlags[NN_jnp] = true; // Jump if Not Parity (PF=0)
SMPUsesFlags[NN_jns] = true; // Jump if Not Sign (SF=0)
SMPUsesFlags[NN_jnz] = true; // Jump if Not Zero (ZF=0)
SMPUsesFlags[NN_jo] = true; // Jump if Overflow (OF=1)
SMPUsesFlags[NN_jp] = true; // Jump if Parity (PF=1)
SMPUsesFlags[NN_jpe] = true; // Jump if Parity Even (PF=1)
SMPUsesFlags[NN_jpo] = true; // Jump if Parity Odd (PF=0)
SMPUsesFlags[NN_js] = true; // Jump if Sign (SF=1)
SMPUsesFlags[NN_jz] = true; // Jump if Zero (ZF=1)
SMPUsesFlags[NN_lahf] = true; // Load Flags into AH Register
SMPUsesFlags[NN_lods] = true; // Load String
SMPUsesFlags[NN_loopwe] = true; // Loop while CX != 0 and ZF=1
SMPUsesFlags[NN_loope] = true; // Loop while rCX != 0 and ZF=1
SMPUsesFlags[NN_loopde] = true; // Loop while ECX != 0 and ZF=1
SMPUsesFlags[NN_loopqe] = true; // Loop while RCX != 0 and ZF=1
SMPUsesFlags[NN_loopwne] = true; // Loop while CX != 0 and ZF=0
SMPUsesFlags[NN_loopne] = true; // Loop while rCX != 0 and ZF=0
SMPUsesFlags[NN_loopdne] = true; // Loop while ECX != 0 and ZF=0
SMPUsesFlags[NN_loopqne] = true; // Loop while RCX != 0 and ZF=0
SMPUsesFlags[NN_movs] = true; // Move String (uses flags if REP prefix)
SMPUsesFlags[NN_outs] = true; // Output Byte(s) to Port
SMPUsesFlags[NN_pushfw] = true; // Push Flags Register onto the Stack
SMPUsesFlags[NN_pushf] = true; // Push Flags Register onto the Stack
SMPUsesFlags[NN_pushfd] = true; // Push Flags Register onto the Stack (use32)
SMPUsesFlags[NN_pushfq] = true; // Push Flags Register onto the Stack (use64)
SMPUsesFlags[NN_rcl] = true; // Rotate Through Carry Left
SMPUsesFlags[NN_rcr] = true; // Rotate Through Carry Right
SMPUsesFlags[NN_repe] = true; // Repeat String Operation while ZF=1
SMPUsesFlags[NN_repne] = true; // Repeat String Operation while ZF=0
SMPUsesFlags[NN_sbb] = true; // Integer Subtraction with Borrow
SMPUsesFlags[NN_scas] = true; // Compare String (uses DF direction flag)
SMPUsesFlags[NN_seta] = true; // Set Byte if Above (CF=0 & ZF=0)
SMPUsesFlags[NN_setae] = true; // Set Byte if Above or Equal (CF=0)
SMPUsesFlags[NN_setb] = true; // Set Byte if Below (CF=1)
SMPUsesFlags[NN_setbe] = true; // Set Byte if Below or Equal (CF=1 | ZF=1)
SMPUsesFlags[NN_setc] = true; // Set Byte if Carry (CF=1)
SMPUsesFlags[NN_sete] = true; // Set Byte if Equal (ZF=1)
SMPUsesFlags[NN_setg] = true; // Set Byte if Greater (ZF=0 & SF=OF)
SMPUsesFlags[NN_setge] = true; // Set Byte if Greater or Equal (SF=OF)
SMPUsesFlags[NN_setl] = true; // Set Byte if Less (SF!=OF)
SMPUsesFlags[NN_setle] = true; // Set Byte if Less or Equal (ZF=1 | SF!=OF)
SMPUsesFlags[NN_setna] = true; // Set Byte if Not Above (CF=1 | ZF=1)
SMPUsesFlags[NN_setnae] = true; // Set Byte if Not Above or Equal (CF=1)
SMPUsesFlags[NN_setnb] = true; // Set Byte if Not Below (CF=0)
SMPUsesFlags[NN_setnbe] = true; // Set Byte if Not Below or Equal (CF=0 & ZF=0)
SMPUsesFlags[NN_setnc] = true; // Set Byte if Not Carry (CF=0)
SMPUsesFlags[NN_setne] = true; // Set Byte if Not Equal (ZF=0)
SMPUsesFlags[NN_setng] = true; // Set Byte if Not Greater (ZF=1 | SF!=OF)
SMPUsesFlags[NN_setnge] = true; // Set Byte if Not Greater or Equal (SF!=OF)
SMPUsesFlags[NN_setnl] = true; // Set Byte if Not Less (SF=OF)
SMPUsesFlags[NN_setnle] = true; // Set Byte if Not Less or Equal (ZF=0 & SF=OF)
SMPUsesFlags[NN_setno] = true; // Set Byte if Not Overflow (OF=0)
SMPUsesFlags[NN_setnp] = true; // Set Byte if Not Parity (PF=0)
SMPUsesFlags[NN_setns] = true; // Set Byte if Not Sign (SF=0)
SMPUsesFlags[NN_setnz] = true; // Set Byte if Not Zero (ZF=0)
SMPUsesFlags[NN_seto] = true; // Set Byte if Overflow (OF=1)
SMPUsesFlags[NN_setp] = true; // Set Byte if Parity (PF=1)
SMPUsesFlags[NN_setpe] = true; // Set Byte if Parity Even (PF=1)
SMPUsesFlags[NN_setpo] = true; // Set Byte if Parity Odd (PF=0)
SMPUsesFlags[NN_sets] = true; // Set Byte if Sign (SF=1)
SMPUsesFlags[NN_setz] = true; // Set Byte if Zero (ZF=1)
SMPUsesFlags[NN_stos] = true; // Store String
//
// 486 instructions
//
//
// Pentium instructions
//
#if 0
SMPUsesFlags[NN_cpuid] = true; // Get CPU ID
SMPUsesFlags[NN_cmpxchg8b] = true; // Compare and Exchange Eight Bytes
#endif
//
// Pentium Pro instructions
//
SMPUsesFlags[NN_cmova] = true; // Move if Above (CF=0 & ZF=0)
SMPUsesFlags[NN_cmovb] = true; // Move if Below (CF=1)
SMPUsesFlags[NN_cmovbe] = true; // Move if Below or Equal (CF=1 | ZF=1)
SMPUsesFlags[NN_cmovg] = true; // Move if Greater (ZF=0 & SF=OF)
SMPUsesFlags[NN_cmovge] = true; // Move if Greater or Equal (SF=OF)
SMPUsesFlags[NN_cmovl] = true; // Move if Less (SF!=OF)
SMPUsesFlags[NN_cmovle] = true; // Move if Less or Equal (ZF=1 | SF!=OF)
SMPUsesFlags[NN_cmovnb] = true; // Move if Not Below (CF=0)
SMPUsesFlags[NN_cmovno] = true; // Move if Not Overflow (OF=0)
SMPUsesFlags[NN_cmovnp] = true; // Move if Not Parity (PF=0)
SMPUsesFlags[NN_cmovns] = true; // Move if Not Sign (SF=0)
SMPUsesFlags[NN_cmovnz] = true; // Move if Not Zero (ZF=0)
SMPUsesFlags[NN_cmovo] = true; // Move if Overflow (OF=1)
SMPUsesFlags[NN_cmovp] = true; // Move if Parity (PF=1)
SMPUsesFlags[NN_cmovs] = true; // Move if Sign (SF=1)
SMPUsesFlags[NN_cmovz] = true; // Move if Zero (ZF=1)
SMPUsesFlags[NN_fcmovb] = true; // Floating Move if Below
SMPUsesFlags[NN_fcmove] = true; // Floating Move if Equal
SMPUsesFlags[NN_fcmovbe] = true; // Floating Move if Below or Equal
SMPUsesFlags[NN_fcmovu] = true; // Floating Move if Unordered
SMPUsesFlags[NN_fcmovnb] = true; // Floating Move if Not Below
SMPUsesFlags[NN_fcmovne] = true; // Floating Move if Not Equal
SMPUsesFlags[NN_fcmovnbe] = true; // Floating Move if Not Below or Equal
SMPUsesFlags[NN_fcmovnu] = true; // Floating Move if Not Unordered
//
// FPP instructions
//
//
// 80387 instructions
//
//
// Instructions added 28.02.96
//
SMPUsesFlags[NN_setalc] = true; // Set AL to Carry Flag
//
// MMX instructions
//
//
// Undocumented Deschutes processor instructions
//
// Pentium II instructions
// 3DNow! instructions
// Pentium III instructions
// Pentium III Pseudo instructions
// AMD K7 instructions
// Revisit AMD if we port to it.
// Undocumented FP instructions (thanks to norbert.juffa@adm.com)
// Pentium 4 instructions
// AMD syscall/sysret instructions NOTE: not AMD, found in Intel manual
// AMD64 instructions NOTE: not AMD, found in Intel manual
// New Pentium instructions (SSE3)
// Missing AMD64 instructions NOTE: also found in Intel manual
// SSE3 instructions
// SSSE3 instructions
// VMX instructions
// Added with x86-64
// Geode LX 3DNow! extensions
// SSE2 pseudoinstructions
// SSSE4.1 instructions
// SSSE4.2 instructions
// AMD SSE4a instructions
// xsave/xrstor instructions
// Intel Safer Mode Extensions (SMX)
// AMD-V Virtualization ISA Extension
// VMX+ instructions
// Intel Atom instructions
// Intel AES instructions
// Carryless multiplication
// Returns modified by operand size prefixes
// RDRAND support
// new GPR instructions
SMPUsesFlags[NN_adcx] = true; // Unsigned Integer Addition of Two Operands with Carry Flag
SMPUsesFlags[NN_adox] = true; // Unsigned Integer Addition of Two Operands with Overflow Flag
// new AVX instructions
// Transactional Synchronization Extensions
// Virtual PC synthetic instructions
SMPUsesFlags[NN_last] = false;
return;
} // end InitSMPUsesFlags()
// Initialize the SMPTypeCategory[] array to define how we infer
// numeric or pointer operand types for optimizing annotations.
void InitTypeCategory(void) {
// Default category is 0, no type inference without knowing context.
(void) memset(SMPTypeCategory, 0, sizeof(SMPTypeCategory));
// Category 1 instructions will need no mmStrata instrumentation
// and are irrelevant to our type system, so we do not attempt
// to make type inferences. Many of these operate on numeric
// operands such as floating point or MMX/SSE registers. mmStrata
// assumes that such registers are always numeric, so we do not
// need annotations informing mmStrata that FP/MMX/SSE regs are numeric.
// Category 2 instructions always have a result type of 'n' (number).
// Category 3 instructions have a result type of 'n' (number)
// whenever the second source operand is an operand of type 'n'.
// NOTE: MOV is the only current example, and this will take some thought if
// other examples arise.
// Category 4 instructions have a result type identical to the 1st source operand type.
// NOTE: This is currently set for single-operand instructions such as
// INC, DEC. As a result, these are treated pretty much as if
// they were category 1 instructions, as there is no metadata update,
// even if the operand is a memory operand.
// If new instructions are added to this category that are not single
// operand and do require some updating, the category should be split.
// Category 5 instructions have a result type identical to the 1st source operand
// type whenever the 2nd source operand is an operand of type 'n' & vice versa.
// Examples are add, sub, adc, and sbb. There are subtle exceptions
// handled in the SMPInstr::EmitTypeAnnotations() method.
// Category 6 instructions always have a result type of 'p' (pointer).
// Category 7 instructions are category 2 instructions with two destinations,
// such as multiply and divide instructions that affect EDX:EAX. There are
// forms of these instructions that only have one destination, so they have
// to be distinguished via the operand info.
// Category 8 instructions implicitly write a numeric value to EDX:EAX, but
// EDX and EAX are not listed as operands. RDTSC, RDPMC, RDMSR, and other
// instructions that copy machine registers into EDX:EAX are category 8.
// Some instructions in category 8 also write to ECX.
// Category 9 instructions are floating point instructions that either
// have a memory destination (treat as category 13) or a FP reg destination
// (treat as category 1, as FP regs are always 'n' and ignored in our system).
// Category 10 instructions have 'n' results if the sources are all 'n';
// we cannot infer the type of the result if the sources are of mixed types.
// Bitwise OR and AND and LEA (load effective address) are examples.
// Category 11 instructions need to have their types and locations on the stack
// frame tracked, e.g. push and pop instructions. No direct type inference.
// Category 12 instructions are similar to category 10, except that we do not
// output 'n' annotations when all sources are 'n'; rather, the instruction can
// be simply ignored (not instrumented by mmStrata) in that case. Conditional
// exchange instructions are examples; we do or do not
// move a numeric value into a register that already has numeric metadata.
// Category 13 instructions imply that their memory destination is 'n'.
// Category 14 instructions imply that their reg or memory source operand is 'n';
// if source is not memory, they are category 1 (inferences, but no instrumentation).
// There should never be a memory destination (usual destination is fpreg or flags).
// Category 15 instructions always have 'n' source AND destination operands;
// if addressed using indirect or indexed addressing, they are a subset of category 0
// (must be instrumented by mmStrata to keep index in bounds). Memory destinations
// are common in this category.
// NOTE: The Memory Monitor SDT needs just three categories, corresponding
// to categories 0, 1, and all others. For all categories > 1, the
// annotation should tell the SDT exactly how to update its metadata.
// For example, a division instruction will write type 'n' (NUM) as
// the metadata for result registers EDX:EAX. So, the annotation should
// list 'n', EDX, EAX, and a terminator of ZZ. CWD (convert word to
// doubleword) should have a list of n EAX ZZ.
SMPTypeCategory[NN_null] = 0; // Unknown Operation
SMPTypeCategory[NN_aaa] = 2; // ASCII Adjust after Addition
SMPTypeCategory[NN_aad] = 2; // ASCII Adjust AX before Division
SMPTypeCategory[NN_aam] = 2; // ASCII Adjust AX after Multiply
SMPTypeCategory[NN_aas] = 2; // ASCII Adjust AL after Subtraction
SMPTypeCategory[NN_adc] = 5; // Add with Carry
SMPTypeCategory[NN_add] = 5; // Add
SMPTypeCategory[NN_and] = 10; // Logical AND
SMPTypeCategory[NN_arpl] = 1; // Adjust RPL Field of Selector
SMPTypeCategory[NN_bound] = 1; // Check Array Index Against Bounds
SMPTypeCategory[NN_bsf] = 2; // Bit Scan Forward
SMPTypeCategory[NN_bsr] = 2; // Bit Scan Reverse
SMPTypeCategory[NN_bt] = 10; // Bit Test
SMPTypeCategory[NN_btc] = 10; // Bit Test and Complement
SMPTypeCategory[NN_btr] = 10; // Bit Test and Reset
SMPTypeCategory[NN_bts] = 10; // Bit Test and Set
SMPTypeCategory[NN_call] = 1; // Call Procedure
SMPTypeCategory[NN_callfi] = 1; // Indirect Call Far Procedure
SMPTypeCategory[NN_callni] = 1; // Indirect Call Near Procedure
SMPTypeCategory[NN_cbw] = 2; // AL -> AX (with sign) ** No ops?
SMPTypeCategory[NN_cwde] = 2; // AX -> EAX (with sign) **
SMPTypeCategory[NN_cdqe] = 2; // EAX -> RAX (with sign) **
SMPTypeCategory[NN_clc] = 1; // Clear Carry Flag
SMPTypeCategory[NN_cld] = 1; // Clear Direction Flag
SMPTypeCategory[NN_cli] = 1; // Clear Interrupt Flag
SMPTypeCategory[NN_clts] = 1; // Clear Task-Switched Flag in CR0
SMPTypeCategory[NN_cmc] = 1; // Complement Carry Flag
SMPTypeCategory[NN_cmp] = 1; // Compare Two Operands
SMPTypeCategory[NN_cmps] = 14; // Compare Strings
SMPTypeCategory[NN_cwd] = 2; // AX -> DX:AX (with sign)
SMPTypeCategory[NN_cdq] = 2; // EAX -> EDX:EAX (with sign)
SMPTypeCategory[NN_cqo] = 2; // RAX -> RDX:RAX (with sign)
SMPTypeCategory[NN_daa] = 2; // Decimal Adjust AL after Addition
SMPTypeCategory[NN_das] = 2; // Decimal Adjust AL after Subtraction
SMPTypeCategory[NN_dec] = 4; // Decrement by 1
SMPTypeCategory[NN_div] = 7; // Unsigned Divide
SMPTypeCategory[NN_enterw] = 0; // Make Stack Frame for Procedure Parameters **
SMPTypeCategory[NN_enter] = 0; // Make Stack Frame for Procedure Parameters **
SMPTypeCategory[NN_enterd] = 0; // Make Stack Frame for Procedure Parameters **
SMPTypeCategory[NN_enterq] = 0; // Make Stack Frame for Procedure Parameters **
SMPTypeCategory[NN_hlt] = 0; // Halt
SMPTypeCategory[NN_idiv] = 7; // Signed Divide
SMPTypeCategory[NN_imul] = 7; // Signed Multiply
SMPTypeCategory[NN_in] = 0; // Input from Port **
SMPTypeCategory[NN_inc] = 4; // Increment by 1
SMPTypeCategory[NN_ins] = 2; // Input Byte(s) from Port to String **
SMPTypeCategory[NN_int] = 0; // Call to Interrupt Procedure
SMPTypeCategory[NN_into] = 0; // Call to Interrupt Procedure if Overflow Flag = 1
SMPTypeCategory[NN_int3] = 0; // Trap to Debugger
SMPTypeCategory[NN_iretw] = 0; // Interrupt Return
SMPTypeCategory[NN_iret] = 0; // Interrupt Return
SMPTypeCategory[NN_iretd] = 0; // Interrupt Return (use32)
SMPTypeCategory[NN_iretq] = 0; // Interrupt Return (use64)
SMPTypeCategory[NN_ja] = 1; // Jump if Above (CF=0 & ZF=0)
SMPTypeCategory[NN_jae] = 1; // Jump if Above or Equal (CF=0)
SMPTypeCategory[NN_jb] = 1; // Jump if Below (CF=1)
SMPTypeCategory[NN_jbe] = 1; // Jump if Below or Equal (CF=1 | ZF=1)
SMPTypeCategory[NN_jc] = 1; // Jump if Carry (CF=1)
SMPTypeCategory[NN_jcxz] = 1; // Jump if CX is 0
SMPTypeCategory[NN_jecxz] = 1; // Jump if ECX is 0
SMPTypeCategory[NN_jrcxz] = 1; // Jump if RCX is 0
SMPTypeCategory[NN_je] = 1; // Jump if Equal (ZF=1)
SMPTypeCategory[NN_jg] = 1; // Jump if Greater (ZF=0 & SF=OF)
SMPTypeCategory[NN_jge] = 1; // Jump if Greater or Equal (SF=OF)
SMPTypeCategory[NN_jl] = 1; // Jump if Less (SF!=OF)
SMPTypeCategory[NN_jle] = 1; // Jump if Less or Equal (ZF=1 | SF!=OF)
SMPTypeCategory[NN_jna] = 1; // Jump if Not Above (CF=1 | ZF=1)
SMPTypeCategory[NN_jnae] = 1; // Jump if Not Above or Equal (CF=1)
SMPTypeCategory[NN_jnb] = 1; // Jump if Not Below (CF=0)
SMPTypeCategory[NN_jnbe] = 1; // Jump if Not Below or Equal (CF=0 & ZF=0)
SMPTypeCategory[NN_jnc] = 1; // Jump if Not Carry (CF=0)
SMPTypeCategory[NN_jne] = 1; // Jump if Not Equal (ZF=0)
SMPTypeCategory[NN_jng] = 1; // Jump if Not Greater (ZF=1 | SF!=OF)
SMPTypeCategory[NN_jnge] = 1; // Jump if Not Greater or Equal (SF!=OF)
SMPTypeCategory[NN_jnl] = 1; // Jump if Not Less (SF=OF)
SMPTypeCategory[NN_jnle] = 1; // Jump if Not Less or Equal (ZF=0 & SF=OF)
SMPTypeCategory[NN_jno] = 1; // Jump if Not Overflow (OF=0)
SMPTypeCategory[NN_jnp] = 1; // Jump if Not Parity (PF=0)
SMPTypeCategory[NN_jns] = 1; // Jump if Not Sign (SF=0)
SMPTypeCategory[NN_jnz] = 1; // Jump if Not Zero (ZF=0)
SMPTypeCategory[NN_jo] = 1; // Jump if Overflow (OF=1)
SMPTypeCategory[NN_jp] = 1; // Jump if Parity (PF=1)
SMPTypeCategory[NN_jpe] = 1; // Jump if Parity Even (PF=1)
SMPTypeCategory[NN_jpo] = 1; // Jump if Parity Odd (PF=0)
SMPTypeCategory[NN_js] = 1; // Jump if Sign (SF=1)
SMPTypeCategory[NN_jz] = 1; // Jump if Zero (ZF=1)
SMPTypeCategory[NN_jmp] = 1; // Jump
SMPTypeCategory[NN_jmpfi] = 1; // Indirect Far Jump
SMPTypeCategory[NN_jmpni] = 1; // Indirect Near Jump
SMPTypeCategory[NN_jmpshort] = 1; // Jump Short (not used)
SMPTypeCategory[NN_lahf] = 2; // Load Flags into AH Register
SMPTypeCategory[NN_lar] = 2; // Load Access Rights Byte
SMPTypeCategory[NN_lea] = 10; // Load Effective Address **
SMPTypeCategory[NN_leavew] = 0; // High Level Procedure Exit **
SMPTypeCategory[NN_leave] = 0; // High Level Procedure Exit **
SMPTypeCategory[NN_leaved] = 0; // High Level Procedure Exit **
SMPTypeCategory[NN_leaveq] = 0; // High Level Procedure Exit **
SMPTypeCategory[NN_lgdt] = 0; // Load Global Descriptor Table Register
SMPTypeCategory[NN_lidt] = 0; // Load Interrupt Descriptor Table Register
SMPTypeCategory[NN_lgs] = 6; // Load Full Pointer to GS:xx
SMPTypeCategory[NN_lss] = 6; // Load Full Pointer to SS:xx
SMPTypeCategory[NN_lds] = 6; // Load Full Pointer to DS:xx
SMPTypeCategory[NN_les] = 6; // Load Full Pointer to ES:xx
SMPTypeCategory[NN_lfs] = 6; // Load Full Pointer to FS:xx
SMPTypeCategory[NN_lldt] = 0; // Load Local Descriptor Table Register
SMPTypeCategory[NN_lmsw] = 1; // Load Machine Status Word
SMPTypeCategory[NN_lock] = 1; // Assert LOCK# Signal Prefix
SMPTypeCategory[NN_lods] = 0; // Load String
SMPTypeCategory[NN_loopw] = 1; // Loop while ECX != 0
SMPTypeCategory[NN_loop] = 1; // Loop while CX != 0
SMPTypeCategory[NN_loopd] = 1; // Loop while ECX != 0
SMPTypeCategory[NN_loopq] = 1; // Loop while RCX != 0
SMPTypeCategory[NN_loopwe] = 1; // Loop while CX != 0 and ZF=1
SMPTypeCategory[NN_loope] = 1; // Loop while rCX != 0 and ZF=1
SMPTypeCategory[NN_loopde] = 1; // Loop while ECX != 0 and ZF=1
SMPTypeCategory[NN_loopqe] = 1; // Loop while RCX != 0 and ZF=1
SMPTypeCategory[NN_loopwne] = 1; // Loop while CX != 0 and ZF=0
SMPTypeCategory[NN_loopne] = 1; // Loop while rCX != 0 and ZF=0
SMPTypeCategory[NN_loopdne] = 1; // Loop while ECX != 0 and ZF=0
SMPTypeCategory[NN_loopqne] = 1; // Loop while RCX != 0 and ZF=0
SMPTypeCategory[NN_lsl] = 6; // Load Segment Limit
SMPTypeCategory[NN_ltr] = 1; // Load Task Register
SMPTypeCategory[NN_mov] = 3; // Move Data
SMPTypeCategory[NN_movsp] = 3; // Move to/from Special Registers
SMPTypeCategory[NN_movs] = 0; // Move Byte(s) from String to String
SMPTypeCategory[NN_movsx] = 3; // Move with Sign-Extend
SMPTypeCategory[NN_movzx] = 3; // Move with Zero-Extend
SMPTypeCategory[NN_mul] = 7; // Unsigned Multiplication of AL or AX
SMPTypeCategory[NN_neg] = 2; // Two's Complement Negation !!!!****!!!! Change this when mmStrata handles NEGATEDPTR type.
SMPTypeCategory[NN_nop] = 1; // No Operation
SMPTypeCategory[NN_not] = 2; // One's Complement Negation
SMPTypeCategory[NN_or] = 10; // Logical Inclusive OR
SMPTypeCategory[NN_out] = 0; // Output to Port
SMPTypeCategory[NN_outs] = 0; // Output Byte(s) to Port
SMPTypeCategory[NN_pop] = 11; // Pop a word from the Stack
SMPTypeCategory[NN_popaw] = 11; // Pop all General Registers
SMPTypeCategory[NN_popa] = 11; // Pop all General Registers
SMPTypeCategory[NN_popad] = 11; // Pop all General Registers (use32)
SMPTypeCategory[NN_popaq] = 11; // Pop all General Registers (use64)
SMPTypeCategory[NN_popfw] = 11; // Pop Stack into Flags Register **
SMPTypeCategory[NN_popf] = 11; // Pop Stack into Flags Register **
SMPTypeCategory[NN_popfd] = 11; // Pop Stack into Eflags Register **
SMPTypeCategory[NN_popfq] = 11; // Pop Stack into Rflags Register **
SMPTypeCategory[NN_push] = 11; // Push Operand onto the Stack
SMPTypeCategory[NN_pushaw] = 11; // Push all General Registers
SMPTypeCategory[NN_pusha] = 11; // Push all General Registers
SMPTypeCategory[NN_pushad] = 11; // Push all General Registers (use32)
SMPTypeCategory[NN_pushaq] = 11; // Push all General Registers (use64)
SMPTypeCategory[NN_pushfw] = 11; // Push Flags Register onto the Stack
SMPTypeCategory[NN_pushf] = 11; // Push Flags Register onto the Stack
SMPTypeCategory[NN_pushfd] = 11; // Push Flags Register onto the Stack (use32)
SMPTypeCategory[NN_pushfq] = 11; // Push Flags Register onto the Stack (use64)
SMPTypeCategory[NN_rcl] = 2; // Rotate Through Carry Left
SMPTypeCategory[NN_rcr] = 2; // Rotate Through Carry Right
SMPTypeCategory[NN_rol] = 2; // Rotate Left
SMPTypeCategory[NN_ror] = 2; // Rotate Right
SMPTypeCategory[NN_rep] = 0; // Repeat String Operation
SMPTypeCategory[NN_repe] = 0; // Repeat String Operation while ZF=1
SMPTypeCategory[NN_repne] = 0; // Repeat String Operation while ZF=0
SMPTypeCategory[NN_retn] = 0; // Return Near from Procedure
SMPTypeCategory[NN_retf] = 0; // Return Far from Procedure
SMPTypeCategory[NN_sahf] = 14; // Store AH into Flags Register
SMPTypeCategory[NN_sal] = 2; // Shift Arithmetic Left
SMPTypeCategory[NN_sar] = 2; // Shift Arithmetic Right
SMPTypeCategory[NN_shl] = 2; // Shift Logical Left
SMPTypeCategory[NN_shr] = 2; // Shift Logical Right
SMPTypeCategory[NN_sbb] = 5; // Integer Subtraction with Borrow
SMPTypeCategory[NN_scas] = 14; // Compare String
SMPTypeCategory[NN_seta] = 2; // Set Byte if Above (CF=0 & ZF=0)
SMPTypeCategory[NN_setae] = 2; // Set Byte if Above or Equal (CF=0)
SMPTypeCategory[NN_setb] = 2; // Set Byte if Below (CF=1)
SMPTypeCategory[NN_setbe] = 2; // Set Byte if Below or Equal (CF=1 | ZF=1)
SMPTypeCategory[NN_setc] = 2; // Set Byte if Carry (CF=1)
SMPTypeCategory[NN_sete] = 2; // Set Byte if Equal (ZF=1)
SMPTypeCategory[NN_setg] = 2; // Set Byte if Greater (ZF=0 & SF=OF)
SMPTypeCategory[NN_setge] = 2; // Set Byte if Greater or Equal (SF=OF)
SMPTypeCategory[NN_setl] = 2; // Set Byte if Less (SF!=OF)
SMPTypeCategory[NN_setle] = 2; // Set Byte if Less or Equal (ZF=1 | SF!=OF)
SMPTypeCategory[NN_setna] = 2; // Set Byte if Not Above (CF=1 | ZF=1)
SMPTypeCategory[NN_setnae] = 2; // Set Byte if Not Above or Equal (CF=1)
SMPTypeCategory[NN_setnb] = 2; // Set Byte if Not Below (CF=0)
SMPTypeCategory[NN_setnbe] = 2; // Set Byte if Not Below or Equal (CF=0 & ZF=0)
SMPTypeCategory[NN_setnc] = 2; // Set Byte if Not Carry (CF=0)
SMPTypeCategory[NN_setne] = 2; // Set Byte if Not Equal (ZF=0)
SMPTypeCategory[NN_setng] = 2; // Set Byte if Not Greater (ZF=1 | SF!=OF)
SMPTypeCategory[NN_setnge] = 2; // Set Byte if Not Greater or Equal (SF!=OF)
SMPTypeCategory[NN_setnl] = 2; // Set Byte if Not Less (SF=OF)
SMPTypeCategory[NN_setnle] = 2; // Set Byte if Not Less or Equal (ZF=0 & SF=OF)
SMPTypeCategory[NN_setno] = 2; // Set Byte if Not Overflow (OF=0)
SMPTypeCategory[NN_setnp] = 2; // Set Byte if Not Parity (PF=0)
SMPTypeCategory[NN_setns] = 2; // Set Byte if Not Sign (SF=0)
SMPTypeCategory[NN_setnz] = 2; // Set Byte if Not Zero (ZF=0)
SMPTypeCategory[NN_seto] = 2; // Set Byte if Overflow (OF=1)
SMPTypeCategory[NN_setp] = 2; // Set Byte if Parity (PF=1)
SMPTypeCategory[NN_setpe] = 2; // Set Byte if Parity Even (PF=1)
SMPTypeCategory[NN_setpo] = 2; // Set Byte if Parity Odd (PF=0)
SMPTypeCategory[NN_sets] = 2; // Set Byte if Sign (SF=1)
SMPTypeCategory[NN_setz] = 2; // Set Byte if Zero (ZF=1)
SMPTypeCategory[NN_sgdt] = 0; // Store Global Descriptor Table Register
SMPTypeCategory[NN_sidt] = 0; // Store Interrupt Descriptor Table Register
SMPTypeCategory[NN_shld] = 2; // Double Precision Shift Left
SMPTypeCategory[NN_shrd] = 2; // Double Precision Shift Right
SMPTypeCategory[NN_sldt] = 6; // Store Local Descriptor Table Register
SMPTypeCategory[NN_smsw] = 2; // Store Machine Status Word
SMPTypeCategory[NN_stc] = 1; // Set Carry Flag
SMPTypeCategory[NN_std] = 1; // Set Direction Flag
SMPTypeCategory[NN_sti] = 1; // Set Interrupt Flag
SMPTypeCategory[NN_stos] = 0; // Store String
SMPTypeCategory[NN_str] = 6; // Store Task Register
SMPTypeCategory[NN_sub] = 5; // Integer Subtraction
SMPTypeCategory[NN_test] = 1; // Logical Compare
SMPTypeCategory[NN_verr] = 1; // Verify a Segment for Reading
SMPTypeCategory[NN_verw] = 1; // Verify a Segment for Writing
SMPTypeCategory[NN_wait] = 1; // Wait until BUSY# Pin is Inactive (HIGH)
SMPTypeCategory[NN_xchg] = 12; // Exchange Register/Memory with Register
SMPTypeCategory[NN_xlat] = 0; // Table Lookup Translation
SMPTypeCategory[NN_xor] = 2; // Logical Exclusive OR
//
// 486 instructions
//
SMPTypeCategory[NN_cmpxchg] = 12; // Compare and Exchange
SMPTypeCategory[NN_bswap] = 1; // Swap bytes in register
SMPTypeCategory[NN_xadd] = 12; // t<-dest; dest<-src+dest; src<-t
SMPTypeCategory[NN_invd] = 1; // Invalidate Data Cache
SMPTypeCategory[NN_wbinvd] = 1; // Invalidate Data Cache (write changes)
SMPTypeCategory[NN_invlpg] = 1; // Invalidate TLB entry
//
// Pentium instructions
//
SMPTypeCategory[NN_rdmsr] = 8; // Read Machine Status Register
SMPTypeCategory[NN_wrmsr] = 1; // Write Machine Status Register
SMPTypeCategory[NN_cpuid] = 8; // Get CPU ID
SMPTypeCategory[NN_cmpxchg8b] = 12; // Compare and Exchange Eight Bytes
SMPTypeCategory[NN_rdtsc] = 8; // Read Time Stamp Counter
SMPTypeCategory[NN_rsm] = 1; // Resume from System Management Mode
//
// Pentium Pro instructions
//
SMPTypeCategory[NN_cmova] = 0; // Move if Above (CF=0 & ZF=0)
SMPTypeCategory[NN_cmovb] = 0; // Move if Below (CF=1)
SMPTypeCategory[NN_cmovbe] = 0; // Move if Below or Equal (CF=1 | ZF=1)
SMPTypeCategory[NN_cmovg] = 0; // Move if Greater (ZF=0 & SF=OF)
SMPTypeCategory[NN_cmovge] = 0; // Move if Greater or Equal (SF=OF)
SMPTypeCategory[NN_cmovl] = 0; // Move if Less (SF!=OF)
SMPTypeCategory[NN_cmovle] = 0; // Move if Less or Equal (ZF=1 | SF!=OF)
SMPTypeCategory[NN_cmovnb] = 0; // Move if Not Below (CF=0)
SMPTypeCategory[NN_cmovno] = 0; // Move if Not Overflow (OF=0)
SMPTypeCategory[NN_cmovnp] = 0; // Move if Not Parity (PF=0)
SMPTypeCategory[NN_cmovns] = 0; // Move if Not Sign (SF=0)
SMPTypeCategory[NN_cmovnz] = 0; // Move if Not Zero (ZF=0)
SMPTypeCategory[NN_cmovo] = 0; // Move if Overflow (OF=1)
SMPTypeCategory[NN_cmovp] = 0; // Move if Parity (PF=1)
SMPTypeCategory[NN_cmovs] = 0; // Move if Sign (SF=1)
SMPTypeCategory[NN_cmovz] = 0; // Move if Zero (ZF=1)
SMPTypeCategory[NN_fcmovb] = 1; // Floating Move if Below
SMPTypeCategory[NN_fcmove] = 1; // Floating Move if Equal
SMPTypeCategory[NN_fcmovbe] = 1; // Floating Move if Below or Equal
SMPTypeCategory[NN_fcmovu] = 1; // Floating Move if Unordered
SMPTypeCategory[NN_fcmovnb] = 1; // Floating Move if Not Below
SMPTypeCategory[NN_fcmovne] = 1; // Floating Move if Not Equal
SMPTypeCategory[NN_fcmovnbe] = 1; // Floating Move if Not Below or Equal
SMPTypeCategory[NN_fcmovnu] = 1; // Floating Move if Not Unordered
SMPTypeCategory[NN_fcomi] = 1; // FP Compare, result in EFLAGS
SMPTypeCategory[NN_fucomi] = 1; // FP Unordered Compare, result in EFLAGS
SMPTypeCategory[NN_fcomip] = 1; // FP Compare, result in EFLAGS, pop stack
SMPTypeCategory[NN_fucomip] = 1; // FP Unordered Compare, result in EFLAGS, pop stack
SMPTypeCategory[NN_rdpmc] = 8; // Read Performance Monitor Counter
//
// FPP instructions
//
SMPTypeCategory[NN_fld] = 14; // Load Real ** Infer src is 'n'
SMPTypeCategory[NN_fst] = 9; // Store Real
SMPTypeCategory[NN_fstp] = 9; // Store Real and Pop
SMPTypeCategory[NN_fxch] = 1; // Exchange Registers
SMPTypeCategory[NN_fild] = 14; // Load Integer ** Infer src is 'n'
SMPTypeCategory[NN_fist] = 13; // Store Integer
SMPTypeCategory[NN_fistp] = 13; // Store Integer and Pop
SMPTypeCategory[NN_fbld] = 1; // Load BCD
SMPTypeCategory[NN_fbstp] = 13; // Store BCD and Pop
SMPTypeCategory[NN_fadd] = 14; // Add Real
SMPTypeCategory[NN_faddp] = 14; // Add Real and Pop
SMPTypeCategory[NN_fiadd] = 14; // Add Integer
SMPTypeCategory[NN_fsub] = 14; // Subtract Real
SMPTypeCategory[NN_fsubp] = 14; // Subtract Real and Pop
SMPTypeCategory[NN_fisub] = 14; // Subtract Integer
SMPTypeCategory[NN_fsubr] = 14; // Subtract Real Reversed
SMPTypeCategory[NN_fsubrp] = 14; // Subtract Real Reversed and Pop
SMPTypeCategory[NN_fisubr] = 14; // Subtract Integer Reversed
SMPTypeCategory[NN_fmul] = 14; // Multiply Real
SMPTypeCategory[NN_fmulp] = 14; // Multiply Real and Pop
SMPTypeCategory[NN_fimul] = 14; // Multiply Integer
SMPTypeCategory[NN_fdiv] = 14; // Divide Real
SMPTypeCategory[NN_fdivp] = 14; // Divide Real and Pop
SMPTypeCategory[NN_fidiv] = 14; // Divide Integer
SMPTypeCategory[NN_fdivr] = 14; // Divide Real Reversed
SMPTypeCategory[NN_fdivrp] = 14; // Divide Real Reversed and Pop
SMPTypeCategory[NN_fidivr] = 14; // Divide Integer Reversed
SMPTypeCategory[NN_fsqrt] = 1; // Square Root
SMPTypeCategory[NN_fscale] = 1; // Scale: st(0) <- st(0) * 2^st(1)
SMPTypeCategory[NN_fprem] = 1; // Partial Remainder
SMPTypeCategory[NN_frndint] = 1; // Round to Integer
SMPTypeCategory[NN_fxtract] = 1; // Extract exponent and significand
SMPTypeCategory[NN_fabs] = 1; // Absolute value
SMPTypeCategory[NN_fchs] = 1; // Change Sign
SMPTypeCategory[NN_fcom] = 1; // Compare Real
SMPTypeCategory[NN_fcomp] = 1; // Compare Real and Pop
SMPTypeCategory[NN_fcompp] = 1; // Compare Real and Pop Twice
SMPTypeCategory[NN_ficom] = 1; // Compare Integer
SMPTypeCategory[NN_ficomp] = 1; // Compare Integer and Pop
SMPTypeCategory[NN_ftst] = 1; // Test
SMPTypeCategory[NN_fxam] = 1; // Examine
SMPTypeCategory[NN_fptan] = 1; // Partial tangent
SMPTypeCategory[NN_fpatan] = 1; // Partial arctangent
SMPTypeCategory[NN_f2xm1] = 1; // 2^x - 1
SMPTypeCategory[NN_fyl2x] = 1; // Y * lg2(X)
SMPTypeCategory[NN_fyl2xp1] = 1; // Y * lg2(X+1)
SMPTypeCategory[NN_fldz] = 1; // Load +0.0
SMPTypeCategory[NN_fld1] = 1; // Load +1.0
SMPTypeCategory[NN_fldpi] = 1; // Load PI=3.14...
SMPTypeCategory[NN_fldl2t] = 1; // Load lg2(10)
SMPTypeCategory[NN_fldl2e] = 1; // Load lg2(e)
SMPTypeCategory[NN_fldlg2] = 1; // Load lg10(2)
SMPTypeCategory[NN_fldln2] = 1; // Load ln(2)
SMPTypeCategory[NN_finit] = 1; // Initialize Processor
SMPTypeCategory[NN_fninit] = 1; // Initialize Processor (no wait)
SMPTypeCategory[NN_fsetpm] = 1; // Set Protected Mode
SMPTypeCategory[NN_fldcw] = 14; // Load Control Word
SMPTypeCategory[NN_fstcw] = 13; // Store Control Word
SMPTypeCategory[NN_fnstcw] = 13; // Store Control Word (no wait)
SMPTypeCategory[NN_fstsw] = 2; // Store Status Word to memory or AX
SMPTypeCategory[NN_fnstsw] = 2; // Store Status Word (no wait) to memory or AX
SMPTypeCategory[NN_fclex] = 1; // Clear Exceptions
SMPTypeCategory[NN_fnclex] = 1; // Clear Exceptions (no wait)
SMPTypeCategory[NN_fstenv] = 13; // Store Environment
SMPTypeCategory[NN_fnstenv] = 13; // Store Environment (no wait)
SMPTypeCategory[NN_fldenv] = 14; // Load Environment
SMPTypeCategory[NN_fsave] = 13; // Save State
SMPTypeCategory[NN_fnsave] = 13; // Save State (no wait)
SMPTypeCategory[NN_frstor] = 14; // Restore State ** infer src is 'n'
SMPTypeCategory[NN_fincstp] = 1; // Increment Stack Pointer
SMPTypeCategory[NN_fdecstp] = 1; // Decrement Stack Pointer
SMPTypeCategory[NN_ffree] = 1; // Free Register
SMPTypeCategory[NN_fnop] = 1; // No Operation
SMPTypeCategory[NN_feni] = 1; // (8087 only)
SMPTypeCategory[NN_fneni] = 1; // (no wait) (8087 only)
SMPTypeCategory[NN_fdisi] = 1; // (8087 only)
SMPTypeCategory[NN_fndisi] = 1; // (no wait) (8087 only)
//
// 80387 instructions
//
SMPTypeCategory[NN_fprem1] = 1; // Partial Remainder ( < half )
SMPTypeCategory[NN_fsincos] = 1; // t<-cos(st); st<-sin(st); push t
SMPTypeCategory[NN_fsin] = 1; // Sine
SMPTypeCategory[NN_fcos] = 1; // Cosine
SMPTypeCategory[NN_fucom] = 1; // Compare Unordered Real
SMPTypeCategory[NN_fucomp] = 1; // Compare Unordered Real and Pop
SMPTypeCategory[NN_fucompp] = 1; // Compare Unordered Real and Pop Twice
//
// Instructions added 28.02.96
//
SMPTypeCategory[NN_setalc] = 2; // Set AL to Carry Flag **
SMPTypeCategory[NN_svdc] = 0; // Save Register and Descriptor
SMPTypeCategory[NN_rsdc] = 0; // Restore Register and Descriptor
SMPTypeCategory[NN_svldt] = 0; // Save LDTR and Descriptor
SMPTypeCategory[NN_rsldt] = 0; // Restore LDTR and Descriptor
SMPTypeCategory[NN_svts] = 1; // Save TR and Descriptor
SMPTypeCategory[NN_rsts] = 1; // Restore TR and Descriptor
SMPTypeCategory[NN_icebp] = 1; // ICE Break Point
SMPTypeCategory[NN_loadall] = 0; // Load the entire CPU state from ES:EDI ???
//
// MMX instructions
//
SMPTypeCategory[NN_emms] = 1; // Empty MMX state
SMPTypeCategory[NN_movd] = 15; // Move 32 bits
SMPTypeCategory[NN_movq] = 15; // Move 64 bits
SMPTypeCategory[NN_packsswb] = 14; // Pack with Signed Saturation (Word->Byte)
SMPTypeCategory[NN_packssdw] = 14; // Pack with Signed Saturation (Dword->Word)
SMPTypeCategory[NN_packuswb] = 14; // Pack with Unsigned Saturation (Word->Byte)
SMPTypeCategory[NN_paddb] = 14; // Packed Add Byte
SMPTypeCategory[NN_paddw] = 14; // Packed Add Word
SMPTypeCategory[NN_paddd] = 14; // Packed Add Dword
SMPTypeCategory[NN_paddsb] = 14; // Packed Add with Saturation (Byte)
SMPTypeCategory[NN_paddsw] = 14; // Packed Add with Saturation (Word)
SMPTypeCategory[NN_paddusb] = 14; // Packed Add Unsigned with Saturation (Byte)
SMPTypeCategory[NN_paddusw] = 14; // Packed Add Unsigned with Saturation (Word)
SMPTypeCategory[NN_pand] = 14; // Bitwise Logical And
SMPTypeCategory[NN_pandn] = 14; // Bitwise Logical And Not
SMPTypeCategory[NN_pcmpeqb] = 14; // Packed Compare for Equal (Byte)
SMPTypeCategory[NN_pcmpeqw] = 14; // Packed Compare for Equal (Word)
SMPTypeCategory[NN_pcmpeqd] = 14; // Packed Compare for Equal (Dword)
SMPTypeCategory[NN_pcmpgtb] = 14; // Packed Compare for Greater Than (Byte)
SMPTypeCategory[NN_pcmpgtw] = 14; // Packed Compare for Greater Than (Word)
SMPTypeCategory[NN_pcmpgtd] = 14; // Packed Compare for Greater Than (Dword)
SMPTypeCategory[NN_pmaddwd] = 14; // Packed Multiply and Add
SMPTypeCategory[NN_pmulhw] = 14; // Packed Multiply High
SMPTypeCategory[NN_pmullw] = 14; // Packed Multiply Low
SMPTypeCategory[NN_por] = 14; // Bitwise Logical Or
SMPTypeCategory[NN_psllw] = 14; // Packed Shift Left Logical (Word)
SMPTypeCategory[NN_pslld] = 14; // Packed Shift Left Logical (Dword)
SMPTypeCategory[NN_psllq] = 14; // Packed Shift Left Logical (Qword)
SMPTypeCategory[NN_psraw] = 14; // Packed Shift Right Arithmetic (Word)
SMPTypeCategory[NN_psrad] = 14; // Packed Shift Right Arithmetic (Dword)
SMPTypeCategory[NN_psrlw] = 14; // Packed Shift Right Logical (Word)
SMPTypeCategory[NN_psrld] = 14; // Packed Shift Right Logical (Dword)
SMPTypeCategory[NN_psrlq] = 14; // Packed Shift Right Logical (Qword)
SMPTypeCategory[NN_psubb] = 14; // Packed Subtract Byte
SMPTypeCategory[NN_psubw] = 14; // Packed Subtract Word
SMPTypeCategory[NN_psubd] = 14; // Packed Subtract Dword
SMPTypeCategory[NN_psubsb] = 14; // Packed Subtract with Saturation (Byte)
SMPTypeCategory[NN_psubsw] = 14; // Packed Subtract with Saturation (Word)
SMPTypeCategory[NN_psubusb] = 14; // Packed Subtract Unsigned with Saturation (Byte)
SMPTypeCategory[NN_psubusw] = 14; // Packed Subtract Unsigned with Saturation (Word)
SMPTypeCategory[NN_punpckhbw] = 14; // Unpack High Packed Data (Byte->Word)
SMPTypeCategory[NN_punpckhwd] = 14; // Unpack High Packed Data (Word->Dword)
SMPTypeCategory[NN_punpckhdq] = 14; // Unpack High Packed Data (Dword->Qword)
SMPTypeCategory[NN_punpcklbw] = 14; // Unpack Low Packed Data (Byte->Word)
SMPTypeCategory[NN_punpcklwd] = 14; // Unpack Low Packed Data (Word->Dword)
SMPTypeCategory[NN_punpckldq] = 14; // Unpack Low Packed Data (Dword->Qword)
SMPTypeCategory[NN_pxor] = 14; // Bitwise Logical Exclusive Or
//
// Undocumented Deschutes processor instructions
//
SMPTypeCategory[NN_fxsave] = 1; // Fast save FP context ** to where?
SMPTypeCategory[NN_fxrstor] = 1; // Fast restore FP context ** from where?
// Pentium II instructions
SMPTypeCategory[NN_sysenter] = 1; // Fast Transition to System Call Entry Point
SMPTypeCategory[NN_sysexit] = 1; // Fast Transition from System Call Entry Point
// 3DNow! instructions
SMPTypeCategory[NN_pavgusb] = 14; // Packed 8-bit Unsigned Integer Averaging
SMPTypeCategory[NN_pfadd] = 14; // Packed Floating-Point Addition
SMPTypeCategory[NN_pfsub] = 14; // Packed Floating-Point Subtraction
SMPTypeCategory[NN_pfsubr] = 14; // Packed Floating-Point Reverse Subtraction
SMPTypeCategory[NN_pfacc] = 14; // Packed Floating-Point Accumulate
SMPTypeCategory[NN_pfcmpge] = 14; // Packed Floating-Point Comparison, Greater or Equal
SMPTypeCategory[NN_pfcmpgt] = 14; // Packed Floating-Point Comparison, Greater
SMPTypeCategory[NN_pfcmpeq] = 14; // Packed Floating-Point Comparison, Equal
SMPTypeCategory[NN_pfmin] = 14; // Packed Floating-Point Minimum
SMPTypeCategory[NN_pfmax] = 14; // Packed Floating-Point Maximum
SMPTypeCategory[NN_pi2fd] = 14; // Packed 32-bit Integer to Floating-Point
SMPTypeCategory[NN_pf2id] = 14; // Packed Floating-Point to 32-bit Integer
SMPTypeCategory[NN_pfrcp] = 14; // Packed Floating-Point Reciprocal Approximation
SMPTypeCategory[NN_pfrsqrt] = 14; // Packed Floating-Point Reciprocal Square Root Approximation
SMPTypeCategory[NN_pfmul] = 14; // Packed Floating-Point Multiplication
SMPTypeCategory[NN_pfrcpit1] = 14; // Packed Floating-Point Reciprocal First Iteration Step
SMPTypeCategory[NN_pfrsqit1] = 14; // Packed Floating-Point Reciprocal Square Root First Iteration Step
SMPTypeCategory[NN_pfrcpit2] = 14; // Packed Floating-Point Reciprocal Second Iteration Step
SMPTypeCategory[NN_pmulhrw] = 14; // Packed Floating-Point 16-bit Integer Multiply with rounding
SMPTypeCategory[NN_femms] = 1; // Faster entry/exit of the MMX or floating-point state
SMPTypeCategory[NN_prefetch] = 1; // Prefetch at least a 32-byte line into L1 data cache
SMPTypeCategory[NN_prefetchw] = 1; // Prefetch processor cache line into L1 data cache (mark as modified)
// Pentium III instructions
SMPTypeCategory[NN_addps] = 14; // Packed Single-FP Add
SMPTypeCategory[NN_addss] = 14; // Scalar Single-FP Add
SMPTypeCategory[NN_andnps] = 14; // Bitwise Logical And Not for Single-FP
SMPTypeCategory[NN_andps] = 14; // Bitwise Logical And for Single-FP
SMPTypeCategory[NN_cmpps] = 14; // Packed Single-FP Compare
SMPTypeCategory[NN_cmpss] = 14; // Scalar Single-FP Compare
SMPTypeCategory[NN_comiss] = 14; // Scalar Ordered Single-FP Compare and Set EFLAGS
SMPTypeCategory[NN_cvtpi2ps] = 14; // Packed signed INT32 to Packed Single-FP conversion
SMPTypeCategory[NN_cvtps2pi] = 14; // Packed Single-FP to Packed INT32 conversion
SMPTypeCategory[NN_cvtsi2ss] = 14; // Scalar signed INT32 to Single-FP conversion
SMPTypeCategory[NN_cvtss2si] = 14; // Scalar Single-FP to signed INT32 conversion
SMPTypeCategory[NN_cvttps2pi] = 14; // Packed Single-FP to Packed INT32 conversion (truncate)
SMPTypeCategory[NN_cvttss2si] = 14; // Scalar Single-FP to signed INT32 conversion (truncate)
SMPTypeCategory[NN_divps] = 14; // Packed Single-FP Divide
SMPTypeCategory[NN_divss] = 14; // Scalar Single-FP Divide
SMPTypeCategory[NN_ldmxcsr] = 14; // Load Streaming SIMD Extensions Technology Control/Status Register
SMPTypeCategory[NN_maxps] = 14; // Packed Single-FP Maximum
SMPTypeCategory[NN_maxss] = 14; // Scalar Single-FP Maximum
SMPTypeCategory[NN_minps] = 14; // Packed Single-FP Minimum
SMPTypeCategory[NN_minss] = 14; // Scalar Single-FP Minimum
SMPTypeCategory[NN_movaps] = 15; // Move Aligned Four Packed Single-FP ** infer memsrc 'n'?
SMPTypeCategory[NN_movhlps] = 15; // Move High to Low Packed Single-FP
SMPTypeCategory[NN_movhps] = 15; // Move High Packed Single-FP
SMPTypeCategory[NN_movlhps] = 15; // Move Low to High Packed Single-FP
SMPTypeCategory[NN_movlps] = 15; // Move Low Packed Single-FP
SMPTypeCategory[NN_movmskps] = 15; // Move Mask to Register
SMPTypeCategory[NN_movss] = 15; // Move Scalar Single-FP
SMPTypeCategory[NN_movups] = 15; // Move Unaligned Four Packed Single-FP
SMPTypeCategory[NN_mulps] = 14; // Packed Single-FP Multiply
SMPTypeCategory[NN_mulss] = 14; // Scalar Single-FP Multiply
SMPTypeCategory[NN_orps] = 14; // Bitwise Logical OR for Single-FP Data
SMPTypeCategory[NN_rcpps] = 14; // Packed Single-FP Reciprocal
SMPTypeCategory[NN_rcpss] = 14; // Scalar Single-FP Reciprocal
SMPTypeCategory[NN_rsqrtps] = 14; // Packed Single-FP Square Root Reciprocal
SMPTypeCategory[NN_rsqrtss] = 14; // Scalar Single-FP Square Root Reciprocal
SMPTypeCategory[NN_shufps] = 14; // Shuffle Single-FP
SMPTypeCategory[NN_sqrtps] = 14; // Packed Single-FP Square Root
SMPTypeCategory[NN_sqrtss] = 14; // Scalar Single-FP Square Root
SMPTypeCategory[NN_stmxcsr] = 15; // Store Streaming SIMD Extensions Technology Control/Status Register ** Infer dest is 'n'
SMPTypeCategory[NN_subps] = 14; // Packed Single-FP Subtract
SMPTypeCategory[NN_subss] = 14; // Scalar Single-FP Subtract
SMPTypeCategory[NN_ucomiss] = 14; // Scalar Unordered Single-FP Compare and Set EFLAGS
SMPTypeCategory[NN_unpckhps] = 14; // Unpack High Packed Single-FP Data
SMPTypeCategory[NN_unpcklps] = 14; // Unpack Low Packed Single-FP Data
SMPTypeCategory[NN_xorps] = 14; // Bitwise Logical XOR for Single-FP Data
SMPTypeCategory[NN_pavgb] = 14; // Packed Average (Byte)
SMPTypeCategory[NN_pavgw] = 14; // Packed Average (Word)
SMPTypeCategory[NN_pextrw] = 15; // Extract Word
SMPTypeCategory[NN_pinsrw] = 14; // Insert Word
SMPTypeCategory[NN_pmaxsw] = 14; // Packed Signed Integer Word Maximum
SMPTypeCategory[NN_pmaxub] = 14; // Packed Unsigned Integer Byte Maximum
SMPTypeCategory[NN_pminsw] = 14; // Packed Signed Integer Word Minimum
SMPTypeCategory[NN_pminub] = 14; // Packed Unsigned Integer Byte Minimum
SMPTypeCategory[NN_pmovmskb] = 2; // Move Byte Mask to Integer
SMPTypeCategory[NN_pmulhuw] = 14; // Packed Multiply High Unsigned
SMPTypeCategory[NN_psadbw] = 14; // Packed Sum of Absolute Differences
SMPTypeCategory[NN_pshufw] = 14; // Packed Shuffle Word
SMPTypeCategory[NN_maskmovq] = 15; // Byte Mask write ** Infer dest is 'n'
SMPTypeCategory[NN_movntps] = 13; // Move Aligned Four Packed Single-FP Non Temporal * infer dest is 'n'
SMPTypeCategory[NN_movntq] = 13; // Move 64 Bits Non Temporal ** Infer dest is 'n'
SMPTypeCategory[NN_prefetcht0] = 1; // Prefetch to all cache levels
SMPTypeCategory[NN_prefetcht1] = 1; // Prefetch to all cache levels
SMPTypeCategory[NN_prefetcht2] = 1; // Prefetch to L2 cache
SMPTypeCategory[NN_prefetchnta] = 1; // Prefetch to L1 cache
SMPTypeCategory[NN_sfence] = 1; // Store Fence
// Pentium III Pseudo instructions
SMPTypeCategory[NN_cmpeqps] = 14; // Packed Single-FP Compare EQ
SMPTypeCategory[NN_cmpltps] = 14; // Packed Single-FP Compare LT
SMPTypeCategory[NN_cmpleps] = 14; // Packed Single-FP Compare LE
SMPTypeCategory[NN_cmpunordps] = 14; // Packed Single-FP Compare UNORD
SMPTypeCategory[NN_cmpneqps] = 14; // Packed Single-FP Compare NOT EQ
SMPTypeCategory[NN_cmpnltps] = 14; // Packed Single-FP Compare NOT LT
SMPTypeCategory[NN_cmpnleps] = 14; // Packed Single-FP Compare NOT LE
SMPTypeCategory[NN_cmpordps] = 14; // Packed Single-FP Compare ORDERED
SMPTypeCategory[NN_cmpeqss] = 14; // Scalar Single-FP Compare EQ
SMPTypeCategory[NN_cmpltss] = 14; // Scalar Single-FP Compare LT
SMPTypeCategory[NN_cmpless] = 14; // Scalar Single-FP Compare LE
SMPTypeCategory[NN_cmpunordss] = 14; // Scalar Single-FP Compare UNORD
SMPTypeCategory[NN_cmpneqss] = 14; // Scalar Single-FP Compare NOT EQ
SMPTypeCategory[NN_cmpnltss] = 14; // Scalar Single-FP Compare NOT LT
SMPTypeCategory[NN_cmpnless] = 14; // Scalar Single-FP Compare NOT LE
SMPTypeCategory[NN_cmpordss] = 14; // Scalar Single-FP Compare ORDERED
// AMD K7 instructions
// Revisit AMD if we port to it.
SMPTypeCategory[NN_pf2iw] = 15; // Packed Floating-Point to Integer with Sign Extend
SMPTypeCategory[NN_pfnacc] = 15; // Packed Floating-Point Negative Accumulate
SMPTypeCategory[NN_pfpnacc] = 15; // Packed Floating-Point Mixed Positive-Negative Accumulate
SMPTypeCategory[NN_pi2fw] = 15; // Packed 16-bit Integer to Floating-Point
SMPTypeCategory[NN_pswapd] = 15; // Packed Swap Double Word
// Undocumented FP instructions (thanks to norbert.juffa@adm.com)
SMPTypeCategory[NN_fstp1] = 9; // Alias of Store Real and Pop
SMPTypeCategory[NN_fcom2] = 1; // Alias of Compare Real
SMPTypeCategory[NN_fcomp3] = 1; // Alias of Compare Real and Pop
SMPTypeCategory[NN_fxch4] = 1; // Alias of Exchange Registers
SMPTypeCategory[NN_fcomp5] = 1; // Alias of Compare Real and Pop
SMPTypeCategory[NN_ffreep] = 1; // Free Register and Pop
SMPTypeCategory[NN_fxch7] = 1; // Alias of Exchange Registers
SMPTypeCategory[NN_fstp8] = 9; // Alias of Store Real and Pop
SMPTypeCategory[NN_fstp9] = 9; // Alias of Store Real and Pop
// Pentium 4 instructions
SMPTypeCategory[NN_addpd] = 14; // Add Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_addsd] = 14; // Add Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_andnpd] = 14; // Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_andpd] = 14; // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_clflush] = 1; // Flush Cache Line
SMPTypeCategory[NN_cmppd] = 14; // Compare Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_cmpsd] = 14; // Compare Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_comisd] = 14; // Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
SMPTypeCategory[NN_cvtdq2pd] = 14; // Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_cvtdq2ps] = 14; // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_cvtpd2dq] = 14; // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_cvtpd2pi] = 14; // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_cvtpd2ps] = 14; // Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_cvtpi2pd] = 14; // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_cvtps2dq] = 14; // Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_cvtps2pd] = 14; // Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_cvtsd2si] = 14; // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
SMPTypeCategory[NN_cvtsd2ss] = 14; // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
SMPTypeCategory[NN_cvtsi2sd] = 14; // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_cvtss2sd] = 14; // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_cvttpd2dq] = 14; // Convert With Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_cvttpd2pi] = 14; // Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_cvttps2dq] = 14; // Convert With Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_cvttsd2si] = 14; // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
SMPTypeCategory[NN_divpd] = 14; // Divide Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_divsd] = 14; // Divide Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_lfence] = 1; // Load Fence
SMPTypeCategory[NN_maskmovdqu] = 13; // Store Selected Bytes of Double Quadword ** Infer dest is 'n'
SMPTypeCategory[NN_maxpd] = 14; // Return Maximum Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_maxsd] = 14; // Return Maximum Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_mfence] = 1; // Memory Fence
SMPTypeCategory[NN_minpd] = 14; // Return Minimum Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_minsd] = 14; // Return Minimum Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_movapd] = 15; // Move Aligned Packed Double-Precision Floating-Point Values ** Infer dest is 'n'
SMPTypeCategory[NN_movdq2q] = 15; // Move Quadword from XMM to MMX Register
SMPTypeCategory[NN_movdqa] = 15; // Move Aligned Double Quadword ** Infer dest is 'n'
SMPTypeCategory[NN_movdqu] = 15; // Move Unaligned Double Quadword ** Infer dest is 'n'
SMPTypeCategory[NN_movhpd] = 15; // Move High Packed Double-Precision Floating-Point Values ** Infer dest is 'n'
SMPTypeCategory[NN_movlpd] = 15; // Move Low Packed Double-Precision Floating-Point Values ** Infer dest is 'n'
SMPTypeCategory[NN_movmskpd] = 15; // Extract Packed Double-Precision Floating-Point Sign Mask
SMPTypeCategory[NN_movntdq] = 13; // Store Double Quadword Using Non-Temporal Hint
SMPTypeCategory[NN_movnti] = 13; // Store Doubleword Using Non-Temporal Hint
SMPTypeCategory[NN_movntpd] = 13; // Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
SMPTypeCategory[NN_movq2dq] = 1; // Move Quadword from MMX to XMM Register
SMPTypeCategory[NN_movsd] = 15; // Move Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_movupd] = 15; // Move Unaligned Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_mulpd] = 14; // Multiply Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_mulsd] = 14; // Multiply Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_orpd] = 14; // Bitwise Logical OR of Double-Precision Floating-Point Values
SMPTypeCategory[NN_paddq] = 14; // Add Packed Quadword Integers
SMPTypeCategory[NN_pause] = 1; // Spin Loop Hint
SMPTypeCategory[NN_pmuludq] = 14; // Multiply Packed Unsigned Doubleword Integers
SMPTypeCategory[NN_pshufd] = 14; // Shuffle Packed Doublewords
SMPTypeCategory[NN_pshufhw] = 14; // Shuffle Packed High Words
SMPTypeCategory[NN_pshuflw] = 14; // Shuffle Packed Low Words
SMPTypeCategory[NN_pslldq] = 14; // Shift Double Quadword Left Logical
SMPTypeCategory[NN_psrldq] = 14; // Shift Double Quadword Right Logical
SMPTypeCategory[NN_psubq] = 14; // Subtract Packed Quadword Integers
SMPTypeCategory[NN_punpckhqdq] = 14; // Unpack High Data
SMPTypeCategory[NN_punpcklqdq] = 14; // Unpack Low Data
SMPTypeCategory[NN_shufpd] = 14; // Shuffle Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_sqrtpd] = 1; // Compute Square Roots of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_sqrtsd] = 14; // Compute Square Rootof Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_subpd] = 14; // Subtract Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_subsd] = 14; // Subtract Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_ucomisd] = 14; // Unordered Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
SMPTypeCategory[NN_unpckhpd] = 14; // Unpack and Interleave High Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_unpcklpd] = 14; // Unpack and Interleave Low Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_xorpd] = 14; // Bitwise Logical OR of Double-Precision Floating-Point Values
// AMD syscall/sysret instructions NOTE: not AMD, found in Intel manual
SMPTypeCategory[NN_syscall] = 1; // Low latency system call
SMPTypeCategory[NN_sysret] = 1; // Return from system call
// AMD64 instructions NOTE: not AMD, found in Intel manual
SMPTypeCategory[NN_swapgs] = 1; // Exchange GS base with KernelGSBase MSR
// New Pentium instructions (SSE3)
SMPTypeCategory[NN_movddup] = 14; // Move One Double-FP and Duplicate
SMPTypeCategory[NN_movshdup] = 14; // Move Packed Single-FP High and Duplicate
SMPTypeCategory[NN_movsldup] = 14; // Move Packed Single-FP Low and Duplicate
// Missing AMD64 instructions NOTE: also found in Intel manual
SMPTypeCategory[NN_movsxd] = 2; // Move with Sign-Extend Doubleword
SMPTypeCategory[NN_cmpxchg16b] = 0; // Compare and Exchange 16 Bytes
// SSE3 instructions
SMPTypeCategory[NN_addsubpd] = 14; // Add /Sub packed DP FP numbers
SMPTypeCategory[NN_addsubps] = 14; // Add /Sub packed SP FP numbers
SMPTypeCategory[NN_haddpd] = 14; // Add horizontally packed DP FP numbers
SMPTypeCategory[NN_haddps] = 14; // Add horizontally packed SP FP numbers
SMPTypeCategory[NN_hsubpd] = 14; // Sub horizontally packed DP FP numbers
SMPTypeCategory[NN_hsubps] = 14; // Sub horizontally packed SP FP numbers
SMPTypeCategory[NN_monitor] = 1; // Set up a linear address range to be monitored by hardware
SMPTypeCategory[NN_mwait] = 1; // Wait until write-back store performed within the range specified by the MONITOR instruction
SMPTypeCategory[NN_fisttp] = 13; // Store ST in intXX (chop) and pop
SMPTypeCategory[NN_lddqu] = 14; // Load unaligned integer 128-bit
// SSSE3 instructions
SMPTypeCategory[NN_psignb] = 14; // Packed SIGN Byte
SMPTypeCategory[NN_psignw] = 14; // Packed SIGN Word
SMPTypeCategory[NN_psignd] = 14; // Packed SIGN Doubleword
SMPTypeCategory[NN_pshufb] = 14; // Packed Shuffle Bytes
SMPTypeCategory[NN_pmulhrsw] = 14; // Packed Multiply High with Round and Scale
SMPTypeCategory[NN_pmaddubsw] = 14; // Multiply and Add Packed Signed and Unsigned Bytes
SMPTypeCategory[NN_phsubsw] = 14; // Packed Horizontal Subtract and Saturate
SMPTypeCategory[NN_phaddsw] = 14; // Packed Horizontal Add and Saturate
SMPTypeCategory[NN_phaddw] = 14; // Packed Horizontal Add Word
SMPTypeCategory[NN_phaddd] = 14; // Packed Horizontal Add Doubleword
SMPTypeCategory[NN_phsubw] = 14; // Packed Horizontal Subtract Word
SMPTypeCategory[NN_phsubd] = 14; // Packed Horizontal Subtract Doubleword
SMPTypeCategory[NN_palignr] = 15; // Packed Align Right
SMPTypeCategory[NN_pabsb] = 14; // Packed Absolute Value Byte
SMPTypeCategory[NN_pabsw] = 14; // Packed Absolute Value Word
SMPTypeCategory[NN_pabsd] = 14; // Packed Absolute Value Doubleword
// VMX instructions
SMPTypeCategory[NN_vmcall] = 1; // Call to VM Monitor
SMPTypeCategory[NN_vmclear] = 0; // Clear Virtual Machine Control Structure
SMPTypeCategory[NN_vmlaunch] = 1; // Launch Virtual Machine
SMPTypeCategory[NN_vmresume] = 1; // Resume Virtual Machine
SMPTypeCategory[NN_vmptrld] = 6; // Load Pointer to Virtual Machine Control Structure
SMPTypeCategory[NN_vmptrst] = 0; // Store Pointer to Virtual Machine Control Structure
SMPTypeCategory[NN_vmread] = 0; // Read Field from Virtual Machine Control Structure
SMPTypeCategory[NN_vmwrite] = 0; // Write Field from Virtual Machine Control Structure
SMPTypeCategory[NN_vmxoff] = 1; // Leave VMX Operation
SMPTypeCategory[NN_vmxon] = 1; // Enter VMX Operation
#if 599 < IDA_SDK_VERSION
SMPTypeCategory[NN_ud2] = 1; // Undefined Instruction
// Added with x86-64
SMPTypeCategory[NN_rdtscp] = 8; // Read Time-Stamp Counter and Processor ID
// Geode LX 3DNow! extensions
SMPTypeCategory[NN_pfrcpv] = 1; // Reciprocal Approximation for a Pair of 32-bit Floats
SMPTypeCategory[NN_pfrsqrtv] = 1; // Reciprocal Square Root Approximation for a Pair of 32-bit Floats
// SSE2 pseudoinstructions
SMPTypeCategory[NN_cmpeqpd] = 1; // Packed Double-FP Compare EQ
SMPTypeCategory[NN_cmpltpd] = 1; // Packed Double-FP Compare LT
SMPTypeCategory[NN_cmplepd] = 1; // Packed Double-FP Compare LE
SMPTypeCategory[NN_cmpunordpd] = 1; // Packed Double-FP Compare UNORD
SMPTypeCategory[NN_cmpneqpd] = 1; // Packed Double-FP Compare NOT EQ
SMPTypeCategory[NN_cmpnltpd] = 1; // Packed Double-FP Compare NOT LT
SMPTypeCategory[NN_cmpnlepd] = 1; // Packed Double-FP Compare NOT LE
SMPTypeCategory[NN_cmpordpd] = 1; // Packed Double-FP Compare ORDERED
SMPTypeCategory[NN_cmpeqsd] = 1; // Scalar Double-FP Compare EQ
SMPTypeCategory[NN_cmpltsd] = 1; // Scalar Double-FP Compare LT
SMPTypeCategory[NN_cmplesd] = 1; // Scalar Double-FP Compare LE
SMPTypeCategory[NN_cmpunordsd] = 1; // Scalar Double-FP Compare UNORD
SMPTypeCategory[NN_cmpneqsd] = 1; // Scalar Double-FP Compare NOT EQ
SMPTypeCategory[NN_cmpnltsd] = 1; // Scalar Double-FP Compare NOT LT
SMPTypeCategory[NN_cmpnlesd] = 1; // Scalar Double-FP Compare NOT LE
SMPTypeCategory[NN_cmpordsd] = 1; // Scalar Double-FP Compare ORDERED
// SSSE4.1 instructions
SMPTypeCategory[NN_blendpd] = 14; // Blend Packed Double Precision Floating-Point Values
SMPTypeCategory[NN_blendps] = 14; // Blend Packed Single Precision Floating-Point Values
SMPTypeCategory[NN_blendvpd] = 14; // Variable Blend Packed Double Precision Floating-Point Values
SMPTypeCategory[NN_blendvps] = 14; // Variable Blend Packed Single Precision Floating-Point Values
SMPTypeCategory[NN_dppd] = 14; // Dot Product of Packed Double Precision Floating-Point Values
SMPTypeCategory[NN_dpps] = 14; // Dot Product of Packed Single Precision Floating-Point Values
SMPTypeCategory[NN_extractps] = 15; // Extract Packed Single Precision Floating-Point Value
SMPTypeCategory[NN_insertps] = 14; // Insert Packed Single Precision Floating-Point Value
SMPTypeCategory[NN_movntdqa] = 0; // Load Double Quadword Non-Temporal Aligned Hint
SMPTypeCategory[NN_mpsadbw] = 1; // Compute Multiple Packed Sums of Absolute Difference
SMPTypeCategory[NN_packusdw] = 14; // Pack with Unsigned Saturation
SMPTypeCategory[NN_pblendvb] = 14; // Variable Blend Packed Bytes
SMPTypeCategory[NN_pblendw] = 14; // Blend Packed Words
SMPTypeCategory[NN_pcmpeqq] = 14; // Compare Packed Qword Data for Equal
SMPTypeCategory[NN_pextrb] = 15; // Extract Byte
SMPTypeCategory[NN_pextrd] = 15; // Extract Dword
SMPTypeCategory[NN_pextrq] = 15; // Extract Qword
SMPTypeCategory[NN_phminposuw] = 14; // Packed Horizontal Word Minimum
SMPTypeCategory[NN_pinsrb] = 14; // Insert Byte !!! Could this be used as a generic move???
SMPTypeCategory[NN_pinsrd] = 14; // Insert Dword !!! Could this be used as a generic move???
SMPTypeCategory[NN_pinsrq] = 14; // Insert Qword !!! Could this be used as a generic move???
SMPTypeCategory[NN_pmaxsb] = 14; // Maximum of Packed Signed Byte Integers
SMPTypeCategory[NN_pmaxsd] = 14; // Maximum of Packed Signed Dword Integers
SMPTypeCategory[NN_pmaxud] = 14; // Maximum of Packed Unsigned Dword Integers
SMPTypeCategory[NN_pmaxuw] = 14; // Maximum of Packed Word Integers
SMPTypeCategory[NN_pminsb] = 14; // Minimum of Packed Signed Byte Integers
SMPTypeCategory[NN_pminsd] = 14; // Minimum of Packed Signed Dword Integers
SMPTypeCategory[NN_pminud] = 14; // Minimum of Packed Unsigned Dword Integers
SMPTypeCategory[NN_pminuw] = 14; // Minimum of Packed Word Integers
SMPTypeCategory[NN_pmovsxbw] = 14; // Packed Move with Sign Extend
SMPTypeCategory[NN_pmovsxbd] = 14; // Packed Move with Sign Extend
SMPTypeCategory[NN_pmovsxbq] = 14; // Packed Move with Sign Extend
SMPTypeCategory[NN_pmovsxwd] = 14; // Packed Move with Sign Extend
SMPTypeCategory[NN_pmovsxwq] = 14; // Packed Move with Sign Extend
SMPTypeCategory[NN_pmovsxdq] = 14; // Packed Move with Sign Extend
SMPTypeCategory[NN_pmovzxbw] = 14; // Packed Move with Zero Extend
SMPTypeCategory[NN_pmovzxbd] = 14; // Packed Move with Zero Extend
SMPTypeCategory[NN_pmovzxbq] = 14; // Packed Move with Zero Extend
SMPTypeCategory[NN_pmovzxwd] = 14; // Packed Move with Zero Extend
SMPTypeCategory[NN_pmovzxwq] = 14; // Packed Move with Zero Extend
SMPTypeCategory[NN_pmovzxdq] = 14; // Packed Move with Zero Extend
SMPTypeCategory[NN_pmuldq] = 14; // Multiply Packed Signed Dword Integers
SMPTypeCategory[NN_pmulld] = 14; // Multiply Packed Signed Dword Integers and Store Low Result
SMPTypeCategory[NN_ptest] = 1; // Logical Compare
SMPTypeCategory[NN_roundpd] = 14; // Round Packed Double Precision Floating-Point Values
SMPTypeCategory[NN_roundps] = 14; // Round Packed Single Precision Floating-Point Values
SMPTypeCategory[NN_roundsd] = 14; // Round Scalar Double Precision Floating-Point Values
SMPTypeCategory[NN_roundss] = 14; // Round Scalar Single Precision Floating-Point Values
// SSSE4.2 instructions
SMPTypeCategory[NN_crc32] = 14; // Accumulate CRC32 Value
SMPTypeCategory[NN_pcmpestri] = 2; // Packed Compare Explicit Length Strings, Return Index
SMPTypeCategory[NN_pcmpestrm] = 2; // Packed Compare Explicit Length Strings, Return Mask
SMPTypeCategory[NN_pcmpistri] = 2; // Packed Compare Implicit Length Strings, Return Index
SMPTypeCategory[NN_pcmpistrm] = 2; // Packed Compare Implicit Length Strings, Return Mask
SMPTypeCategory[NN_pcmpgtq] = 14; // Compare Packed Data for Greater Than
SMPTypeCategory[NN_popcnt] = 2; // Return the Count of Number of Bits Set to 1
// AMD SSE4a instructions
SMPTypeCategory[NN_extrq] = 1; // Extract Field From Register
SMPTypeCategory[NN_insertq] = 1; // Insert Field
SMPTypeCategory[NN_movntsd] = 13; // Move Non-Temporal Scalar Double-Precision Floating-Point !!! Could this be used as a generic move???
SMPTypeCategory[NN_movntss] = 13; // Move Non-Temporal Scalar Single-Precision Floating-Point !!! Could this be used as a generic move???
SMPTypeCategory[NN_lzcnt] = 2; // Leading Zero Count
// xsave/xrstor instructions
SMPTypeCategory[NN_xgetbv] = 8; // Get Value of Extended Control Register
SMPTypeCategory[NN_xrstor] = 0; // Restore Processor Extended States
SMPTypeCategory[NN_xsave] = 1; // Save Processor Extended States
SMPTypeCategory[NN_xsetbv] = 1; // Set Value of Extended Control Register
// Intel Safer Mode Extensions (SMX)
SMPTypeCategory[NN_getsec] = 1; // Safer Mode Extensions (SMX) Instruction
// AMD-V Virtualization ISA Extension
SMPTypeCategory[NN_clgi] = 0; // Clear Global Interrupt Flag
SMPTypeCategory[NN_invlpga] = 1; // Invalidate TLB Entry in a Specified ASID
SMPTypeCategory[NN_skinit] = 1; // Secure Init and Jump with Attestation
SMPTypeCategory[NN_stgi] = 0; // Set Global Interrupt Flag
SMPTypeCategory[NN_vmexit] = 1; // Stop Executing Guest, Begin Executing Host
SMPTypeCategory[NN_vmload] = 0; // Load State from VMCB
SMPTypeCategory[NN_vmmcall] = 1; // Call VMM
SMPTypeCategory[NN_vmrun] = 1; // Run Virtual Machine
SMPTypeCategory[NN_vmsave] = 0; // Save State to VMCB
// VMX+ instructions
SMPTypeCategory[NN_invept] = 1; // Invalidate Translations Derived from EPT
SMPTypeCategory[NN_invvpid] = 1; // Invalidate Translations Based on VPID
// Intel Atom instructions
// !!!! continue work here
SMPTypeCategory[NN_movbe] = 3; // Move Data After Swapping Bytes
// Intel AES instructions
SMPTypeCategory[NN_aesenc] = 14; // Perform One Round of an AES Encryption Flow
SMPTypeCategory[NN_aesenclast] = 14; // Perform the Last Round of an AES Encryption Flow
SMPTypeCategory[NN_aesdec] = 14; // Perform One Round of an AES Decryption Flow
SMPTypeCategory[NN_aesdeclast] = 14; // Perform the Last Round of an AES Decryption Flow
SMPTypeCategory[NN_aesimc] = 14; // Perform the AES InvMixColumn Transformation
SMPTypeCategory[NN_aeskeygenassist] = 14; // AES Round Key Generation Assist
// Carryless multiplication
SMPTypeCategory[NN_pclmulqdq] = 14; // Carry-Less Multiplication Quadword
// Returns modified by operand size prefixes
SMPTypeCategory[NN_retnw] = 0; // Return Near from Procedure (use16)
SMPTypeCategory[NN_retnd] = 0; // Return Near from Procedure (use32)
SMPTypeCategory[NN_retnq] = 0; // Return Near from Procedure (use64)
SMPTypeCategory[NN_retfw] = 0; // Return Far from Procedure (use16)
SMPTypeCategory[NN_retfd] = 0; // Return Far from Procedure (use32)
SMPTypeCategory[NN_retfq] = 0; // Return Far from Procedure (use64)
// RDRAND support
SMPTypeCategory[NN_rdrand] = 2; // Read Random Number
// new GPR instructions
SMPTypeCategory[NN_adcx] = 5; // Unsigned Integer Addition of Two Operands with Carry Flag
SMPTypeCategory[NN_adox] = 5; // Unsigned Integer Addition of Two Operands with Overflow Flag
SMPTypeCategory[NN_andn] = 10; // Logical AND NOT
SMPTypeCategory[NN_bextr] = 14; // Bit Field Extract
SMPTypeCategory[NN_blsi] = 14; // Extract Lowest Set Isolated Bit
SMPTypeCategory[NN_blsmsk] = 2; // Get Mask Up to Lowest Set Bit
SMPTypeCategory[NN_blsr] = 2; // Reset Lowest Set Bit
SMPTypeCategory[NN_bzhi] = 2; // Zero High Bits Starting with Specified Bit Position
SMPTypeCategory[NN_clac] = 1; // Clear AC Flag in EFLAGS Register
SMPTypeCategory[NN_mulx] = 2; // Unsigned Multiply Without Affecting Flags
SMPTypeCategory[NN_pdep] = 2; // Parallel Bits Deposit
SMPTypeCategory[NN_pext] = 2; // Parallel Bits Extract
SMPTypeCategory[NN_rorx] = 2; // Rotate Right Logical Without Affecting Flags
SMPTypeCategory[NN_sarx] = 2; // Shift Arithmetically Right Without Affecting Flags
SMPTypeCategory[NN_shlx] = 2; // Shift Logically Left Without Affecting Flags
SMPTypeCategory[NN_shrx] = 2; // Shift Logically Right Without Affecting Flags
SMPTypeCategory[NN_stac] = 1; // Set AC Flag in EFLAGS Register
SMPTypeCategory[NN_tzcnt] = 2; // Count the Number of Trailing Zero Bits
SMPTypeCategory[NN_xsaveopt] = 1; // Save Processor Extended States Optimized
SMPTypeCategory[NN_invpcid] = 1; // Invalidate Processor Context ID
SMPTypeCategory[NN_rdseed] = 2; // Read Random Seed
SMPTypeCategory[NN_rdfsbase] = 6; // Read FS Segment Base
SMPTypeCategory[NN_rdgsbase] = 6; // Read GS Segment Base
SMPTypeCategory[NN_wrfsbase] = 6; // Write FS Segment Base
SMPTypeCategory[NN_wrgsbase] = 6; // Write GS Segment Base
// new AVX instructions
SMPTypeCategory[NN_vaddpd] = 14; // Add Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vaddps] = 14; // Packed Single-FP Add
SMPTypeCategory[NN_vaddsd] = 14; // Add Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vaddss] = 14; // Scalar Single-FP Add
SMPTypeCategory[NN_vaddsubpd] = 14; // Add /Sub packed DP FP numbers
SMPTypeCategory[NN_vaddsubps] = 14; // Add /Sub packed SP FP numbers
SMPTypeCategory[NN_vaesdec] = 14; // Perform One Round of an AES Decryption Flow
SMPTypeCategory[NN_vaesdeclast] = 14; // Perform the Last Round of an AES Decryption Flow
SMPTypeCategory[NN_vaesenc] = 14; // Perform One Round of an AES Encryption Flow
SMPTypeCategory[NN_vaesenclast] = 14; // Perform the Last Round of an AES Encryption Flow
SMPTypeCategory[NN_vaesimc] = 14; // Perform the AES InvMixColumn Transformation
SMPTypeCategory[NN_vaeskeygenassist] = 14; // AES Round Key Generation Assist
SMPTypeCategory[NN_vandnpd] = 14; // Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vandnps] = 14; // Bitwise Logical And Not for Single-FP
SMPTypeCategory[NN_vandpd] = 14; // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vandps] = 14; // Bitwise Logical And for Single-FP
SMPTypeCategory[NN_vblendpd] = 14; // Blend Packed Double Precision Floating-Point Values
SMPTypeCategory[NN_vblendps] = 14; // Blend Packed Single Precision Floating-Point Values
SMPTypeCategory[NN_vblendvpd] = 14; // Variable Blend Packed Double Precision Floating-Point Values
SMPTypeCategory[NN_vblendvps] = 14; // Variable Blend Packed Single Precision Floating-Point Values
SMPTypeCategory[NN_vbroadcastf128] = 14; // Broadcast 128 Bits of Floating-Point Data
SMPTypeCategory[NN_vbroadcasti128] = 14; // Broadcast 128 Bits of Integer Data
SMPTypeCategory[NN_vbroadcastsd] = 14; // Broadcast Double-Precision Floating-Point Element
SMPTypeCategory[NN_vbroadcastss] = 14; // Broadcast Single-Precision Floating-Point Element
SMPTypeCategory[NN_vcmppd] = 14; // Compare Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vcmpps] = 14; // Packed Single-FP Compare
SMPTypeCategory[NN_vcmpsd] = 14; // Compare Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vcmpss] = 14; // Scalar Single-FP Compare
SMPTypeCategory[NN_vcomisd] = 14; // Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
SMPTypeCategory[NN_vcomiss] = 14; // Scalar Ordered Single-FP Compare and Set EFLAGS
SMPTypeCategory[NN_vcvtdq2pd] = 14; // Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vcvtdq2ps] = 14; // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vcvtpd2dq] = 14; // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_vcvtpd2ps] = 14; // Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vcvtph2ps] = 14; // Convert 16-bit FP Values to Single-Precision FP Values
SMPTypeCategory[NN_vcvtps2dq] = 14; // Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_vcvtps2pd] = 14; // Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vcvtps2ph] = 14; // Convert Single-Precision FP value to 16-bit FP value
SMPTypeCategory[NN_vcvtsd2si] = 14; // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
SMPTypeCategory[NN_vcvtsd2ss] = 14; // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
SMPTypeCategory[NN_vcvtsi2sd] = 14; // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_vcvtsi2ss] = 14; // Scalar signed INT32 to Single-FP conversion
SMPTypeCategory[NN_vcvtss2sd] = 14; // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_vcvtss2si] = 14; // Scalar Single-FP to signed INT32 conversion
SMPTypeCategory[NN_vcvttpd2dq] = 14; // Convert With Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_vcvttps2dq] = 14; // Convert With Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_vcvttsd2si] = 14; // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
SMPTypeCategory[NN_vcvttss2si] = 14; // Scalar Single-FP to signed INT32 conversion (truncate)
SMPTypeCategory[NN_vdivpd] = 14; // Divide Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vdivps] = 14; // Packed Single-FP Divide
SMPTypeCategory[NN_vdivsd] = 14; // Divide Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vdivss] = 14; // Scalar Single-FP Divide
SMPTypeCategory[NN_vdppd] = 14; // Dot Product of Packed Double Precision Floating-Point Values
SMPTypeCategory[NN_vdpps] = 14; // Dot Product of Packed Single Precision Floating-Point Values
SMPTypeCategory[NN_vextractf128] = 14; // Extract Packed Floating-Point Values
SMPTypeCategory[NN_vextracti128] = 14; // Extract Packed Integer Values
SMPTypeCategory[NN_vextractps] = 14; // Extract Packed Floating-Point Values
SMPTypeCategory[NN_vfmadd132pd] = 14; // Fused Multiply-Add of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmadd132ps] = 14; // Fused Multiply-Add of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmadd132sd] = 14; // Fused Multiply-Add of Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmadd132ss] = 14; // Fused Multiply-Add of Scalar Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmadd213pd] = 14; // Fused Multiply-Add of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmadd213ps] = 14; // Fused Multiply-Add of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmadd213sd] = 14; // Fused Multiply-Add of Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmadd213ss] = 14; // Fused Multiply-Add of Scalar Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmadd231pd] = 14; // Fused Multiply-Add of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmadd231ps] = 14; // Fused Multiply-Add of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmadd231sd] = 14; // Fused Multiply-Add of Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmadd231ss] = 14; // Fused Multiply-Add of Scalar Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmaddsub132pd] = 14; // Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmaddsub132ps] = 14; // Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmaddsub213pd] = 14; // Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmaddsub213ps] = 14; // Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmaddsub231pd] = 14; // Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmaddsub231ps] = 14; // Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsub132pd] = 14; // Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsub132ps] = 14; // Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsub132sd] = 14; // Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsub132ss] = 14; // Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsub213pd] = 14; // Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsub213ps] = 14; // Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsub213sd] = 14; // Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsub213ss] = 14; // Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsub231pd] = 14; // Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsub231ps] = 14; // Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsub231sd] = 14; // Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsub231ss] = 14; // Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsubadd132pd] = 14; // Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsubadd132ps] = 14; // Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsubadd213pd] = 14; // Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsubadd213ps] = 14; // Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsubadd231pd] = 14; // Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsubadd231ps] = 14; // Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmadd132pd] = 14; // Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmadd132ps] = 14; // Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmadd132sd] = 14; // Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmadd132ss] = 14; // Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmadd213pd] = 14; // Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmadd213ps] = 14; // Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmadd213sd] = 14; // Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmadd213ss] = 14; // Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmadd231pd] = 14; // Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmadd231ps] = 14; // Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmadd231sd] = 14; // Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmadd231ss] = 14; // Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmsub132pd] = 14; // Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmsub132ps] = 14; // Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmsub132sd] = 14; // Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmsub132ss] = 14; // Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmsub213pd] = 14; // Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmsub213ps] = 14; // Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmsub213sd] = 14; // Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmsub213ss] = 14; // Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmsub231pd] = 14; // Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmsub231ps] = 14; // Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmsub231sd] = 14; // Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmsub231ss] = 14; // Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values
SMPTypeCategory[NN_vgatherdps] = 14; // Gather Packed SP FP Values Using Signed Dword Indices
SMPTypeCategory[NN_vgatherdpd] = 14; // Gather Packed DP FP Values Using Signed Dword Indices
SMPTypeCategory[NN_vgatherqps] = 14; // Gather Packed SP FP Values Using Signed Qword Indices
SMPTypeCategory[NN_vgatherqpd] = 14; // Gather Packed DP FP Values Using Signed Qword Indices
SMPTypeCategory[NN_vhaddpd] = 14; // Add horizontally packed DP FP numbers
SMPTypeCategory[NN_vhaddps] = 14; // Add horizontally packed SP FP numbers
SMPTypeCategory[NN_vhsubpd] = 14; // Sub horizontally packed DP FP numbers
SMPTypeCategory[NN_vhsubps] = 14; // Sub horizontally packed SP FP numbers
SMPTypeCategory[NN_vinsertf128] = 14; // Insert Packed Floating-Point Values
SMPTypeCategory[NN_vinserti128] = 14; // Insert Packed Integer Values
SMPTypeCategory[NN_vinsertps] = 14; // Insert Packed Single Precision Floating-Point Value
SMPTypeCategory[NN_vlddqu] = 14; // Load Unaligned Packed Integer Values
SMPTypeCategory[NN_vldmxcsr] = 14; // Load Streaming SIMD Extensions Technology Control/Status Register
SMPTypeCategory[NN_vmaskmovdqu] = 15; // Store Selected Bytes of Double Quadword with NT Hint
SMPTypeCategory[NN_vmaskmovpd] = 15; // Conditionally Load Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vmaskmovps] = 15; // Conditionally Load Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vmaxpd] = 14; // Return Maximum Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vmaxps] = 14; // Packed Single-FP Maximum
SMPTypeCategory[NN_vmaxsd] = 14; // Return Maximum Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_vmaxss] = 14; // Scalar Single-FP Maximum
SMPTypeCategory[NN_vminpd] = 14; // Return Minimum Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vminps] = 14; // Packed Single-FP Minimum
SMPTypeCategory[NN_vminsd] = 14; // Return Minimum Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_vminss] = 14; // Scalar Single-FP Minimum
SMPTypeCategory[NN_vmovapd] = 15; // Move Aligned Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vmovaps] = 15; // Move Aligned Four Packed Single-FP
SMPTypeCategory[NN_vmovd] = 15; // Move 32 bits
SMPTypeCategory[NN_vmovddup] = 15; // Move One Double-FP and Duplicate
SMPTypeCategory[NN_vmovdqa] = 15; // Move Aligned Double Quadword
SMPTypeCategory[NN_vmovdqu] = 15; // Move Unaligned Double Quadword
SMPTypeCategory[NN_vmovhlps] = 15; // Move High to Low Packed Single-FP
SMPTypeCategory[NN_vmovhpd] = 15; // Move High Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vmovhps] = 15; // Move High Packed Single-FP
SMPTypeCategory[NN_vmovlhps] = 15; // Move Low to High Packed Single-FP
SMPTypeCategory[NN_vmovlpd] = 15; // Move Low Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vmovlps] = 15; // Move Low Packed Single-FP
SMPTypeCategory[NN_vmovmskpd] = 15; // Extract Packed Double-Precision Floating-Point Sign Mask
SMPTypeCategory[NN_vmovmskps] = 15; // Move Mask to Register
SMPTypeCategory[NN_vmovntdq] = 15; // Store Double Quadword Using Non-Temporal Hint
SMPTypeCategory[NN_vmovntdqa] = 15; // Load Double Quadword Non-Temporal Aligned Hint
SMPTypeCategory[NN_vmovntpd] = 15; // Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
SMPTypeCategory[NN_vmovntps] = 15; // Move Aligned Four Packed Single-FP Non Temporal
SMPTypeCategory[NN_vmovntsd] = 15; // Move Non-Temporal Scalar Double-Precision Floating-Point
SMPTypeCategory[NN_vmovntss] = 15; // Move Non-Temporal Scalar Single-Precision Floating-Point
SMPTypeCategory[NN_vmovq] = 15; // Move 64 bits
SMPTypeCategory[NN_vmovsd] = 15; // Move Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vmovshdup] = 15; // Move Packed Single-FP High and Duplicate
SMPTypeCategory[NN_vmovsldup] = 15; // Move Packed Single-FP Low and Duplicate
SMPTypeCategory[NN_vmovss] = 15; // Move Scalar Single-FP
SMPTypeCategory[NN_vmovupd] = 15; // Move Unaligned Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vmovups] = 15; // Move Unaligned Four Packed Single-FP
SMPTypeCategory[NN_vmpsadbw] = 14; // Compute Multiple Packed Sums of Absolute Difference
SMPTypeCategory[NN_vmulpd] = 14; // Multiply Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vmulps] = 14; // Packed Single-FP Multiply
SMPTypeCategory[NN_vmulsd] = 14; // Multiply Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vmulss] = 14; // Scalar Single-FP Multiply
SMPTypeCategory[NN_vorpd] = 14; // Bitwise Logical OR of Double-Precision Floating-Point Values
SMPTypeCategory[NN_vorps] = 14; // Bitwise Logical OR for Single-FP Data
SMPTypeCategory[NN_vpabsb] = 14; // Packed Absolute Value Byte
SMPTypeCategory[NN_vpabsd] = 14; // Packed Absolute Value Doubleword
SMPTypeCategory[NN_vpabsw] = 14; // Packed Absolute Value Word
SMPTypeCategory[NN_vpackssdw] = 14; // Pack with Signed Saturation (Dword->Word)
SMPTypeCategory[NN_vpacksswb] = 14; // Pack with Signed Saturation (Word->Byte)
SMPTypeCategory[NN_vpackusdw] = 14; // Pack with Unsigned Saturation
SMPTypeCategory[NN_vpackuswb] = 14; // Pack with Unsigned Saturation (Word->Byte)
SMPTypeCategory[NN_vpaddb] = 14; // Packed Add Byte
SMPTypeCategory[NN_vpaddd] = 14; // Packed Add Dword
SMPTypeCategory[NN_vpaddq] = 14; // Add Packed Quadword Integers
SMPTypeCategory[NN_vpaddsb] = 14; // Packed Add with Saturation (Byte)
SMPTypeCategory[NN_vpaddsw] = 14; // Packed Add with Saturation (Word)
SMPTypeCategory[NN_vpaddusb] = 14; // Packed Add Unsigned with Saturation (Byte)
SMPTypeCategory[NN_vpaddusw] = 14; // Packed Add Unsigned with Saturation (Word)
SMPTypeCategory[NN_vpaddw] = 14; // Packed Add Word
SMPTypeCategory[NN_vpalignr] = 14; // Packed Align Right
SMPTypeCategory[NN_vpand] = 14; // Bitwise Logical And
SMPTypeCategory[NN_vpandn] = 14; // Bitwise Logical And Not
SMPTypeCategory[NN_vpavgb] = 14; // Packed Average (Byte)
SMPTypeCategory[NN_vpavgw] = 14; // Packed Average (Word)
SMPTypeCategory[NN_vpblendd] = 14; // Blend Packed Dwords
SMPTypeCategory[NN_vpblendvb] = 14; // Variable Blend Packed Bytes
SMPTypeCategory[NN_vpblendw] = 14; // Blend Packed Words
SMPTypeCategory[NN_vpbroadcastb] = 14; // Broadcast a Byte Integer
SMPTypeCategory[NN_vpbroadcastd] = 14; // Broadcast a Dword Integer
SMPTypeCategory[NN_vpbroadcastq] = 14; // Broadcast a Qword Integer
SMPTypeCategory[NN_vpbroadcastw] = 14; // Broadcast a Word Integer
SMPTypeCategory[NN_vpclmulqdq] = 14; // Carry-Less Multiplication Quadword
SMPTypeCategory[NN_vpcmpeqb] = 14; // Packed Compare for Equal (Byte)
SMPTypeCategory[NN_vpcmpeqd] = 14; // Packed Compare for Equal (Dword)
SMPTypeCategory[NN_vpcmpeqq] = 14; // Compare Packed Qword Data for Equal
SMPTypeCategory[NN_vpcmpeqw] = 14; // Packed Compare for Equal (Word)
SMPTypeCategory[NN_vpcmpestri] = 14; // Packed Compare Explicit Length Strings, Return Index
SMPTypeCategory[NN_vpcmpestrm] = 14; // Packed Compare Explicit Length Strings, Return Mask
SMPTypeCategory[NN_vpcmpgtb] = 14; // Packed Compare for Greater Than (Byte)
SMPTypeCategory[NN_vpcmpgtd] = 14; // Packed Compare for Greater Than (Dword)
SMPTypeCategory[NN_vpcmpgtq] = 14; // Compare Packed Data for Greater Than
SMPTypeCategory[NN_vpcmpgtw] = 14; // Packed Compare for Greater Than (Word)
SMPTypeCategory[NN_vpcmpistri] = 14; // Packed Compare Implicit Length Strings, Return Index
SMPTypeCategory[NN_vpcmpistrm] = 14; // Packed Compare Implicit Length Strings, Return Mask
SMPTypeCategory[NN_vperm2f128] = 14; // Permute Floating-Point Values
SMPTypeCategory[NN_vperm2i128] = 14; // Permute Integer Values
SMPTypeCategory[NN_vpermd] = 14; // Full Doublewords Element Permutation
SMPTypeCategory[NN_vpermilpd] = 14; // Permute Double-Precision Floating-Point Values
SMPTypeCategory[NN_vpermilps] = 14; // Permute Single-Precision Floating-Point Values
SMPTypeCategory[NN_vpermpd] = 14; // Permute Double-Precision Floating-Point Elements
SMPTypeCategory[NN_vpermps] = 14; // Permute Single-Precision Floating-Point Elements
SMPTypeCategory[NN_vpermq] = 14; // Qwords Element Permutation
SMPTypeCategory[NN_vpextrb] = 14; // Extract Byte
SMPTypeCategory[NN_vpextrd] = 14; // Extract Dword
SMPTypeCategory[NN_vpextrq] = 14; // Extract Qword
SMPTypeCategory[NN_vpextrw] = 14; // Extract Word
SMPTypeCategory[NN_vpgatherdd] = 14; // Gather Packed Dword Values Using Signed Dword Indices
SMPTypeCategory[NN_vpgatherdq] = 14; // Gather Packed Qword Values Using Signed Dword Indices
SMPTypeCategory[NN_vpgatherqd] = 14; // Gather Packed Dword Values Using Signed Qword Indices
SMPTypeCategory[NN_vpgatherqq] = 14; // Gather Packed Qword Values Using Signed Qword Indices
SMPTypeCategory[NN_vphaddd] = 14; // Packed Horizontal Add Doubleword
SMPTypeCategory[NN_vphaddsw] = 14; // Packed Horizontal Add and Saturate
SMPTypeCategory[NN_vphaddw] = 14; // Packed Horizontal Add Word
SMPTypeCategory[NN_vphminposuw] = 14; // Packed Horizontal Word Minimum
SMPTypeCategory[NN_vphsubd] = 14; // Packed Horizontal Subtract Doubleword
SMPTypeCategory[NN_vphsubsw] = 14; // Packed Horizontal Subtract and Saturate
SMPTypeCategory[NN_vphsubw] = 14; // Packed Horizontal Subtract Word
SMPTypeCategory[NN_vpinsrb] = 14; // Insert Byte
SMPTypeCategory[NN_vpinsrd] = 14; // Insert Dword
SMPTypeCategory[NN_vpinsrq] = 14; // Insert Qword
SMPTypeCategory[NN_vpinsrw] = 14; // Insert Word
SMPTypeCategory[NN_vpmaddubsw] = 14; // Multiply and Add Packed Signed and Unsigned Bytes
SMPTypeCategory[NN_vpmaddwd] = 14; // Packed Multiply and Add
SMPTypeCategory[NN_vpmaskmovd] = 15; // Conditionally Store Dword Values Using Mask
SMPTypeCategory[NN_vpmaskmovq] = 15; // Conditionally Store Qword Values Using Mask
SMPTypeCategory[NN_vpmaxsb] = 14; // Maximum of Packed Signed Byte Integers
SMPTypeCategory[NN_vpmaxsd] = 14; // Maximum of Packed Signed Dword Integers
SMPTypeCategory[NN_vpmaxsw] = 14; // Packed Signed Integer Word Maximum
SMPTypeCategory[NN_vpmaxub] = 14; // Packed Unsigned Integer Byte Maximum
SMPTypeCategory[NN_vpmaxud] = 14; // Maximum of Packed Unsigned Dword Integers
SMPTypeCategory[NN_vpmaxuw] = 14; // Maximum of Packed Word Integers
SMPTypeCategory[NN_vpminsb] = 14; // Minimum of Packed Signed Byte Integers
SMPTypeCategory[NN_vpminsd] = 14; // Minimum of Packed Signed Dword Integers
SMPTypeCategory[NN_vpminsw] = 14; // Packed Signed Integer Word Minimum
SMPTypeCategory[NN_vpminub] = 14; // Packed Unsigned Integer Byte Minimum
SMPTypeCategory[NN_vpminud] = 14; // Minimum of Packed Unsigned Dword Integers
SMPTypeCategory[NN_vpminuw] = 14; // Minimum of Packed Word Integers
SMPTypeCategory[NN_vpmovmskb] = 15; // Move Byte Mask to Integer
SMPTypeCategory[NN_vpmovsxbd] = 15; // Packed Move with Sign Extend
SMPTypeCategory[NN_vpmovsxbq] = 15; // Packed Move with Sign Extend
SMPTypeCategory[NN_vpmovsxbw] = 15; // Packed Move with Sign Extend
SMPTypeCategory[NN_vpmovsxdq] = 15; // Packed Move with Sign Extend
SMPTypeCategory[NN_vpmovsxwd] = 15; // Packed Move with Sign Extend
SMPTypeCategory[NN_vpmovsxwq] = 15; // Packed Move with Sign Extend
SMPTypeCategory[NN_vpmovzxbd] = 15; // Packed Move with Zero Extend
SMPTypeCategory[NN_vpmovzxbq] = 15; // Packed Move with Zero Extend
SMPTypeCategory[NN_vpmovzxbw] = 15; // Packed Move with Zero Extend
SMPTypeCategory[NN_vpmovzxdq] = 15; // Packed Move with Zero Extend
SMPTypeCategory[NN_vpmovzxwd] = 15; // Packed Move with Zero Extend
SMPTypeCategory[NN_vpmovzxwq] = 15; // Packed Move with Zero Extend
SMPTypeCategory[NN_vpmuldq] = 14; // Multiply Packed Signed Dword Integers
SMPTypeCategory[NN_vpmulhrsw] = 14; // Packed Multiply High with Round and Scale
SMPTypeCategory[NN_vpmulhuw] = 14; // Packed Multiply High Unsigned
SMPTypeCategory[NN_vpmulhw] = 14; // Packed Multiply High
SMPTypeCategory[NN_vpmulld] = 14; // Multiply Packed Signed Dword Integers and Store Low Result
SMPTypeCategory[NN_vpmullw] = 14; // Packed Multiply Low
SMPTypeCategory[NN_vpmuludq] = 14; // Multiply Packed Unsigned Doubleword Integers
SMPTypeCategory[NN_vpor] = 14; // Bitwise Logical Or
SMPTypeCategory[NN_vpsadbw] = 14; // Packed Sum of Absolute Differences
SMPTypeCategory[NN_vpshufb] = 14; // Packed Shuffle Bytes
SMPTypeCategory[NN_vpshufd] = 14; // Shuffle Packed Doublewords
SMPTypeCategory[NN_vpshufhw] = 14; // Shuffle Packed High Words
SMPTypeCategory[NN_vpshuflw] = 14; // Shuffle Packed Low Words
SMPTypeCategory[NN_vpsignb] = 14; // Packed SIGN Byte
SMPTypeCategory[NN_vpsignd] = 14; // Packed SIGN Doubleword
SMPTypeCategory[NN_vpsignw] = 14; // Packed SIGN Word
SMPTypeCategory[NN_vpslld] = 14; // Packed Shift Left Logical (Dword)
SMPTypeCategory[NN_vpslldq] = 14; // Shift Double Quadword Left Logical
SMPTypeCategory[NN_vpsllq] = 14; // Packed Shift Left Logical (Qword)
SMPTypeCategory[NN_vpsllvd] = 14; // Variable Bit Shift Left Logical (Dword)
SMPTypeCategory[NN_vpsllvq] = 14; // Variable Bit Shift Left Logical (Qword)
SMPTypeCategory[NN_vpsllw] = 14; // Packed Shift Left Logical (Word)
SMPTypeCategory[NN_vpsrad] = 14; // Packed Shift Right Arithmetic (Dword)
SMPTypeCategory[NN_vpsravd] = 14; // Variable Bit Shift Right Arithmetic
SMPTypeCategory[NN_vpsraw] = 14; // Packed Shift Right Arithmetic (Word)
SMPTypeCategory[NN_vpsrld] = 14; // Packed Shift Right Logical (Dword)
SMPTypeCategory[NN_vpsrldq] = 14; // Shift Double Quadword Right Logical (Qword)
SMPTypeCategory[NN_vpsrlq] = 14; // Packed Shift Right Logical (Qword)
SMPTypeCategory[NN_vpsrlvd] = 14; // Variable Bit Shift Right Logical (Dword)
SMPTypeCategory[NN_vpsrlvq] = 14; // Variable Bit Shift Right Logical (Qword)
SMPTypeCategory[NN_vpsrlw] = 14; // Packed Shift Right Logical (Word)
SMPTypeCategory[NN_vpsubb] = 14; // Packed Subtract Byte
SMPTypeCategory[NN_vpsubd] = 14; // Packed Subtract Dword
SMPTypeCategory[NN_vpsubq] = 14; // Subtract Packed Quadword Integers
SMPTypeCategory[NN_vpsubsb] = 14; // Packed Subtract with Saturation (Byte)
SMPTypeCategory[NN_vpsubsw] = 14; // Packed Subtract with Saturation (Word)
SMPTypeCategory[NN_vpsubusb] = 14; // Packed Subtract Unsigned with Saturation (Byte)
SMPTypeCategory[NN_vpsubusw] = 14; // Packed Subtract Unsigned with Saturation (Word)
SMPTypeCategory[NN_vpsubw] = 14; // Packed Subtract Word
SMPTypeCategory[NN_vptest] = 14; // Logical Compare
SMPTypeCategory[NN_vpunpckhbw] = 14; // Unpack High Packed Data (Byte->Word)
SMPTypeCategory[NN_vpunpckhdq] = 14; // Unpack High Packed Data (Dword->Qword)
SMPTypeCategory[NN_vpunpckhqdq] = 14; // Unpack High Packed Data (Qword->Xmmword)
SMPTypeCategory[NN_vpunpckhwd] = 14; // Unpack High Packed Data (Word->Dword)
SMPTypeCategory[NN_vpunpcklbw] = 14; // Unpack Low Packed Data (Byte->Word)
SMPTypeCategory[NN_vpunpckldq] = 14; // Unpack Low Packed Data (Dword->Qword)
SMPTypeCategory[NN_vpunpcklqdq] = 14; // Unpack Low Packed Data (Qword->Xmmword)
SMPTypeCategory[NN_vpunpcklwd] = 14; // Unpack Low Packed Data (Word->Dword)
SMPTypeCategory[NN_vpxor] = 14; // Bitwise Logical Exclusive Or
SMPTypeCategory[NN_vrcpps] = 14; // Packed Single-FP Reciprocal
SMPTypeCategory[NN_vrcpss] = 14; // Scalar Single-FP Reciprocal
SMPTypeCategory[NN_vroundpd] = 14; // Round Packed Double Precision Floating-Point Values
SMPTypeCategory[NN_vroundps] = 14; // Round Packed Single Precision Floating-Point Values
SMPTypeCategory[NN_vroundsd] = 14; // Round Scalar Double Precision Floating-Point Values
SMPTypeCategory[NN_vroundss] = 14; // Round Scalar Single Precision Floating-Point Values
SMPTypeCategory[NN_vrsqrtps] = 14; // Packed Single-FP Square Root Reciprocal
SMPTypeCategory[NN_vrsqrtss] = 14; // Scalar Single-FP Square Root Reciprocal
SMPTypeCategory[NN_vshufpd] = 14; // Shuffle Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vshufps] = 14; // Shuffle Single-FP
SMPTypeCategory[NN_vsqrtpd] = 14; // Compute Square Roots of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vsqrtps] = 14; // Packed Single-FP Square Root
SMPTypeCategory[NN_vsqrtsd] = 14; // Compute Square Rootof Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_vsqrtss] = 14; // Scalar Single-FP Square Root
SMPTypeCategory[NN_vstmxcsr] = 14; // Store Streaming SIMD Extensions Technology Control/Status Register
SMPTypeCategory[NN_vsubpd] = 14; // Subtract Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vsubps] = 14; // Packed Single-FP Subtract
SMPTypeCategory[NN_vsubsd] = 14; // Subtract Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vsubss] = 14; // Scalar Single-FP Subtract
SMPTypeCategory[NN_vtestpd] = 14; // Packed Double-Precision Floating-Point Bit Test
SMPTypeCategory[NN_vtestps] = 14; // Packed Single-Precision Floating-Point Bit Test
SMPTypeCategory[NN_vucomisd] = 14; // Unordered Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
SMPTypeCategory[NN_vucomiss] = 14; // Scalar Unordered Single-FP Compare and Set EFLAGS
SMPTypeCategory[NN_vunpckhpd] = 14; // Unpack and Interleave High Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vunpckhps] = 14; // Unpack High Packed Single-FP Data
SMPTypeCategory[NN_vunpcklpd] = 14; // Unpack and Interleave Low Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vunpcklps] = 14; // Unpack Low Packed Single-FP Data
SMPTypeCategory[NN_vxorpd] = 14; // Bitwise Logical OR of Double-Precision Floating-Point Values
SMPTypeCategory[NN_vxorps] = 14; // Bitwise Logical XOR for Single-FP Data
SMPTypeCategory[NN_vzeroall] = 14; // Zero All YMM Registers
SMPTypeCategory[NN_vzeroupper] = 14; // Zero Upper Bits of YMM Registers
// Transactional Synchronization Extensions
SMPTypeCategory[NN_xabort] = 1; // Transaction Abort
SMPTypeCategory[NN_xbegin] = 1; // Transaction Begin
SMPTypeCategory[NN_xend] = 1; // Transaction End
SMPTypeCategory[NN_xtest] = 1; // Test If In Transactional Execution
// Virtual PC synthetic instructions
SMPTypeCategory[NN_vmgetinfo] = 1; // Virtual PC - Get VM Information
SMPTypeCategory[NN_vmsetinfo] = 1; // Virtual PC - Set VM Information
SMPTypeCategory[NN_vmdxdsbl] = 1; // Virtual PC - Disable Direct Execution
SMPTypeCategory[NN_vmdxenbl] = 1; // Virtual PC - Enable Direct Execution
SMPTypeCategory[NN_vmcpuid] = 1; // Virtual PC - Virtualized CPU Information
SMPTypeCategory[NN_vmhlt] = 1; // Virtual PC - Halt
SMPTypeCategory[NN_vmsplaf] = 1; // Virtual PC - Spin Lock Acquisition Failed
SMPTypeCategory[NN_vmpushfd] = 1; // Virtual PC - Push virtualized flags register
SMPTypeCategory[NN_vmpopfd] = 1; // Virtual PC - Pop virtualized flags register
SMPTypeCategory[NN_vmcli] = 1; // Virtual PC - Clear Interrupt Flag
SMPTypeCategory[NN_vmsti] = 1; // Virtual PC - Set Interrupt Flag
SMPTypeCategory[NN_vmiretd] = 1; // Virtual PC - Return From Interrupt
SMPTypeCategory[NN_vmsgdt] = 1; // Virtual PC - Store Global Descriptor Table
SMPTypeCategory[NN_vmsidt] = 1; // Virtual PC - Store Interrupt Descriptor Table
SMPTypeCategory[NN_vmsldt] = 1; // Virtual PC - Store Local Descriptor Table
SMPTypeCategory[NN_vmstr] = 1; // Virtual PC - Store Task Register
SMPTypeCategory[NN_vmsdte] = 1; // Virtual PC - Store to Descriptor Table Entry
SMPTypeCategory[NN_vpcext] = 1; // Virtual PC - ISA extension
#endif // 599 < IDA_SDK_VERSION
SMPTypeCategory[NN_last] = 1;
return;
} // end InitTypeCategory()