From 2994f35fe4e2e3513c36253a5f09d1b3bac39ede Mon Sep 17 00:00:00 2001
From: Nguyen Anh Quynh <aquynh@gmail.com>
Date: Tue, 19 Jul 2016 17:42:48 +0800
Subject: [PATCH] cleanup
---
llvm/lib/MC/ELFObjectWriter.cpp | 66 -------------------
llvm/lib/MC/MCParser/AsmParser.cpp | 3 +-
llvm/lib/MC/MCParser/DarwinAsmParser.cpp | 4 +-
.../Target/AArch64/AArch64GenAsmMatcher.inc | 15 -----
.../MCTargetDesc/AArch64MCCodeEmitter.cpp | 53 ---------------
llvm/lib/Target/ARM/ARMGenAsmMatcher.inc | 14 ----
.../ARM/MCTargetDesc/ARMMCCodeEmitter.cpp | 41 ------------
.../Target/Mips/AsmParser/MipsAsmParser.cpp | 58 ----------------
llvm/lib/Target/PowerPC/PPCGenAsmMatcher.inc | 14 ----
llvm/lib/Target/Sparc/SparcGenAsmMatcher.inc | 14 ----
.../Target/SystemZ/SystemZGenAsmMatcher.inc | 14 ----
11 files changed, 4 insertions(+), 292 deletions(-)
diff --git a/llvm/lib/MC/ELFObjectWriter.cpp b/llvm/lib/MC/ELFObjectWriter.cpp
index 0de700c..c2361d5 100644
--- a/llvm/lib/MC/ELFObjectWriter.cpp
+++ b/llvm/lib/MC/ELFObjectWriter.cpp
@@ -69,7 +69,6 @@ public:
};
class ELFObjectWriter : public MCObjectWriter {
- static bool isFixupKindPCRel(const MCAssembler &Asm, unsigned Kind);
static uint64_t SymbolValue(const MCSymbol &Sym, const MCAsmLayout &Layout);
static bool isInSymtab(const MCAsmLayout &Layout, const MCSymbolELF &Symbol,
bool Used, bool Renamed);
@@ -166,8 +165,6 @@ class ELFObjectWriter : public MCObjectWriter {
support::endian::Writer<support::big>(getStream()).write(Val);
}
- void writeHeader(const MCAssembler &Asm);
-
void writeSymbol(SymbolTableWriter &Writer, uint32_t StringIndex,
ELFSymbolData &MSD, const MCAsmLayout &Layout);
@@ -296,69 +293,9 @@ void SymbolTableWriter::writeSymbol(uint32_t name, uint8_t info, uint64_t value,
++NumWritten;
}
-bool ELFObjectWriter::isFixupKindPCRel(const MCAssembler &Asm, unsigned Kind) {
- const MCFixupKindInfo &FKI =
- Asm.getBackend().getFixupKindInfo((MCFixupKind) Kind);
-
- return FKI.Flags & MCFixupKindInfo::FKF_IsPCRel;
-}
-
ELFObjectWriter::~ELFObjectWriter()
{}
-// Emit the ELF header.
-void ELFObjectWriter::writeHeader(const MCAssembler &Asm) {
- // ELF Header
- // ----------
- //
- // Note
- // ----
- // emitWord method behaves differently for ELF32 and ELF64, writing
- // 4 bytes in the former and 8 in the latter.
-
- writeBytes(ELF::ElfMagic); // e_ident[EI_MAG0] to e_ident[EI_MAG3]
-
- write8(is64Bit() ? ELF::ELFCLASS64 : ELF::ELFCLASS32); // e_ident[EI_CLASS]
-
- // e_ident[EI_DATA]
- write8(isLittleEndian() ? ELF::ELFDATA2LSB : ELF::ELFDATA2MSB);
-
- write8(ELF::EV_CURRENT); // e_ident[EI_VERSION]
- // e_ident[EI_OSABI]
- write8(TargetObjectWriter->getOSABI());
- write8(0); // e_ident[EI_ABIVERSION]
-
- WriteZeros(ELF::EI_NIDENT - ELF::EI_PAD);
-
- write16(ELF::ET_REL); // e_type
-
- write16(TargetObjectWriter->getEMachine()); // e_machine = target
-
- write32(ELF::EV_CURRENT); // e_version
- WriteWord(0); // e_entry, no entry point in .o file
- WriteWord(0); // e_phoff, no program header for .o
- WriteWord(0); // e_shoff = sec hdr table off in bytes
-
- // e_flags = whatever the target wants
- write32(Asm.getELFHeaderEFlags());
-
- // e_ehsize = ELF header size
- write16(is64Bit() ? sizeof(ELF::Elf64_Ehdr) : sizeof(ELF::Elf32_Ehdr));
-
- write16(0); // e_phentsize = prog header entry size
- write16(0); // e_phnum = # prog header entries = 0
-
- // e_shentsize = Section header entry size
- write16(is64Bit() ? sizeof(ELF::Elf64_Shdr) : sizeof(ELF::Elf32_Shdr));
-
- // e_shnum = # of section header ents
- write16(0);
-
- // e_shstrndx = Section # of '.shstrtab'
- assert(StringTableIndex < ELF::SHN_LORESERVE);
- write16(StringTableIndex);
-}
-
uint64_t ELFObjectWriter::SymbolValue(const MCSymbol &Sym,
const MCAsmLayout &Layout) {
if (Sym.isCommon() && Sym.isExternal())
@@ -1173,9 +1110,6 @@ void ELFObjectWriter::writeObject(MCAssembler &Asm,
std::map<const MCSymbol *, std::vector<const MCSectionELF *>> GroupMembers;
- // Write out the ELF header ...
- //writeHeader(Asm); // qq
-
// ... then the sections ...
SectionOffsetsTy SectionOffsets;
std::vector<MCSectionELF *> Groups;
diff --git a/llvm/lib/MC/MCParser/AsmParser.cpp b/llvm/lib/MC/MCParser/AsmParser.cpp
index cb432b4..9bc787c 100644
--- a/llvm/lib/MC/MCParser/AsmParser.cpp
+++ b/llvm/lib/MC/MCParser/AsmParser.cpp
@@ -3221,10 +3221,11 @@ bool AsmParser::parseDirectiveAlign(bool IsPow2, unsigned ValueSize)
// up to one.
if (Alignment == 0)
Alignment = 1;
- if (!isPowerOf2_64(Alignment))
+ if (!isPowerOf2_64(Alignment)) {
//Error(AlignmentLoc, "alignment must be a power of 2");
KsError = KS_ERR_ASM_DIRECTIVE_INVALID;
return true;
+ }
}
// Diagnose non-sensical max bytes to align.
diff --git a/llvm/lib/MC/MCParser/DarwinAsmParser.cpp b/llvm/lib/MC/MCParser/DarwinAsmParser.cpp
index 76e1b7d..3a7b127 100644
--- a/llvm/lib/MC/MCParser/DarwinAsmParser.cpp
+++ b/llvm/lib/MC/MCParser/DarwinAsmParser.cpp
@@ -930,8 +930,8 @@ bool DarwinAsmParser::parseVersionMin(StringRef Directive, SMLoc Loc) {
if (getLexer().isNot(AsmToken::Integer))
return TokError("invalid OS update number");
Update = getLexer().getTok().getIntVal(valid);
- if (Update > 255 || Update < 0)
- return TokError("invalid OS update number");
+ if (Update > 255 || Update < 0)
+ return TokError("invalid OS update number");
Lex();
}
diff --git a/llvm/lib/Target/AArch64/AArch64GenAsmMatcher.inc b/llvm/lib/Target/AArch64/AArch64GenAsmMatcher.inc
index 5123f22..6ed8079 100644
--- a/llvm/lib/Target/AArch64/AArch64GenAsmMatcher.inc
+++ b/llvm/lib/Target/AArch64/AArch64GenAsmMatcher.inc
@@ -16,7 +16,6 @@
const OperandVector &Operands);
void convertToMapAndConstraints(unsigned Kind,
const OperandVector &Operands) override;
- bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID);
unsigned MatchInstructionImpl(const OperandVector &Operands,
MCInst &Inst,
uint64_t &ErrorInfo, bool matchingInlineAsm,
@@ -14564,20 +14563,6 @@ static const MatchEntry MatchTable1[] = {
{ 4039 /* zip2 */, AArch64::ZIP2v8i16, Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3, Feature_HasNEON, { MCK__DOT_8h, MCK_VectorReg128, MCK_VectorReg128, MCK_VectorReg128 }, },
};
-bool AArch64AsmParser::
-mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) {
- // Find the appropriate table for this asm variant.
- const MatchEntry *Start, *End;
- switch (VariantID) {
- default: llvm_unreachable("invalid variant!");
- case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
- case 1: Start = std::begin(MatchTable1); End = std::end(MatchTable1); break;
- }
- // Search the table.
- auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
- return MnemonicRange.first != MnemonicRange.second;
-}
-
unsigned AArch64AsmParser::
MatchInstructionImpl(const OperandVector &Operands,
MCInst &Inst, uint64_t &ErrorInfo,
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
index e8eb59f..e4e6143 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
@@ -151,24 +151,6 @@ public:
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
- /// getSIMDShift64OpValue - Return the encoded value for the
- // shift-by-immediate AdvSIMD instructions.
- uint32_t getSIMDShift64OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
- uint32_t getSIMDShift64_32OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
- uint32_t getSIMDShift32OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
- uint32_t getSIMDShift16OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
unsigned fixMOVZ(const MCInst &MI, unsigned EncodedValue,
const MCSubtargetInfo &STI) const;
@@ -413,41 +395,6 @@ AArch64MCCodeEmitter::getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
llvm_unreachable("Invalid value for vector shift amount!");
}
-uint32_t
-AArch64MCCodeEmitter::getSIMDShift64OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(OpIdx);
- assert(MO.isImm() && "Expected an immediate value for the shift amount!");
- return 64 - (MO.getImm());
-}
-
-uint32_t AArch64MCCodeEmitter::getSIMDShift64_32OpValue(
- const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(OpIdx);
- assert(MO.isImm() && "Expected an immediate value for the shift amount!");
- return 64 - (MO.getImm() | 32);
-}
-
-uint32_t
-AArch64MCCodeEmitter::getSIMDShift32OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(OpIdx);
- assert(MO.isImm() && "Expected an immediate value for the shift amount!");
- return 32 - (MO.getImm() | 16);
-}
-
-uint32_t
-AArch64MCCodeEmitter::getSIMDShift16OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(OpIdx);
- assert(MO.isImm() && "Expected an immediate value for the shift amount!");
- return 16 - (MO.getImm() | 8);
-}
-
/// getFixedPointScaleOpValue - Return the encoded value for the
// FP-to-fixed-point scale factor.
uint32_t AArch64MCCodeEmitter::getFixedPointScaleOpValue(
diff --git a/llvm/lib/Target/ARM/ARMGenAsmMatcher.inc b/llvm/lib/Target/ARM/ARMGenAsmMatcher.inc
index c7f2e9b..8dca24e 100644
--- a/llvm/lib/Target/ARM/ARMGenAsmMatcher.inc
+++ b/llvm/lib/Target/ARM/ARMGenAsmMatcher.inc
@@ -16,7 +16,6 @@
const OperandVector &Operands);
void convertToMapAndConstraints(unsigned Kind,
const OperandVector &Operands) override;
- bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID);
unsigned MatchInstructionImpl(const OperandVector &Operands,
MCInst &Inst,
uint64_t &ErrorInfo, bool matchingInlineAsm,
@@ -10452,19 +10451,6 @@ static const MatchEntry MatchTable0[] = {
{ 2676 /* yield */, ARM::t2HINT, Convert__imm_95_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
};
-bool ARMAsmParser::
-mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) {
- // Find the appropriate table for this asm variant.
- const MatchEntry *Start, *End;
- switch (VariantID) {
- default: llvm_unreachable("invalid variant!");
- case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
- }
- // Search the table.
- auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
- return MnemonicRange.first != MnemonicRange.second;
-}
-
unsigned ARMAsmParser::
MatchInstructionImpl(const OperandVector &Operands,
MCInst &Inst, uint64_t &ErrorInfo,
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
index 152fd56..ea324d9 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -217,11 +217,6 @@ public:
llvm_unreachable("Invalid ShiftOpc!");
}
- /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
- uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
/// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
@@ -353,10 +348,6 @@ public:
unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
- unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
/// getSORegOpValue - Return an encoded so_reg shifted register value.
unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
@@ -1112,21 +1103,6 @@ getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
return Binary;
}
-uint32_t ARMMCCodeEmitter::
-getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- // {17-14} Rn
- // {13} 1 == imm12, 0 == Rm
- // {12} isAdd
- // {11-0} imm12/Rm
- const MCOperand &MO = MI.getOperand(OpIdx);
- unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
- uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups, STI);
- Binary |= Rn << 14;
- return Binary;
-}
-
uint32_t ARMMCCodeEmitter::
getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
@@ -1488,23 +1464,6 @@ getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
return Value;
}
-unsigned ARMMCCodeEmitter::
-getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO1 = MI.getOperand(OpNum);
-
- // FIXME: Needs fixup support.
- unsigned Value = 0;
- int32_t tmp = (int32_t)MO1.getImm();
- if (tmp < 0)
- tmp = abs(tmp);
- else
- Value |= 4096; // Set the ADD bit
- Value |= tmp & 4095;
- return Value;
-}
-
unsigned ARMMCCodeEmitter::
getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 0f2efa2..4be9a46 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -159,7 +159,6 @@ class MipsAsmParser : public MCTargetAsmParser {
OperandMatchResultTy parseImm(OperandVector &Operands);
OperandMatchResultTy parseJumpTarget(OperandVector &Operands);
OperandMatchResultTy parseInvNum(OperandVector &Operands);
- OperandMatchResultTy parseLSAImm(OperandVector &Operands);
OperandMatchResultTy parseRegisterPair(OperandVector &Operands);
OperandMatchResultTy parseMovePRegPair(OperandVector &Operands);
OperandMatchResultTy parseRegisterList(OperandVector &Operands);
@@ -308,8 +307,6 @@ class MipsAsmParser : public MCTargetAsmParser {
int matchHWRegsRegisterName(StringRef Symbol);
- int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
-
int matchFPURegisterName(StringRef Name);
int matchFCCRegisterName(StringRef Name);
@@ -322,8 +319,6 @@ class MipsAsmParser : public MCTargetAsmParser {
unsigned getReg(int RC, int RegNo);
- unsigned getGPR(int RegNo);
-
/// Returns the internal register number for the current AT. Also checks if
/// the current AT is unavailable (set to $0) and gives an error if it is.
/// This should be used in pseudo-instruction expansions which need AT.
@@ -4042,19 +4037,6 @@ unsigned MipsAsmParser::getReg(int RC, int RegNo) {
return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo);
}
-unsigned MipsAsmParser::getGPR(int RegNo) {
- return getReg(isGP64bit() ? Mips::GPR64RegClassID : Mips::GPR32RegClassID,
- RegNo);
-}
-
-int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
- if (RegNum >
- getContext().getRegisterInfo()->getRegClass(RegClass).getNumRegs() - 1)
- return -1;
-
- return getReg(RegClass, RegNum);
-}
-
bool MipsAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic, unsigned int &ErrorCode)
{
MCAsmParser &Parser = getParser();
@@ -4616,46 +4598,6 @@ MipsAsmParser::parseInvNum(OperandVector &Operands) {
return MatchOperand_Success;
}
-MipsAsmParser::OperandMatchResultTy
-MipsAsmParser::parseLSAImm(OperandVector &Operands) {
- MCAsmParser &Parser = getParser();
- switch (getLexer().getKind()) {
- default:
- return MatchOperand_NoMatch;
- case AsmToken::LParen:
- case AsmToken::Plus:
- case AsmToken::Minus:
- case AsmToken::Integer:
- break;
- }
-
- const MCExpr *Expr;
- SMLoc S = Parser.getTok().getLoc();
-
- if (getParser().parseExpression(Expr))
- return MatchOperand_ParseFail;
-
- int64_t Val;
- if (!Expr->evaluateAsAbsolute(Val)) {
- Error(S, "expected immediate value");
- return MatchOperand_ParseFail;
- }
-
- // The LSA instruction allows a 2-bit unsigned immediate. For this reason
- // and because the CPU always adds one to the immediate field, the allowed
- // range becomes 1..4. We'll only check the range here and will deal
- // with the addition/subtraction when actually decoding/encoding
- // the instruction.
- if (Val < 1 || Val > 4) {
- Error(S, "immediate not in range (1..4)");
- return MatchOperand_ParseFail;
- }
-
- Operands.push_back(
- MipsOperand::CreateImm(Expr, S, Parser.getTok().getLoc(), *this));
- return MatchOperand_Success;
-}
-
MipsAsmParser::OperandMatchResultTy
MipsAsmParser::parseRegisterList(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
diff --git a/llvm/lib/Target/PowerPC/PPCGenAsmMatcher.inc b/llvm/lib/Target/PowerPC/PPCGenAsmMatcher.inc
index bc21aaf..953533e 100644
--- a/llvm/lib/Target/PowerPC/PPCGenAsmMatcher.inc
+++ b/llvm/lib/Target/PowerPC/PPCGenAsmMatcher.inc
@@ -16,7 +16,6 @@
const OperandVector &Operands);
void convertToMapAndConstraints(unsigned Kind,
const OperandVector &Operands) override;
- bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID);
unsigned MatchInstructionImpl(const OperandVector &Operands,
MCInst &Inst,
uint64_t &ErrorInfo, bool matchingInlineAsm,
@@ -5955,19 +5954,6 @@ static const MatchEntry MatchTable0[] = {
{ 11831 /* xxswapd */, PPC::XXPERMDI, Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_1__imm_95_2, 0, { MCK_RegVSRC, MCK_RegVSRC }, },
};
-bool PPCAsmParser::
-mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) {
- // Find the appropriate table for this asm variant.
- const MatchEntry *Start, *End;
- switch (VariantID) {
- default: llvm_unreachable("invalid variant!");
- case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
- }
- // Search the table.
- auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
- return MnemonicRange.first != MnemonicRange.second;
-}
-
unsigned PPCAsmParser::
MatchInstructionImpl(const OperandVector &Operands,
MCInst &Inst, uint64_t &ErrorInfo,
diff --git a/llvm/lib/Target/Sparc/SparcGenAsmMatcher.inc b/llvm/lib/Target/Sparc/SparcGenAsmMatcher.inc
index d83444d..b7e689c 100644
--- a/llvm/lib/Target/Sparc/SparcGenAsmMatcher.inc
+++ b/llvm/lib/Target/Sparc/SparcGenAsmMatcher.inc
@@ -16,7 +16,6 @@
const OperandVector &Operands);
void convertToMapAndConstraints(unsigned Kind,
const OperandVector &Operands) override;
- bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID);
unsigned MatchInstructionImpl(const OperandVector &Operands,
MCInst &Inst,
uint64_t &ErrorInfo, bool matchingInlineAsm,
@@ -3615,19 +3614,6 @@ static const MatchEntry MatchTable0[] = {
{ 3152 /* xorcc */, Sparc::XORCCri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
};
-bool SparcAsmParser::
-mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) {
- // Find the appropriate table for this asm variant.
- const MatchEntry *Start, *End;
- switch (VariantID) {
- default: llvm_unreachable("invalid variant!");
- case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
- }
- // Search the table.
- auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
- return MnemonicRange.first != MnemonicRange.second;
-}
-
unsigned SparcAsmParser::
MatchInstructionImpl(const OperandVector &Operands,
MCInst &Inst, uint64_t &ErrorInfo,
diff --git a/llvm/lib/Target/SystemZ/SystemZGenAsmMatcher.inc b/llvm/lib/Target/SystemZ/SystemZGenAsmMatcher.inc
index a4e0e02..b579196 100644
--- a/llvm/lib/Target/SystemZ/SystemZGenAsmMatcher.inc
+++ b/llvm/lib/Target/SystemZ/SystemZGenAsmMatcher.inc
@@ -16,7 +16,6 @@
const OperandVector &Operands);
void convertToMapAndConstraints(unsigned Kind,
const OperandVector &Operands) override;
- bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID);
unsigned MatchInstructionImpl(const OperandVector &Operands,
MCInst &Inst,
uint64_t &ErrorInfo, bool matchingInlineAsm,
@@ -2703,19 +2702,6 @@ static const MatchEntry MatchTable0[] = {
{ 6335 /* xy */, SystemZ::XY, Convert__GR321_0__Tie0__BDXAddr64Disp203_1, 0, { MCK_GR32, MCK_BDXAddr64Disp20 }, },
};
-bool SystemZAsmParser::
-mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) {
- // Find the appropriate table for this asm variant.
- const MatchEntry *Start, *End;
- switch (VariantID) {
- default: llvm_unreachable("invalid variant!");
- case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
- }
- // Search the table.
- auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
- return MnemonicRange.first != MnemonicRange.second;
-}
-
unsigned SystemZAsmParser::
MatchInstructionImpl(const OperandVector &Operands,
MCInst &Inst, uint64_t &ErrorInfo,
--
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