SMPDataFlowAnalysis.cpp

SMPDefsFlags[NN_pminsw] = false;              // Packed Signed Integer Word Minimum
SMPDefsFlags[NN_pminub] = false;              // Packed Unsigned Integer Byte Minimum
SMPDefsFlags[NN_pmovmskb] = false;            // Move Byte Mask to Integer
SMPDefsFlags[NN_pmulhuw] = false;             // Packed Multiply High Unsigned
SMPDefsFlags[NN_psadbw] = false;              // Packed Sum of Absolute Differences
SMPDefsFlags[NN_pshufw] = false;              // Packed Shuffle Word
SMPDefsFlags[NN_maskmovq] = false;            // Byte Mask write  
SMPDefsFlags[NN_movntps] = false;             // Move Aligned Four Packed Single-FP Non Temporal
SMPDefsFlags[NN_movntq] = false;              // Move 64 Bits Non Temporal   
SMPDefsFlags[NN_prefetcht0] = false;          // Prefetch to all cache levels
SMPDefsFlags[NN_prefetcht1] = false;          // Prefetch to all cache levels
SMPDefsFlags[NN_prefetcht2] = false;          // Prefetch to L2 cache
SMPDefsFlags[NN_prefetchnta] = false;         // Prefetch to L1 cache
SMPDefsFlags[NN_sfence] = false;              // Store Fence

// Pentium III Pseudo instructions

SMPDefsFlags[NN_cmpeqps] = false;             // Packed Single-FP Compare EQ
SMPDefsFlags[NN_cmpltps] = false;             // Packed Single-FP Compare LT
SMPDefsFlags[NN_cmpleps] = false;             // Packed Single-FP Compare LE
SMPDefsFlags[NN_cmpunordps] = false;          // Packed Single-FP Compare UNORD
SMPDefsFlags[NN_cmpneqps] = false;            // Packed Single-FP Compare NOT EQ
SMPDefsFlags[NN_cmpnltps] = false;            // Packed Single-FP Compare NOT LT
SMPDefsFlags[NN_cmpnleps] = false;            // Packed Single-FP Compare NOT LE
SMPDefsFlags[NN_cmpordps] = false;            // Packed Single-FP Compare ORDERED
SMPDefsFlags[NN_cmpeqss] = false;             // Scalar Single-FP Compare EQ
SMPDefsFlags[NN_cmpltss] = false;             // Scalar Single-FP Compare LT
SMPDefsFlags[NN_cmpless] = false;             // Scalar Single-FP Compare LE
SMPDefsFlags[NN_cmpunordss] = false;          // Scalar Single-FP Compare UNORD
SMPDefsFlags[NN_cmpneqss] = false;            // Scalar Single-FP Compare NOT EQ
SMPDefsFlags[NN_cmpnltss] = false;            // Scalar Single-FP Compare NOT LT
SMPDefsFlags[NN_cmpnless] = false;            // Scalar Single-FP Compare NOT LE
SMPDefsFlags[NN_cmpordss] = false;            // Scalar Single-FP Compare ORDERED

// AMD K7 instructions

// Revisit AMD if we port to it.
SMPDefsFlags[NN_pf2iw] = false;               // Packed Floating-Point to Integer with Sign Extend
SMPDefsFlags[NN_pfnacc] = false;              // Packed Floating-Point Negative Accumulate
SMPDefsFlags[NN_pfpnacc] = false;             // Packed Floating-Point Mixed Positive-Negative Accumulate
SMPDefsFlags[NN_pi2fw] = false;               // Packed 16-bit Integer to Floating-Point
SMPDefsFlags[NN_pswapd] = false;              // Packed Swap Double Word

// Undocumented FP instructions (thanks to norbert.juffa@adm.com)

SMPDefsFlags[NN_fstp1] = false;               // Alias of Store Real and Pop
SMPDefsFlags[NN_fxch4] = false;               // Alias of Exchange Registers
SMPDefsFlags[NN_ffreep] = false;              // Free Register and Pop
SMPDefsFlags[NN_fxch7] = false;               // Alias of Exchange Registers
SMPDefsFlags[NN_fstp8] = false;               // Alias of Store Real and Pop
SMPDefsFlags[NN_fstp9] = false;               // Alias of Store Real and Pop

// Pentium 4 instructions

SMPDefsFlags[NN_addpd] = false;               // Add Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_addsd] = false;               // Add Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_andnpd] = false;              // Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_andpd] = false;               // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_clflush] = false;             // Flush Cache Line
SMPDefsFlags[NN_cmppd] = false;               // Compare Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_cmpsd] = false;               // Compare Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_cvtdq2pd] = false;            // Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_cvtdq2ps] = false;            // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_cvtpd2dq] = false;            // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_cvtpd2pi] = false;            // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_cvtpd2ps] = false;            // Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_cvtpi2pd] = false;            // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_cvtps2dq] = false;            // Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_cvtps2pd] = false;            // Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_cvtsd2si] = false;            // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
SMPDefsFlags[NN_cvtsd2ss] = false;            // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
SMPDefsFlags[NN_cvtsi2sd] = false;            // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_cvtss2sd] = false;            // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_cvttpd2dq] = false;           // Convert With Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_cvttpd2pi] = false;           // Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_cvttps2dq] = false;           // Convert With Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_cvttsd2si] = false;           // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
SMPDefsFlags[NN_divpd] = false;               // Divide Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_divsd] = false;               // Divide Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_lfence] = false;              // Load Fence
SMPDefsFlags[NN_maskmovdqu] = false;          // Store Selected Bytes of Double Quadword 
SMPDefsFlags[NN_maxpd] = false;               // Return Maximum Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_maxsd] = false;               // Return Maximum Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_mfence] = false;              // Memory Fence
SMPDefsFlags[NN_minpd] = false;               // Return Minimum Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_minsd] = false;               // Return Minimum Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_movapd] = false;              // Move Aligned Packed Double-Precision Floating-Point Values 
SMPDefsFlags[NN_movdq2q] = false;             // Move Quadword from XMM to MMX Register
SMPDefsFlags[NN_movdqa] = false;              // Move Aligned Double Quadword  
SMPDefsFlags[NN_movdqu] = false;              // Move Unaligned Double Quadword  
SMPDefsFlags[NN_movhpd] = false;              // Move High Packed Double-Precision Floating-Point Values 
SMPDefsFlags[NN_movlpd] = false;              // Move Low Packed Double-Precision Floating-Point Values 
SMPDefsFlags[NN_movmskpd] = false;            // Extract Packed Double-Precision Floating-Point Sign Mask
SMPDefsFlags[NN_movntdq] = false;             // Store Double Quadword Using Non-Temporal Hint
SMPDefsFlags[NN_movnti] = false;              // Store Doubleword Using Non-Temporal Hint
SMPDefsFlags[NN_movntpd] = false;             // Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
SMPDefsFlags[NN_movq2dq] = false;             // Move Quadword from MMX to XMM Register
SMPDefsFlags[NN_movsd] = false;               // Move Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_movupd] = false;              // Move Unaligned Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_mulpd] = false;               // Multiply Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_mulsd] = false;               // Multiply Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_orpd] = false;                // Bitwise Logical OR of Double-Precision Floating-Point Values
SMPDefsFlags[NN_paddq] = false;               // Add Packed Quadword Integers
SMPDefsFlags[NN_pause] = false;               // Spin Loop Hint
SMPDefsFlags[NN_pmuludq] = false;             // Multiply Packed Unsigned Doubleword Integers
SMPDefsFlags[NN_pshufd] = false;              // Shuffle Packed Doublewords
SMPDefsFlags[NN_pshufhw] = false;             // Shuffle Packed High Words
SMPDefsFlags[NN_pshuflw] = false;             // Shuffle Packed Low Words
SMPDefsFlags[NN_pslldq] = false;              // Shift Double Quadword Left Logical
SMPDefsFlags[NN_psrldq] = false;              // Shift Double Quadword Right Logical
SMPDefsFlags[NN_psubq] = false;               // Subtract Packed Quadword Integers
SMPDefsFlags[NN_punpckhqdq] = false;          // Unpack High Data
SMPDefsFlags[NN_punpcklqdq] = false;          // Unpack Low Data
SMPDefsFlags[NN_shufpd] = false;              // Shuffle Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_sqrtpd] = false;              // Compute Square Roots of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_sqrtsd] = false;              // Compute Square Rootof Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_subpd] = false;               // Subtract Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_subsd] = false;               // Subtract Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_unpckhpd] = false;            // Unpack and Interleave High Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_unpcklpd] = false;            // Unpack and Interleave Low Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_xorpd] = false;               // Bitwise Logical OR of Double-Precision Floating-Point Values


// AMD syscall/sysret instructions  NOTE: not AMD, found in Intel manual


// AMD64 instructions    NOTE: not AMD, found in Intel manual

SMPDefsFlags[NN_swapgs] = false;              // Exchange GS base with KernelGSBase MSR

// New Pentium instructions (SSE3)

SMPDefsFlags[NN_movddup] = false;             // Move One Double-FP and Duplicate
SMPDefsFlags[NN_movshdup] = false;            // Move Packed Single-FP High and Duplicate
SMPDefsFlags[NN_movsldup] = false;            // Move Packed Single-FP Low and Duplicate

// Missing AMD64 instructions  NOTE: also found in Intel manual

SMPDefsFlags[NN_movsxd] = false;              // Move with Sign-Extend Doubleword

// SSE3 instructions

SMPDefsFlags[NN_addsubpd] = false;            // Add /Sub packed DP FP numbers
SMPDefsFlags[NN_addsubps] = false;            // Add /Sub packed SP FP numbers
SMPDefsFlags[NN_haddpd] = false;              // Add horizontally packed DP FP numbers
SMPDefsFlags[NN_haddps] = false;              // Add horizontally packed SP FP numbers
SMPDefsFlags[NN_hsubpd] = false;              // Sub horizontally packed DP FP numbers
SMPDefsFlags[NN_hsubps] = false;              // Sub horizontally packed SP FP numbers
SMPDefsFlags[NN_monitor] = false;             // Set up a linear address range to be monitored by hardware
SMPDefsFlags[NN_mwait] = false;               // Wait until write-back store performed within the range specified by the MONITOR instruction
SMPDefsFlags[NN_fisttp] = false;              // Store ST in intXX (chop) and pop
SMPDefsFlags[NN_lddqu] = false;               // Load unaligned integer 128-bit

// SSSE3 instructions

SMPDefsFlags[NN_psignb] = false;              // Packed SIGN Byte
SMPDefsFlags[NN_psignw] = false;              // Packed SIGN Word
SMPDefsFlags[NN_psignd] = false;              // Packed SIGN Doubleword
SMPDefsFlags[NN_pshufb] = false;              // Packed Shuffle Bytes
SMPDefsFlags[NN_pmulhrsw] = false;            // Packed Multiply High with Round and Scale
SMPDefsFlags[NN_pmaddubsw] = false;           // Multiply and Add Packed Signed and Unsigned Bytes
SMPDefsFlags[NN_phsubsw] = false;             // Packed Horizontal Subtract and Saturate
SMPDefsFlags[NN_phaddsw] = false;             // Packed Horizontal Add and Saturate
SMPDefsFlags[NN_phaddw] = false;              // Packed Horizontal Add Word
SMPDefsFlags[NN_phaddd] = false;              // Packed Horizontal Add Doubleword
SMPDefsFlags[NN_phsubw] = false;              // Packed Horizontal Subtract Word
SMPDefsFlags[NN_phsubd] = false;              // Packed Horizontal Subtract Doubleword
SMPDefsFlags[NN_palignr] = false;             // Packed Align Right
SMPDefsFlags[NN_pabsb] = false;               // Packed Absolute Value Byte
SMPDefsFlags[NN_pabsw] = false;               // Packed Absolute Value Word
SMPDefsFlags[NN_pabsd] = false;               // Packed Absolute Value Doubleword

// VMX instructions

#if 599 < IDA_SDK_VERSION

SMPDefsFlags[NN_ud2] = false;                 // Undefined Instruction

// Added with x86-64

SMPDefsFlags[NN_rdtscp] = false;              // Read Time-Stamp Counter and Processor ID

// Geode LX 3DNow! extensions

SMPDefsFlags[NN_pfrcpv] = false;              // Reciprocal Approximation for a Pair of 32-bit Floats
SMPDefsFlags[NN_pfrsqrtv] = false;            // Reciprocal Square Root Approximation for a Pair of 32-bit Floats

// SSE2 pseudoinstructions

SMPDefsFlags[NN_cmpeqpd] = false;             // Packed Double-FP Compare EQ
SMPDefsFlags[NN_cmpltpd] = false;             // Packed Double-FP Compare LT
SMPDefsFlags[NN_cmplepd] = false;             // Packed Double-FP Compare LE
SMPDefsFlags[NN_cmpunordpd] = false;          // Packed Double-FP Compare UNORD
SMPDefsFlags[NN_cmpneqpd] = false;            // Packed Double-FP Compare NOT EQ
SMPDefsFlags[NN_cmpnltpd] = false;            // Packed Double-FP Compare NOT LT
SMPDefsFlags[NN_cmpnlepd] = false;            // Packed Double-FP Compare NOT LE
SMPDefsFlags[NN_cmpordpd] = false;            // Packed Double-FP Compare ORDERED
SMPDefsFlags[NN_cmpeqsd] = false;             // Scalar Double-FP Compare EQ
SMPDefsFlags[NN_cmpltsd] = false;             // Scalar Double-FP Compare LT
SMPDefsFlags[NN_cmplesd] = false;             // Scalar Double-FP Compare LE
SMPDefsFlags[NN_cmpunordsd] = false;          // Scalar Double-FP Compare UNORD
SMPDefsFlags[NN_cmpneqsd] = false;            // Scalar Double-FP Compare NOT EQ
SMPDefsFlags[NN_cmpnltsd] = false;            // Scalar Double-FP Compare NOT LT
SMPDefsFlags[NN_cmpnlesd] = false;            // Scalar Double-FP Compare NOT LE
SMPDefsFlags[NN_cmpordsd] = false;            // Scalar Double-FP Compare ORDERED

// SSSE4.1 instructions

SMPDefsFlags[NN_blendpd] = false;              // Blend Packed Double Precision Floating-Point Values
SMPDefsFlags[NN_blendps] = false;              // Blend Packed Single Precision Floating-Point Values
SMPDefsFlags[NN_blendvpd] = false;             // Variable Blend Packed Double Precision Floating-Point Values
SMPDefsFlags[NN_blendvps] = false;             // Variable Blend Packed Single Precision Floating-Point Values
SMPDefsFlags[NN_dppd] = false;                 // Dot Product of Packed Double Precision Floating-Point Values
SMPDefsFlags[NN_dpps] = false;                 // Dot Product of Packed Single Precision Floating-Point Values
SMPDefsFlags[NN_extractps] = 2;            // Extract Packed Single Precision Floating-Point Value
SMPDefsFlags[NN_insertps] = false;             // Insert Packed Single Precision Floating-Point Value
SMPDefsFlags[NN_movntdqa] = false;             // Load Double Quadword Non-Temporal Aligned Hint
SMPDefsFlags[NN_mpsadbw] = false;              // Compute Multiple Packed Sums of Absolute Difference
SMPDefsFlags[NN_packusdw] = false;             // Pack with Unsigned Saturation
SMPDefsFlags[NN_pblendvb] = false;             // Variable Blend Packed Bytes
SMPDefsFlags[NN_pblendw] = false;              // Blend Packed Words
SMPDefsFlags[NN_pcmpeqq] = false;              // Compare Packed Qword Data for Equal
SMPDefsFlags[NN_pextrb] = false;               // Extract Byte
SMPDefsFlags[NN_pextrd] = false;               // Extract Dword
SMPDefsFlags[NN_pextrq] = false;               // Extract Qword
SMPDefsFlags[NN_phminposuw] = false;           // Packed Horizontal Word Minimum
SMPDefsFlags[NN_pinsrb] = false;               // Insert Byte
SMPDefsFlags[NN_pinsrd] = false;               // Insert Dword
SMPDefsFlags[NN_pinsrq] = false;               // Insert Qword
SMPDefsFlags[NN_pmaxsb] = false;               // Maximum of Packed Signed Byte Integers
SMPDefsFlags[NN_pmaxsd] = false;               // Maximum of Packed Signed Dword Integers
SMPDefsFlags[NN_pmaxud] = false;               // Maximum of Packed Unsigned Dword Integers
SMPDefsFlags[NN_pmaxuw] = false;               // Maximum of Packed Word Integers
SMPDefsFlags[NN_pminsb] = false;               // Minimum of Packed Signed Byte Integers
SMPDefsFlags[NN_pminsd] = false;               // Minimum of Packed Signed Dword Integers
SMPDefsFlags[NN_pminud] = false;               // Minimum of Packed Unsigned Dword Integers
SMPDefsFlags[NN_pminuw] = false;               // Minimum of Packed Word Integers
SMPDefsFlags[NN_pmovsxbw] = false;             // Packed Move with Sign Extend
SMPDefsFlags[NN_pmovsxbd] = false;             // Packed Move with Sign Extend
SMPDefsFlags[NN_pmovsxbq] = false;             // Packed Move with Sign Extend
SMPDefsFlags[NN_pmovsxwd] = false;             // Packed Move with Sign Extend
SMPDefsFlags[NN_pmovsxwq] = false;             // Packed Move with Sign Extend
SMPDefsFlags[NN_pmovsxdq] = false;             // Packed Move with Sign Extend
SMPDefsFlags[NN_pmovzxbw] = false;             // Packed Move with Zero Extend
SMPDefsFlags[NN_pmovzxbd] = false;             // Packed Move with Zero Extend
SMPDefsFlags[NN_pmovzxbq] = false;             // Packed Move with Zero Extend
SMPDefsFlags[NN_pmovzxwd] = false;             // Packed Move with Zero Extend
SMPDefsFlags[NN_pmovzxwq] = false;             // Packed Move with Zero Extend
SMPDefsFlags[NN_pmovzxdq] = false;             // Packed Move with Zero Extend
SMPDefsFlags[NN_pmuldq] = false;               // Multiply Packed Signed Dword Integers
SMPDefsFlags[NN_pmulld] = false;               // Multiply Packed Signed Dword Integers and Store Low Result
SMPDefsFlags[NN_roundpd] = false;              // Round Packed Double Precision Floating-Point Values
SMPDefsFlags[NN_roundps] = false;              // Round Packed Single Precision Floating-Point Values
SMPDefsFlags[NN_roundsd] = false;              // Round Scalar Double Precision Floating-Point Values
SMPDefsFlags[NN_roundss] = false;              // Round Scalar Single Precision Floating-Point Values

// SSSE4.2 instructions
SMPDefsFlags[NN_crc32] = false;                // Accumulate CRC32 Value
SMPDefsFlags[NN_pcmpgtq] = false;              // Compare Packed Data for Greater Than

// AMD SSE4a instructions

SMPDefsFlags[NN_extrq] = false;                // Extract Field From Register
SMPDefsFlags[NN_insertq] = false;              // Insert Field
SMPDefsFlags[NN_movntsd] = false;              // Move Non-Temporal Scalar Double-Precision Floating-Point
SMPDefsFlags[NN_movntss] = false;              // Move Non-Temporal Scalar Single-Precision Floating-Point

// xsave/xrstor instructions

SMPDefsFlags[NN_xgetbv] = false;               // Get Value of Extended Control Register
SMPDefsFlags[NN_xrstor] = false;               // Restore Processor Extended States
SMPDefsFlags[NN_xsave] = false;                // Save Processor Extended States
SMPDefsFlags[NN_xsetbv] = false;               // Set Value of Extended Control Register

// Intel Safer Mode Extensions (SMX)

// AMD-V Virtualization ISA Extension

SMPDefsFlags[NN_invlpga] = false;              // Invalidate TLB Entry in a Specified ASID
SMPDefsFlags[NN_skinit] = false;               // Secure Init and Jump with Attestation
SMPDefsFlags[NN_vmexit] = false;               // Stop Executing Guest, Begin Executing Host
SMPDefsFlags[NN_vmload] = false;               // Load State from VMCB
SMPDefsFlags[NN_vmmcall] = false;              // Call VMM
SMPDefsFlags[NN_vmrun] = false;                // Run Virtual Machine
SMPDefsFlags[NN_vmsave] = false;               // Save State to VMCB

// VMX+ instructions

SMPDefsFlags[NN_invept] = false;               // Invalidate Translations Derived from EPT
SMPDefsFlags[NN_invvpid] = false;              // Invalidate Translations Based on VPID

// Intel Atom instructions

SMPDefsFlags[NN_movbe] = false;                // Move Data After Swapping Bytes

// Intel AES instructions

SMPDefsFlags[NN_aesenc] = false;                // Perform One Round of an AES Encryption Flow
SMPDefsFlags[NN_aesenclast] = false;            // Perform the Last Round of an AES Encryption Flow
SMPDefsFlags[NN_aesdec] = false;                // Perform One Round of an AES Decryption Flow
SMPDefsFlags[NN_aesdeclast] = false;            // Perform the Last Round of an AES Decryption Flow
SMPDefsFlags[NN_aesimc] = false;                // Perform the AES InvMixColumn Transformation
SMPDefsFlags[NN_aeskeygenassist] = false;       // AES Round Key Generation Assist

// Carryless multiplication

SMPDefsFlags[NN_pclmulqdq] = false;            // Carry-Less Multiplication Quadword

// Returns modified by operand size prefixes

SMPDefsFlags[NN_retnw] = false;               // Return Near from Procedure (use16)
SMPDefsFlags[NN_retnd] = false;               // Return Near from Procedure (use32)
SMPDefsFlags[NN_retnq] = false;               // Return Near from Procedure (use64)
SMPDefsFlags[NN_retfw] = false;               // Return Far from Procedure (use16)
SMPDefsFlags[NN_retfd] = false;               // Return Far from Procedure (use32)
SMPDefsFlags[NN_retfq] = false;               // Return Far from Procedure (use64)

// RDRAND support

// new GPR instructions

SMPDefsFlags[NN_mulx] = false;                 // Unsigned Multiply Without Affecting Flags
SMPDefsFlags[NN_pdep] = false;                 // Parallel Bits Deposit
SMPDefsFlags[NN_pext] = false;                 // Parallel Bits Extract
SMPDefsFlags[NN_rorx] = false;                 // Rotate Right Logical Without Affecting Flags
SMPDefsFlags[NN_sarx] = false;                 // Shift Arithmetically Right Without Affecting Flags
SMPDefsFlags[NN_shlx] = false;                 // Shift Logically Left Without Affecting Flags
SMPDefsFlags[NN_shrx] = false;                 // Shift Logically Right Without Affecting Flags

SMPDefsFlags[NN_xsaveopt] = false;             // Save Processor Extended States Optimized
SMPDefsFlags[NN_invpcid] =  false;             // Invalidate Processor Context ID
SMPDefsFlags[NN_rdseed] = false;               // Read Random Seed
SMPDefsFlags[NN_rdfsbase] = false;             // Read FS Segment Base
SMPDefsFlags[NN_rdgsbase] = false;             // Read GS Segment Base
SMPDefsFlags[NN_wrfsbase] = false;             // Write FS Segment Base
SMPDefsFlags[NN_wrgsbase] = false;             // Write GS Segment Base

// new AVX instructions

SMPDefsFlags[NN_vaddpd] = false;               // Add Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vaddps] = false;               // Packed Single-FP Add
SMPDefsFlags[NN_vaddsd] = false;               // Add Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vaddss] = false;               // Scalar Single-FP Add
SMPDefsFlags[NN_vaddsubpd] = false;            // Add /Sub packed DP FP numbers
SMPDefsFlags[NN_vaddsubps] = false;            // Add /Sub packed SP FP numbers
SMPDefsFlags[NN_vaesdec] = false;              // Perform One Round of an AES Decryption Flow
SMPDefsFlags[NN_vaesdeclast] = false;          // Perform the Last Round of an AES Decryption Flow
SMPDefsFlags[NN_vaesenc] = false;              // Perform One Round of an AES Encryption Flow
SMPDefsFlags[NN_vaesenclast] = false;          // Perform the Last Round of an AES Encryption Flow
SMPDefsFlags[NN_vaesimc] = false;              // Perform the AES InvMixColumn Transformation
SMPDefsFlags[NN_vaeskeygenassist] = false;     // AES Round Key Generation Assist
SMPDefsFlags[NN_vandnpd] = false;              // Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vandnps] = false;              // Bitwise Logical And Not for Single-FP
SMPDefsFlags[NN_vandpd] = false;               // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vandps] = false;               // Bitwise Logical And for Single-FP
SMPDefsFlags[NN_vblendpd] = false;             // Blend Packed Double Precision Floating-Point Values
SMPDefsFlags[NN_vblendps] = false;             // Blend Packed Single Precision Floating-Point Values
SMPDefsFlags[NN_vblendvpd] = false;            // Variable Blend Packed Double Precision Floating-Point Values
SMPDefsFlags[NN_vblendvps] = false;            // Variable Blend Packed Single Precision Floating-Point Values
SMPDefsFlags[NN_vbroadcastf128] = false;       // Broadcast 128 Bits of Floating-Point Data
SMPDefsFlags[NN_vbroadcasti128] = false;       // Broadcast 128 Bits of Integer Data
SMPDefsFlags[NN_vbroadcastsd] = false;         // Broadcast Double-Precision Floating-Point Element
SMPDefsFlags[NN_vbroadcastss] = false;         // Broadcast Single-Precision Floating-Point Element
SMPDefsFlags[NN_vcmppd] = false;               // Compare Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vcmpps] = false;               // Packed Single-FP Compare
SMPDefsFlags[NN_vcmpsd] = false;               // Compare Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vcmpss] = false;               // Scalar Single-FP Compare
SMPDefsFlags[NN_vcomisd] = false;              // Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
SMPDefsFlags[NN_vcomiss] = false;              // Scalar Ordered Single-FP Compare and Set EFLAGS
SMPDefsFlags[NN_vcvtdq2pd] = false;            // Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vcvtdq2ps] = false;            // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vcvtpd2dq] = false;            // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_vcvtpd2ps] = false;            // Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vcvtph2ps] = false;            // Convert 16-bit FP Values to Single-Precision FP Values
SMPDefsFlags[NN_vcvtps2dq] = false;            // Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_vcvtps2pd] = false;            // Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vcvtps2ph] = false;            // Convert Single-Precision FP value to 16-bit FP value
SMPDefsFlags[NN_vcvtsd2si] = false;            // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
SMPDefsFlags[NN_vcvtsd2ss] = false;            // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
SMPDefsFlags[NN_vcvtsi2sd] = false;            // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_vcvtsi2ss] = false;            // Scalar signed INT32 to Single-FP conversion
SMPDefsFlags[NN_vcvtss2sd] = false;            // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_vcvtss2si] = false;            // Scalar Single-FP to signed INT32 conversion
SMPDefsFlags[NN_vcvttpd2dq] = false;           // Convert With Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_vcvttps2dq] = false;           // Convert With Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_vcvttsd2si] = false;           // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
SMPDefsFlags[NN_vcvttss2si] = false;           // Scalar Single-FP to signed INT32 conversion (truncate)
SMPDefsFlags[NN_vdivpd] = false;               // Divide Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vdivps] = false;               // Packed Single-FP Divide
SMPDefsFlags[NN_vdivsd] = false;               // Divide Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vdivss] = false;               // Scalar Single-FP Divide
SMPDefsFlags[NN_vdppd] = false;                // Dot Product of Packed Double Precision Floating-Point Values
SMPDefsFlags[NN_vdpps] = false;                // Dot Product of Packed Single Precision Floating-Point Values
SMPDefsFlags[NN_vextractf128] = false;         // Extract Packed Floating-Point Values
SMPDefsFlags[NN_vextracti128] = false;         // Extract Packed Integer Values
SMPDefsFlags[NN_vextractps] = false;           // Extract Packed Floating-Point Values
SMPDefsFlags[NN_vfmadd132pd] = false;          // Fused Multiply-Add of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmadd132ps] = false;          // Fused Multiply-Add of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmadd132sd] = false;          // Fused Multiply-Add of Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmadd132ss] = false;          // Fused Multiply-Add of Scalar Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmadd213pd] = false;          // Fused Multiply-Add of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmadd213ps] = false;          // Fused Multiply-Add of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmadd213sd] = false;          // Fused Multiply-Add of Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmadd213ss] = false;          // Fused Multiply-Add of Scalar Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmadd231pd] = false;          // Fused Multiply-Add of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmadd231ps] = false;          // Fused Multiply-Add of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmadd231sd] = false;          // Fused Multiply-Add of Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmadd231ss] = false;          // Fused Multiply-Add of Scalar Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmaddsub132pd] = false;       // Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmaddsub132ps] = false;       // Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmaddsub213pd] = false;       // Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmaddsub213ps] = false;       // Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmaddsub231pd] = false;       // Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmaddsub231ps] = false;       // Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsub132pd] = false;          // Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsub132ps] = false;          // Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsub132sd] = false;          // Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsub132ss] = false;          // Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsub213pd] = false;          // Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsub213ps] = false;          // Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsub213sd] = false;          // Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsub213ss] = false;          // Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsub231pd] = false;          // Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsub231ps] = false;          // Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsub231sd] = false;          // Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsub231ss] = false;          // Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsubadd132pd] = false;       // Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsubadd132ps] = false;       // Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsubadd213pd] = false;       // Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsubadd213ps] = false;       // Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsubadd231pd] = false;       // Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfmsubadd231ps] = false;       // Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmadd132pd] = false;         // Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmadd132ps] = false;         // Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmadd132sd] = false;         // Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmadd132ss] = false;         // Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmadd213pd] = false;         // Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmadd213ps] = false;         // Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmadd213sd] = false;         // Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmadd213ss] = false;         // Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmadd231pd] = false;         // Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmadd231ps] = false;         // Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmadd231sd] = false;         // Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmadd231ss] = false;         // Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmsub132pd] = false;         // Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmsub132ps] = false;         // Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmsub132sd] = false;         // Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmsub132ss] = false;         // Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmsub213pd] = false;         // Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmsub213ps] = false;         // Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmsub213sd] = false;         // Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmsub213ss] = false;         // Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmsub231pd] = false;         // Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmsub231ps] = false;         // Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmsub231sd] = false;         // Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vfnmsub231ss] = false;         // Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values
SMPDefsFlags[NN_vgatherdps] = false;           // Gather Packed SP FP Values Using Signed Dword Indices
SMPDefsFlags[NN_vgatherdpd] = false;           // Gather Packed DP FP Values Using Signed Dword Indices
SMPDefsFlags[NN_vgatherqps] = false;           // Gather Packed SP FP Values Using Signed Qword Indices
SMPDefsFlags[NN_vgatherqpd] = false;           // Gather Packed DP FP Values Using Signed Qword Indices
SMPDefsFlags[NN_vhaddpd] = false;              // Add horizontally packed DP FP numbers
SMPDefsFlags[NN_vhaddps] = false;              // Add horizontally packed SP FP numbers
SMPDefsFlags[NN_vhsubpd] = false;              // Sub horizontally packed DP FP numbers
SMPDefsFlags[NN_vhsubps] = false;              // Sub horizontally packed SP FP numbers
SMPDefsFlags[NN_vinsertf128] = false;          // Insert Packed Floating-Point Values
SMPDefsFlags[NN_vinserti128] = false;          // Insert Packed Integer Values
SMPDefsFlags[NN_vinsertps] = false;            // Insert Packed Single Precision Floating-Point Value
SMPDefsFlags[NN_vlddqu] = false;               // Load Unaligned Packed Integer Values
SMPDefsFlags[NN_vldmxcsr] = false;             // Load Streaming SIMD Extensions Technology Control/Status Register
SMPDefsFlags[NN_vmaskmovdqu] = false;          // Store Selected Bytes of Double Quadword with NT Hint
SMPDefsFlags[NN_vmaskmovpd] = false;           // Conditionally Load Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vmaskmovps] = false;           // Conditionally Load Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_vmaxpd] = false;               // Return Maximum Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vmaxps] = false;               // Packed Single-FP Maximum
SMPDefsFlags[NN_vmaxsd] = false;               // Return Maximum Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_vmaxss] = false;               // Scalar Single-FP Maximum
SMPDefsFlags[NN_vminpd] = false;               // Return Minimum Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vminps] = false;               // Packed Single-FP Minimum
SMPDefsFlags[NN_vminsd] = false;               // Return Minimum Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_vminss] = false;               // Scalar Single-FP Minimum
SMPDefsFlags[NN_vmovapd] = false;              // Move Aligned Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vmovaps] = false;              // Move Aligned Four Packed Single-FP
SMPDefsFlags[NN_vmovd] = false;                // Move 32 bits
SMPDefsFlags[NN_vmovddup] = false;             // Move One Double-FP and Duplicate
SMPDefsFlags[NN_vmovdqa] = false;              // Move Aligned Double Quadword
SMPDefsFlags[NN_vmovdqu] = false;              // Move Unaligned Double Quadword
SMPDefsFlags[NN_vmovhlps] = false;             // Move High to Low Packed Single-FP
SMPDefsFlags[NN_vmovhpd] = false;              // Move High Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vmovhps] = false;              // Move High Packed Single-FP
SMPDefsFlags[NN_vmovlhps] = false;             // Move Low to High Packed Single-FP
SMPDefsFlags[NN_vmovlpd] = false;              // Move Low Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vmovlps] = false;              // Move Low Packed Single-FP
SMPDefsFlags[NN_vmovmskpd] = false;            // Extract Packed Double-Precision Floating-Point Sign Mask
SMPDefsFlags[NN_vmovmskps] = false;            // Move Mask to Register
SMPDefsFlags[NN_vmovntdq] = false;             // Store Double Quadword Using Non-Temporal Hint
SMPDefsFlags[NN_vmovntdqa] = false;            // Load Double Quadword Non-Temporal Aligned Hint
SMPDefsFlags[NN_vmovntpd] = false;             // Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
SMPDefsFlags[NN_vmovntps] = false;             // Move Aligned Four Packed Single-FP Non Temporal
SMPDefsFlags[NN_vmovntsd] = false;             // Move Non-Temporal Scalar Double-Precision Floating-Point
SMPDefsFlags[NN_vmovntss] = false;             // Move Non-Temporal Scalar Single-Precision Floating-Point
SMPDefsFlags[NN_vmovq] = false;                // Move 64 bits
SMPDefsFlags[NN_vmovsd] = false;               // Move Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vmovshdup] = false;            // Move Packed Single-FP High and Duplicate
SMPDefsFlags[NN_vmovsldup] = false;            // Move Packed Single-FP Low and Duplicate
SMPDefsFlags[NN_vmovss] = false;               // Move Scalar Single-FP
SMPDefsFlags[NN_vmovupd] = false;              // Move Unaligned Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vmovups] = false;              // Move Unaligned Four Packed Single-FP
SMPDefsFlags[NN_vmpsadbw] = false;             // Compute Multiple Packed Sums of Absolute Difference
SMPDefsFlags[NN_vmulpd] = false;               // Multiply Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vmulps] = false;               // Packed Single-FP Multiply
SMPDefsFlags[NN_vmulsd] = false;               // Multiply Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vmulss] = false;               // Scalar Single-FP Multiply
SMPDefsFlags[NN_vorpd] = false;                // Bitwise Logical OR of Double-Precision Floating-Point Values
SMPDefsFlags[NN_vorps] = false;                // Bitwise Logical OR for Single-FP Data
SMPDefsFlags[NN_vpabsb] = false;               // Packed Absolute Value Byte
SMPDefsFlags[NN_vpabsd] = false;               // Packed Absolute Value Doubleword
SMPDefsFlags[NN_vpabsw] = false;               // Packed Absolute Value Word
SMPDefsFlags[NN_vpackssdw] = false;            // Pack with Signed Saturation (Dword->Word)
SMPDefsFlags[NN_vpacksswb] = false;            // Pack with Signed Saturation (Word->Byte)
SMPDefsFlags[NN_vpackusdw] = false;            // Pack with Unsigned Saturation
SMPDefsFlags[NN_vpackuswb] = false;            // Pack with Unsigned Saturation (Word->Byte)
SMPDefsFlags[NN_vpaddb] = false;               // Packed Add Byte
SMPDefsFlags[NN_vpaddd] = false;               // Packed Add Dword
SMPDefsFlags[NN_vpaddq] = false;               // Add Packed Quadword Integers
SMPDefsFlags[NN_vpaddsb] = false;              // Packed Add with Saturation (Byte)
SMPDefsFlags[NN_vpaddsw] = false;              // Packed Add with Saturation (Word)
SMPDefsFlags[NN_vpaddusb] = false;             // Packed Add Unsigned with Saturation (Byte)
SMPDefsFlags[NN_vpaddusw] = false;             // Packed Add Unsigned with Saturation (Word)
SMPDefsFlags[NN_vpaddw] = false;               // Packed Add Word
SMPDefsFlags[NN_vpalignr] = false;             // Packed Align Right
SMPDefsFlags[NN_vpand] = false;                // Bitwise Logical And
SMPDefsFlags[NN_vpandn] = false;               // Bitwise Logical And Not
SMPDefsFlags[NN_vpavgb] = false;               // Packed Average (Byte)
SMPDefsFlags[NN_vpavgw] = false;               // Packed Average (Word)
SMPDefsFlags[NN_vpblendd] = false;             // Blend Packed Dwords
SMPDefsFlags[NN_vpblendvb] = false;            // Variable Blend Packed Bytes
SMPDefsFlags[NN_vpblendw] = false;             // Blend Packed Words
SMPDefsFlags[NN_vpbroadcastb] = false;         // Broadcast a Byte Integer
SMPDefsFlags[NN_vpbroadcastd] = false;         // Broadcast a Dword Integer
SMPDefsFlags[NN_vpbroadcastq] = false;         // Broadcast a Qword Integer
SMPDefsFlags[NN_vpbroadcastw] = false;         // Broadcast a Word Integer
SMPDefsFlags[NN_vpclmulqdq] = false;           // Carry-Less Multiplication Quadword
SMPDefsFlags[NN_vpcmpeqb] = false;             // Packed Compare for Equal (Byte)
SMPDefsFlags[NN_vpcmpeqd] = false;             // Packed Compare for Equal (Dword)
SMPDefsFlags[NN_vpcmpeqq] = false;             // Compare Packed Qword Data for Equal
SMPDefsFlags[NN_vpcmpeqw] = false;             // Packed Compare for Equal (Word)
SMPDefsFlags[NN_vpcmpestri] = false;           // Packed Compare Explicit Length Strings, Return Index
SMPDefsFlags[NN_vpcmpestrm] = false;           // Packed Compare Explicit Length Strings, Return Mask
SMPDefsFlags[NN_vpcmpgtb] = false;             // Packed Compare for Greater Than (Byte)
SMPDefsFlags[NN_vpcmpgtd] = false;             // Packed Compare for Greater Than (Dword)
SMPDefsFlags[NN_vpcmpgtq] = false;             // Compare Packed Data for Greater Than
SMPDefsFlags[NN_vpcmpgtw] = false;             // Packed Compare for Greater Than (Word)
SMPDefsFlags[NN_vpcmpistri] = false;           // Packed Compare Implicit Length Strings, Return Index
SMPDefsFlags[NN_vpcmpistrm] = false;           // Packed Compare Implicit Length Strings, Return Mask
SMPDefsFlags[NN_vperm2f128] = false;           // Permute Floating-Point Values
SMPDefsFlags[NN_vperm2i128] = false;           // Permute Integer Values
SMPDefsFlags[NN_vpermd] = false;               // Full Doublewords Element Permutation
SMPDefsFlags[NN_vpermilpd] = false;            // Permute Double-Precision Floating-Point Values
SMPDefsFlags[NN_vpermilps] = false;            // Permute Single-Precision Floating-Point Values
SMPDefsFlags[NN_vpermpd] = false;              // Permute Double-Precision Floating-Point Elements
SMPDefsFlags[NN_vpermps] = false;              // Permute Single-Precision Floating-Point Elements
SMPDefsFlags[NN_vpermq] = false;               // Qwords Element Permutation
SMPDefsFlags[NN_vpextrb] = false;              // Extract Byte
SMPDefsFlags[NN_vpextrd] = false;              // Extract Dword
SMPDefsFlags[NN_vpextrq] = false;              // Extract Qword
SMPDefsFlags[NN_vpextrw] = false;              // Extract Word
SMPDefsFlags[NN_vpgatherdd] = false;           // Gather Packed Dword Values Using Signed Dword Indices
SMPDefsFlags[NN_vpgatherdq] = false;           // Gather Packed Qword Values Using Signed Dword Indices
SMPDefsFlags[NN_vpgatherqd] = false;           // Gather Packed Dword Values Using Signed Qword Indices
SMPDefsFlags[NN_vpgatherqq] = false;           // Gather Packed Qword Values Using Signed Qword Indices
SMPDefsFlags[NN_vphaddd] = false;              // Packed Horizontal Add Doubleword
SMPDefsFlags[NN_vphaddsw] = false;          // Packed Horizontal Add and Saturate
SMPDefsFlags[NN_vphaddw] = false;           // Packed Horizontal Add Word
SMPDefsFlags[NN_vphminposuw] = false;       // Packed Horizontal Word Minimum
SMPDefsFlags[NN_vphsubd] = false;           // Packed Horizontal Subtract Doubleword
SMPDefsFlags[NN_vphsubsw] = false;          // Packed Horizontal Subtract and Saturate
SMPDefsFlags[NN_vphsubw] = false;           // Packed Horizontal Subtract Word
SMPDefsFlags[NN_vpinsrb] = false;           // Insert Byte
SMPDefsFlags[NN_vpinsrd] = false;           // Insert Dword
SMPDefsFlags[NN_vpinsrq] = false;           // Insert Qword
SMPDefsFlags[NN_vpinsrw] = false;           // Insert Word
SMPDefsFlags[NN_vpmaddubsw] = false;        // Multiply and Add Packed Signed and Unsigned Bytes
SMPDefsFlags[NN_vpmaddwd] = false;          // Packed Multiply and Add
SMPDefsFlags[NN_vpmaskmovd] = false;        // Conditionally Store Dword Values Using Mask
SMPDefsFlags[NN_vpmaskmovq] = false;        // Conditionally Store Qword Values Using Mask
SMPDefsFlags[NN_vpmaxsb] = false;           // Maximum of Packed Signed Byte Integers
SMPDefsFlags[NN_vpmaxsd] = false;           // Maximum of Packed Signed Dword Integers
SMPDefsFlags[NN_vpmaxsw] = false;           // Packed Signed Integer Word Maximum
SMPDefsFlags[NN_vpmaxub] = false;           // Packed Unsigned Integer Byte Maximum
SMPDefsFlags[NN_vpmaxud] = false;           // Maximum of Packed Unsigned Dword Integers
SMPDefsFlags[NN_vpmaxuw] = false;           // Maximum of Packed Word Integers
SMPDefsFlags[NN_vpminsb] = false;           // Minimum of Packed Signed Byte Integers
SMPDefsFlags[NN_vpminsd] = false;           // Minimum of Packed Signed Dword Integers
SMPDefsFlags[NN_vpminsw] = false;           // Packed Signed Integer Word Minimum
SMPDefsFlags[NN_vpminub] = false;           // Packed Unsigned Integer Byte Minimum
SMPDefsFlags[NN_vpminud] = false;           // Minimum of Packed Unsigned Dword Integers
SMPDefsFlags[NN_vpminuw] = false;           // Minimum of Packed Word Integers
SMPDefsFlags[NN_vpmovmskb] = false;         // Move Byte Mask to Integer
SMPDefsFlags[NN_vpmovsxbd] = false;         // Packed Move with Sign Extend
SMPDefsFlags[NN_vpmovsxbq] = false;         // Packed Move with Sign Extend
SMPDefsFlags[NN_vpmovsxbw] = false;         // Packed Move with Sign Extend
SMPDefsFlags[NN_vpmovsxdq] = false;         // Packed Move with Sign Extend
SMPDefsFlags[NN_vpmovsxwd] = false;         // Packed Move with Sign Extend
SMPDefsFlags[NN_vpmovsxwq] = false;         // Packed Move with Sign Extend
SMPDefsFlags[NN_vpmovzxbd] = false;         // Packed Move with Zero Extend
SMPDefsFlags[NN_vpmovzxbq] = false;         // Packed Move with Zero Extend
SMPDefsFlags[NN_vpmovzxbw] = false;         // Packed Move with Zero Extend
SMPDefsFlags[NN_vpmovzxdq] = false;         // Packed Move with Zero Extend
SMPDefsFlags[NN_vpmovzxwd] = false;         // Packed Move with Zero Extend
SMPDefsFlags[NN_vpmovzxwq] = false;         // Packed Move with Zero Extend
SMPDefsFlags[NN_vpmuldq] = false;           // Multiply Packed Signed Dword Integers
SMPDefsFlags[NN_vpmulhrsw] = false;         // Packed Multiply High with Round and Scale
SMPDefsFlags[NN_vpmulhuw] = false;          // Packed Multiply High Unsigned
SMPDefsFlags[NN_vpmulhw] = false;           // Packed Multiply High
SMPDefsFlags[NN_vpmulld] = false;           // Multiply Packed Signed Dword Integers and Store Low Result
SMPDefsFlags[NN_vpmullw] = false;           // Packed Multiply Low
SMPDefsFlags[NN_vpmuludq] = false;          // Multiply Packed Unsigned Doubleword Integers
SMPDefsFlags[NN_vpor] = false;              // Bitwise Logical Or
SMPDefsFlags[NN_vpsadbw] = false;           // Packed Sum of Absolute Differences
SMPDefsFlags[NN_vpshufb] = false;           // Packed Shuffle Bytes
SMPDefsFlags[NN_vpshufd] = false;           // Shuffle Packed Doublewords
SMPDefsFlags[NN_vpshufhw] = false;          // Shuffle Packed High Words
SMPDefsFlags[NN_vpshuflw] = false;          // Shuffle Packed Low Words
SMPDefsFlags[NN_vpsignb] = false;           // Packed SIGN Byte
SMPDefsFlags[NN_vpsignd] = false;           // Packed SIGN Doubleword
SMPDefsFlags[NN_vpsignw] = false;           // Packed SIGN Word
SMPDefsFlags[NN_vpslld] = false;            // Packed Shift Left Logical (Dword)
SMPDefsFlags[NN_vpslldq] = false;           // Shift Double Quadword Left Logical
SMPDefsFlags[NN_vpsllq] = false;            // Packed Shift Left Logical (Qword)
SMPDefsFlags[NN_vpsllvd] = false;           // Variable Bit Shift Left Logical (Dword)
SMPDefsFlags[NN_vpsllvq] = false;           // Variable Bit Shift Left Logical (Qword)
SMPDefsFlags[NN_vpsllw] = false;            // Packed Shift Left Logical (Word)
SMPDefsFlags[NN_vpsrad] = false;            // Packed Shift Right Arithmetic (Dword)
SMPDefsFlags[NN_vpsravd] = false;           // Variable Bit Shift Right Arithmetic
SMPDefsFlags[NN_vpsraw] = false;            // Packed Shift Right Arithmetic (Word)
SMPDefsFlags[NN_vpsrld] = false;            // Packed Shift Right Logical (Dword)
SMPDefsFlags[NN_vpsrldq] = false;           // Shift Double Quadword Right Logical (Qword)
SMPDefsFlags[NN_vpsrlq] = false;            // Packed Shift Right Logical (Qword)
SMPDefsFlags[NN_vpsrlvd] = false;           // Variable Bit Shift Right Logical (Dword)
SMPDefsFlags[NN_vpsrlvq] = false;           // Variable Bit Shift Right Logical (Qword)
SMPDefsFlags[NN_vpsrlw] = false;            // Packed Shift Right Logical (Word)
SMPDefsFlags[NN_vpsubb] = false;            // Packed Subtract Byte
SMPDefsFlags[NN_vpsubd] = false;            // Packed Subtract Dword
SMPDefsFlags[NN_vpsubq] = false;            // Subtract Packed Quadword Integers
SMPDefsFlags[NN_vpsubsb] = false;           // Packed Subtract with Saturation (Byte)
SMPDefsFlags[NN_vpsubsw] = false;           // Packed Subtract with Saturation (Word)
SMPDefsFlags[NN_vpsubusb] = false;          // Packed Subtract Unsigned with Saturation (Byte)
SMPDefsFlags[NN_vpsubusw] = false;          // Packed Subtract Unsigned with Saturation (Word)
SMPDefsFlags[NN_vpsubw] = false;            // Packed Subtract Word
SMPDefsFlags[NN_vptest] = false;            // Logical Compare
SMPDefsFlags[NN_vpunpckhbw] = false;        // Unpack High Packed Data (Byte->Word)
SMPDefsFlags[NN_vpunpckhdq] = false;        // Unpack High Packed Data (Dword->Qword)
SMPDefsFlags[NN_vpunpckhqdq] = false;       // Unpack High Packed Data (Qword->Xmmword)
SMPDefsFlags[NN_vpunpckhwd] = false;        // Unpack High Packed Data (Word->Dword)
SMPDefsFlags[NN_vpunpcklbw] = false;        // Unpack Low Packed Data (Byte->Word)
SMPDefsFlags[NN_vpunpckldq] = false;        // Unpack Low Packed Data (Dword->Qword)
SMPDefsFlags[NN_vpunpcklqdq] = false;       // Unpack Low Packed Data (Qword->Xmmword)
SMPDefsFlags[NN_vpunpcklwd] = false;        // Unpack Low Packed Data (Word->Dword)
SMPDefsFlags[NN_vpxor] = false;             // Bitwise Logical Exclusive Or
SMPDefsFlags[NN_vrcpps] = false;            // Packed Single-FP Reciprocal
SMPDefsFlags[NN_vrcpss] = false;            // Scalar Single-FP Reciprocal
SMPDefsFlags[NN_vroundpd] = false;          // Round Packed Double Precision Floating-Point Values
SMPDefsFlags[NN_vroundps] = false;          // Round Packed Single Precision Floating-Point Values
SMPDefsFlags[NN_vroundsd] = false;          // Round Scalar Double Precision Floating-Point Values
SMPDefsFlags[NN_vroundss] = false;          // Round Scalar Single Precision Floating-Point Values
SMPDefsFlags[NN_vrsqrtps] = false;          // Packed Single-FP Square Root Reciprocal
SMPDefsFlags[NN_vrsqrtss] = false;          // Scalar Single-FP Square Root Reciprocal
SMPDefsFlags[NN_vshufpd] = false;           // Shuffle Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vshufps] = false;           // Shuffle Single-FP
SMPDefsFlags[NN_vsqrtpd] = false;           // Compute Square Roots of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vsqrtps] = false;           // Packed Single-FP Square Root
SMPDefsFlags[NN_vsqrtsd] = false;           // Compute Square Rootof Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_vsqrtss] = false;           // Scalar Single-FP Square Root
SMPDefsFlags[NN_vstmxcsr] = false;          // Store Streaming SIMD Extensions Technology Control/Status Register
SMPDefsFlags[NN_vsubpd] = false;            // Subtract Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vsubps] = false;            // Packed Single-FP Subtract
SMPDefsFlags[NN_vsubsd] = false;            // Subtract Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_vsubss] = false;            // Scalar Single-FP Subtract
SMPDefsFlags[NN_vtestpd] = false;           // Packed Double-Precision Floating-Point Bit Test
SMPDefsFlags[NN_vtestps] = false;           // Packed Single-Precision Floating-Point Bit Test
SMPDefsFlags[NN_vucomisd] = false;          // Unordered Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
SMPDefsFlags[NN_vucomiss] = false;          // Scalar Unordered Single-FP Compare and Set EFLAGS
SMPDefsFlags[NN_vunpckhpd] = false;         // Unpack and Interleave High Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vunpckhps] = false;         // Unpack High Packed Single-FP Data
SMPDefsFlags[NN_vunpcklpd] = false;         // Unpack and Interleave Low Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_vunpcklps] = false;         // Unpack Low Packed Single-FP Data
SMPDefsFlags[NN_vxorpd] = false;            // Bitwise Logical OR of Double-Precision Floating-Point Values
SMPDefsFlags[NN_vxorps] = false;            // Bitwise Logical XOR for Single-FP Data
SMPDefsFlags[NN_vzeroall] = false;          // Zero All YMM Registers
SMPDefsFlags[NN_vzeroupper] = false;        // Zero Upper Bits of YMM Registers

// Transactional Synchronization Extensions

SMPDefsFlags[NN_xabort] = false;               // Transaction Abort
SMPDefsFlags[NN_xbegin] = false;               // Transaction Begin
SMPDefsFlags[NN_xend] = false;                 // Transaction End
SMPDefsFlags[NN_xtest] = false;                // Test If In Transactional Execution

// Virtual PC synthetic instructions

SMPDefsFlags[NN_vmgetinfo] = false;            // Virtual PC - Get VM Information
SMPDefsFlags[NN_vmsetinfo] = false;            // Virtual PC - Set VM Information
SMPDefsFlags[NN_vmdxdsbl] = false;             // Virtual PC - Disable Direct Execution
SMPDefsFlags[NN_vmdxenbl] = false;             // Virtual PC - Enable Direct Execution
SMPDefsFlags[NN_vmcpuid] = false;              // Virtual PC - Virtualized CPU Information
SMPDefsFlags[NN_vmhlt] = false;                // Virtual PC - Halt
SMPDefsFlags[NN_vmsplaf] = false;              // Virtual PC - Spin Lock Acquisition Failed
SMPDefsFlags[NN_vmpushfd] = false;             // Virtual PC - Push virtualized flags register
SMPDefsFlags[NN_vmpopfd] = false;              // Virtual PC - Pop virtualized flags register
SMPDefsFlags[NN_vmcli] = false;                // Virtual PC - Clear Interrupt Flag
SMPDefsFlags[NN_vmsti] = false;                // Virtual PC - Set Interrupt Flag
SMPDefsFlags[NN_vmiretd] = false;              // Virtual PC - Return From Interrupt
SMPDefsFlags[NN_vmsgdt] = false;               // Virtual PC - Store Global Descriptor Table
SMPDefsFlags[NN_vmsidt] = false;               // Virtual PC - Store Interrupt Descriptor Table
SMPDefsFlags[NN_vmsldt] = false;               // Virtual PC - Store Local Descriptor Table
SMPDefsFlags[NN_vmstr] = false;                // Virtual PC - Store Task Register
SMPDefsFlags[NN_vmsdte] = false;               // Virtual PC - Store to Descriptor Table Entry
SMPDefsFlags[NN_vpcext] = false;               // Virtual PC - ISA extension

#endif // 599 < IDA_SDK_VERSION

SMPDefsFlags[NN_last] = false;

  return;

} // end InitSMPDefsFlags()

// Initialize the SMPUsesFlags[] array to define how we emit
//   optimizing annotations.
void InitSMPUsesFlags(void) {
	// Default value is false. Few instructions use the flags.
	(void) memset(SMPUsesFlags, false, sizeof(SMPUsesFlags));

SMPUsesFlags[NN_null] = true;            // Unknown Operation
SMPUsesFlags[NN_aaa] = true;                 // ASCII adjust after addition
SMPUsesFlags[NN_aas] = true;				 // ASCII adjust after subtraction
SMPUsesFlags[NN_adc] = true;                 // Add with Carry
SMPUsesFlags[NN_cmps] = true;                // Compare Strings (uses DF direction flag)
SMPUsesFlags[NN_daa] = true;                 // Decimal Adjust AL after Addition
SMPUsesFlags[NN_das] = true;                 // Decimal Adjust AL after Subtraction
SMPUsesFlags[NN_ins] = true;                 // Input Byte(s) from Port to String        
SMPUsesFlags[NN_into] = true;                // Call to Interrupt Procedure if Overflow Flag = 1
SMPUsesFlags[NN_ja] = true;                  // Jump if Above (CF=0 & ZF=0)
SMPUsesFlags[NN_jae] = true;                 // Jump if Above or Equal (CF=0)
SMPUsesFlags[NN_jb] = true;                  // Jump if Below (CF=1)
SMPUsesFlags[NN_jbe] = true;                 // Jump if Below or Equal (CF=1 | ZF=1)
SMPUsesFlags[NN_jc] = true;                  // Jump if Carry (CF=1)
SMPUsesFlags[NN_jcxz] = true;                // Jump if CX is 0
SMPUsesFlags[NN_jecxz] = true;               // Jump if ECX is 0
SMPUsesFlags[NN_jrcxz] = true;               // Jump if RCX is 0
SMPUsesFlags[NN_je] = true;                  // Jump if Equal (ZF=1)
SMPUsesFlags[NN_jg] = true;                  // Jump if Greater (ZF=0 & SF=OF)
SMPUsesFlags[NN_jge] = true;                 // Jump if Greater or Equal (SF=OF)
SMPUsesFlags[NN_jl] = true;                  // Jump if Less (SF!=OF)
SMPUsesFlags[NN_jle] = true;                 // Jump if Less or Equal (ZF=1 | SF!=OF)
SMPUsesFlags[NN_jna] = true;                 // Jump if Not Above (CF=1 | ZF=1)
SMPUsesFlags[NN_jnae] = true;                // Jump if Not Above or Equal (CF=1)
SMPUsesFlags[NN_jnb] = true;                 // Jump if Not Below (CF=0)
SMPUsesFlags[NN_jnbe] = true;                // Jump if Not Below or Equal (CF=0 & ZF=0)
SMPUsesFlags[NN_jnc] = true;                 // Jump if Not Carry (CF=0)
SMPUsesFlags[NN_jne] = true;                 // Jump if Not Equal (ZF=0)
SMPUsesFlags[NN_jng] = true;                 // Jump if Not Greater (ZF=1 | SF!=OF)
SMPUsesFlags[NN_jnge] = true;                // Jump if Not Greater or Equal (ZF=1)
SMPUsesFlags[NN_jnl] = true;                 // Jump if Not Less (SF=OF)
SMPUsesFlags[NN_jnle] = true;                // Jump if Not Less or Equal (ZF=0 & SF=OF)
SMPUsesFlags[NN_jno] = true;                 // Jump if Not Overflow (OF=0)
SMPUsesFlags[NN_jnp] = true;                 // Jump if Not Parity (PF=0)
SMPUsesFlags[NN_jns] = true;                 // Jump if Not Sign (SF=0)
SMPUsesFlags[NN_jnz] = true;                 // Jump if Not Zero (ZF=0)
SMPUsesFlags[NN_jo] = true;                  // Jump if Overflow (OF=1)
SMPUsesFlags[NN_jp] = true;                  // Jump if Parity (PF=1)
SMPUsesFlags[NN_jpe] = true;                 // Jump if Parity Even (PF=1)
SMPUsesFlags[NN_jpo] = true;                 // Jump if Parity Odd  (PF=0)
SMPUsesFlags[NN_js] = true;                  // Jump if Sign (SF=1)
SMPUsesFlags[NN_jz] = true;                  // Jump if Zero (ZF=1)
SMPUsesFlags[NN_lahf] = true;                // Load Flags into AH Register
SMPUsesFlags[NN_lods] = true;                // Load String
SMPUsesFlags[NN_loopwe] = true;              // Loop while CX != 0 and ZF=1
SMPUsesFlags[NN_loope] = true;               // Loop while rCX != 0 and ZF=1
SMPUsesFlags[NN_loopde] = true;              // Loop while ECX != 0 and ZF=1
SMPUsesFlags[NN_loopqe] = true;              // Loop while RCX != 0 and ZF=1
SMPUsesFlags[NN_loopwne] = true;             // Loop while CX != 0 and ZF=0
SMPUsesFlags[NN_loopne] = true;              // Loop while rCX != 0 and ZF=0
SMPUsesFlags[NN_loopdne] = true;             // Loop while ECX != 0 and ZF=0
SMPUsesFlags[NN_loopqne] = true;             // Loop while RCX != 0 and ZF=0
SMPUsesFlags[NN_movs] = true;  		         // Move String (uses flags if REP prefix)
SMPUsesFlags[NN_outs] = true;                // Output Byte(s) to Port
SMPUsesFlags[NN_pushfw] = true;              // Push Flags Register onto the Stack
SMPUsesFlags[NN_pushf] = true;               // Push Flags Register onto the Stack
SMPUsesFlags[NN_pushfd] = true;              // Push Flags Register onto the Stack (use32)
SMPUsesFlags[NN_pushfq] = true;              // Push Flags Register onto the Stack (use64)
SMPUsesFlags[NN_rcl] = true;                 // Rotate Through Carry Left
SMPUsesFlags[NN_rcr] = true;                 // Rotate Through Carry Right
SMPUsesFlags[NN_repe] = true;                // Repeat String Operation while ZF=1
SMPUsesFlags[NN_repne] = true;               // Repeat String Operation while ZF=0
SMPUsesFlags[NN_sbb] = true;                 // Integer Subtraction with Borrow
SMPUsesFlags[NN_scas] = true;                // Compare String (uses DF direction flag)
SMPUsesFlags[NN_seta] = true;                // Set Byte if Above (CF=0 & ZF=0)
SMPUsesFlags[NN_setae] = true;               // Set Byte if Above or Equal (CF=0)
SMPUsesFlags[NN_setb] = true;                // Set Byte if Below (CF=1)
SMPUsesFlags[NN_setbe] = true;               // Set Byte if Below or Equal (CF=1 | ZF=1)
SMPUsesFlags[NN_setc] = true;                // Set Byte if Carry (CF=1)
SMPUsesFlags[NN_sete] = true;                // Set Byte if Equal (ZF=1)
SMPUsesFlags[NN_setg] = true;                // Set Byte if Greater (ZF=0 & SF=OF)
SMPUsesFlags[NN_setge] = true;               // Set Byte if Greater or Equal (SF=OF)
SMPUsesFlags[NN_setl] = true;                // Set Byte if Less (SF!=OF)
SMPUsesFlags[NN_setle] = true;               // Set Byte if Less or Equal (ZF=1 | SF!=OF)
SMPUsesFlags[NN_setna] = true;               // Set Byte if Not Above (CF=1 | ZF=1)
SMPUsesFlags[NN_setnae] = true;              // Set Byte if Not Above or Equal (CF=1)
SMPUsesFlags[NN_setnb] = true;               // Set Byte if Not Below (CF=0)
SMPUsesFlags[NN_setnbe] = true;              // Set Byte if Not Below or Equal (CF=0 & ZF=0)
SMPUsesFlags[NN_setnc] = true;               // Set Byte if Not Carry (CF=0)
SMPUsesFlags[NN_setne] = true;               // Set Byte if Not Equal (ZF=0)
SMPUsesFlags[NN_setng] = true;               // Set Byte if Not Greater (ZF=1 | SF!=OF)
SMPUsesFlags[NN_setnge] = true;              // Set Byte if Not Greater or Equal (ZF=1)
SMPUsesFlags[NN_setnl] = true;               // Set Byte if Not Less (SF=OF)
SMPUsesFlags[NN_setnle] = true;              // Set Byte if Not Less or Equal (ZF=0 & SF=OF)
SMPUsesFlags[NN_setno] = true;               // Set Byte if Not Overflow (OF=0)
SMPUsesFlags[NN_setnp] = true;               // Set Byte if Not Parity (PF=0)
SMPUsesFlags[NN_setns] = true;               // Set Byte if Not Sign (SF=0)
SMPUsesFlags[NN_setnz] = true;               // Set Byte if Not Zero (ZF=0)
SMPUsesFlags[NN_seto] = true;                // Set Byte if Overflow (OF=1)
SMPUsesFlags[NN_setp] = true;                // Set Byte if Parity (PF=1)
SMPUsesFlags[NN_setpe] = true;               // Set Byte if Parity Even (PF=1)
SMPUsesFlags[NN_setpo] = true;               // Set Byte if Parity Odd  (PF=0)
SMPUsesFlags[NN_sets] = true;                // Set Byte if Sign (SF=1)
SMPUsesFlags[NN_setz] = true;                // Set Byte if Zero (ZF=1)
SMPUsesFlags[NN_stos] = true;                // Store String

//
//      486 instructions
//

//
//      Pentium instructions
//

#if 0
SMPUsesFlags[NN_cpuid] = true;               // Get CPU ID
SMPUsesFlags[NN_cmpxchg8b] = true;           // Compare and Exchange Eight Bytes
#endif

//
//      Pentium Pro instructions
//

SMPUsesFlags[NN_cmova] = true;               // Move if Above (CF=0 & ZF=0)
SMPUsesFlags[NN_cmovb] = true;               // Move if Below (CF=1)
SMPUsesFlags[NN_cmovbe] = true;              // Move if Below or Equal (CF=1 | ZF=1)
SMPUsesFlags[NN_cmovg] = true;               // Move if Greater (ZF=0 & SF=OF)
SMPUsesFlags[NN_cmovge] = true;              // Move if Greater or Equal (SF=OF)
SMPUsesFlags[NN_cmovl] = true;               // Move if Less (SF!=OF)
SMPUsesFlags[NN_cmovle] = true;              // Move if Less or Equal (ZF=1 | SF!=OF)
SMPUsesFlags[NN_cmovnb] = true;              // Move if Not Below (CF=0)
SMPUsesFlags[NN_cmovno] = true;              // Move if Not Overflow (OF=0)
SMPUsesFlags[NN_cmovnp] = true;              // Move if Not Parity (PF=0)
SMPUsesFlags[NN_cmovns] = true;              // Move if Not Sign (SF=0)
SMPUsesFlags[NN_cmovnz] = true;              // Move if Not Zero (ZF=0)
SMPUsesFlags[NN_cmovo] = true;               // Move if Overflow (OF=1)
SMPUsesFlags[NN_cmovp] = true;               // Move if Parity (PF=1)
SMPUsesFlags[NN_cmovs] = true;               // Move if Sign (SF=1)
SMPUsesFlags[NN_cmovz] = true;               // Move if Zero (ZF=1)
SMPUsesFlags[NN_fcmovb] = true;              // Floating Move if Below          
SMPUsesFlags[NN_fcmove] = true;              // Floating Move if Equal          
SMPUsesFlags[NN_fcmovbe] = true;             // Floating Move if Below or Equal 
SMPUsesFlags[NN_fcmovu] = true;              // Floating Move if Unordered      
SMPUsesFlags[NN_fcmovnb] = true;             // Floating Move if Not Below      
SMPUsesFlags[NN_fcmovne] = true;             // Floating Move if Not Equal      
SMPUsesFlags[NN_fcmovnbe] = true;            // Floating Move if Not Below or Equal
SMPUsesFlags[NN_fcmovnu] = true;             // Floating Move if Not Unordered     

//
//      FPP instructions
//


//
//      80387 instructions
//


//
//      Instructions added 28.02.96
//

SMPUsesFlags[NN_setalc] = true;              // Set AL to Carry Flag      

//
//      MMX instructions
//


//
//      Undocumented Deschutes processor instructions
//


//      Pentium II instructions


//      3DNow! instructions


//      Pentium III instructions


// Pentium III Pseudo instructions


// AMD K7 instructions

// Revisit AMD if we port to it.

// Undocumented FP instructions (thanks to norbert.juffa@adm.com)

// Pentium 4 instructions



// AMD syscall/sysret instructions  NOTE: not AMD, found in Intel manual

// AMD64 instructions    NOTE: not AMD, found in Intel manual


// New Pentium instructions (SSE3)


// Missing AMD64 instructions  NOTE: also found in Intel manual


// SSE3 instructions


// SSSE3 instructions


// VMX instructions

// Added with x86-64

// Geode LX 3DNow! extensions

// SSE2 pseudoinstructions

// SSSE4.1 instructions

// SSSE4.2 instructions

// AMD SSE4a instructions

// xsave/xrstor instructions

// Intel Safer Mode Extensions (SMX)

// AMD-V Virtualization ISA Extension

// VMX+ instructions

// Intel Atom instructions

// Intel AES instructions

// Carryless multiplication

// Returns modified by operand size prefixes

// RDRAND support

// new GPR instructions

SMPUsesFlags[NN_adcx] = true;                 // Unsigned Integer Addition of Two Operands with Carry Flag
SMPUsesFlags[NN_adox] = true;                 // Unsigned Integer Addition of Two Operands with Overflow Flag

// new AVX instructions

// Transactional Synchronization Extensions

// Virtual PC synthetic instructions

SMPUsesFlags[NN_last] = false;

  return;

} // end InitSMPUsesFlags()


// Initialize the SMPTypeCategory[] array to define how we infer
//   numeric or pointer operand types for optimizing annotations.
void InitTypeCategory(void) {
	// Default category is 0, no type inference without knowing context.
	(void) memset(SMPTypeCategory, 0, sizeof(SMPTypeCategory));
	// Category 1 instructions will need no mmStrata instrumentation
	//  and are irrelevant to our type system, so we do not attempt
	//  to make type inferences. Many of these operate on numeric
	//  operands such as floating point or MMX/SSE registers. mmStrata
	//  assumes that such registers are always numeric, so we do not
	//  need annotations informing mmStrata that FP/MMX/SSE regs are numeric.
	// Category 2 instructions always have a result type of 'n' (number).
	// Category 3 instructions have a result type of 'n' (number)
	//  whenever the second source operand is an operand of type 'n'.