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SMPDataFlowAnalysis.cpp 276 KiB
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Initial code to build RTLs and infer operand types.  
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SMPTypeCategory[NN_setnc] = 2;               // Set Byte if Not Carry (CF=0)
SMPTypeCategory[NN_setne] = 2;               // Set Byte if Not Equal (ZF=0)
SMPTypeCategory[NN_setng] = 2;               // Set Byte if Not Greater (ZF=1 | SF!=OF)
SMPTypeCategory[NN_setnge] = 2;              // Set Byte if Not Greater or Equal (ZF=1)
SMPTypeCategory[NN_setnl] = 2;               // Set Byte if Not Less (SF=OF)
SMPTypeCategory[NN_setnle] = 2;              // Set Byte if Not Less or Equal (ZF=0 & SF=OF)
SMPTypeCategory[NN_setno] = 2;               // Set Byte if Not Overflow (OF=0)
SMPTypeCategory[NN_setnp] = 2;               // Set Byte if Not Parity (PF=0)
SMPTypeCategory[NN_setns] = 2;               // Set Byte if Not Sign (SF=0)
SMPTypeCategory[NN_setnz] = 2;               // Set Byte if Not Zero (ZF=0)
SMPTypeCategory[NN_seto] = 2;                // Set Byte if Overflow (OF=1)
SMPTypeCategory[NN_setp] = 2;                // Set Byte if Parity (PF=1)
SMPTypeCategory[NN_setpe] = 2;               // Set Byte if Parity Even (PF=1)
SMPTypeCategory[NN_setpo] = 2;               // Set Byte if Parity Odd  (PF=0)
SMPTypeCategory[NN_sets] = 2;                // Set Byte if Sign (SF=1)
SMPTypeCategory[NN_setz] = 2;                // Set Byte if Zero (ZF=1)
SMPTypeCategory[NN_sgdt] = 0;                // Store Global Descriptor Table Register
SMPTypeCategory[NN_sidt] = 0;                // Store Interrupt Descriptor Table Register
SMPTypeCategory[NN_shld] = 2;                // Double Precision Shift Left
SMPTypeCategory[NN_shrd] = 2;                // Double Precision Shift Right
SMPTypeCategory[NN_sldt] = 6;                // Store Local Descriptor Table Register
SMPTypeCategory[NN_smsw] = 2;                // Store Machine Status Word
SMPTypeCategory[NN_stc] = 1;                 // Set Carry Flag
SMPTypeCategory[NN_std] = 1;                 // Set Direction Flag
SMPTypeCategory[NN_sti] = 1;                 // Set Interrupt Flag
SMPTypeCategory[NN_stos] = 0;                // Store String
SMPTypeCategory[NN_str] = 6;                 // Store Task Register
SMPTypeCategory[NN_sub] = 5;                 // Integer Subtraction
SMPTypeCategory[NN_test] = 1;                // Logical Compare
SMPTypeCategory[NN_verr] = 1;                // Verify a Segment for Reading
SMPTypeCategory[NN_verw] = 1;                // Verify a Segment for Writing
SMPTypeCategory[NN_wait] = 1;                // Wait until BUSY# Pin is Inactive (HIGH)
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Fix tables of which instructions DEF and USE the x86 flags.  
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SMPTypeCategory[NN_xchg] = 12;               // Exchange Register/Memory with Register
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Initial code to build RTLs and infer operand types.  
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SMPTypeCategory[NN_xlat] = 0;                // Table Lookup Translation
SMPTypeCategory[NN_xor] = 2;                 // Logical Exclusive OR

//
//      486 instructions
//

SMPTypeCategory[NN_cmpxchg] = 12;             // Compare and Exchange
SMPTypeCategory[NN_bswap] = 1;               // Swap bytes in register
SMPTypeCategory[NN_xadd] = 12;                // t<-dest; dest<-src+dest; src<-t
SMPTypeCategory[NN_invd] = 1;                // Invalidate Data Cache
SMPTypeCategory[NN_wbinvd] = 1;              // Invalidate Data Cache (write changes)
SMPTypeCategory[NN_invlpg] = 1;              // Invalidate TLB entry

//
//      Pentium instructions
//

SMPTypeCategory[NN_rdmsr] = 8;               // Read Machine Status Register
SMPTypeCategory[NN_wrmsr] = 1;               // Write Machine Status Register
SMPTypeCategory[NN_cpuid] = 8;               // Get CPU ID
SMPTypeCategory[NN_cmpxchg8b] = 12;           // Compare and Exchange Eight Bytes
SMPTypeCategory[NN_rdtsc] = 8;               // Read Time Stamp Counter
SMPTypeCategory[NN_rsm] = 1;                 // Resume from System Management Mode

//
//      Pentium Pro instructions
//
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Move conditional moves from type category 12 to 0; most of category 15 to 14...  
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SMPTypeCategory[NN_cmova] = 0;               // Move if Above (CF=0 & ZF=0)
SMPTypeCategory[NN_cmovb] = 0;               // Move if Below (CF=1)
SMPTypeCategory[NN_cmovbe] = 0;              // Move if Below or Equal (CF=1 | ZF=1)
SMPTypeCategory[NN_cmovg] = 0;               // Move if Greater (ZF=0 & SF=OF)
SMPTypeCategory[NN_cmovge] = 0;              // Move if Greater or Equal (SF=OF)
SMPTypeCategory[NN_cmovl] = 0;               // Move if Less (SF!=OF)
SMPTypeCategory[NN_cmovle] = 0;              // Move if Less or Equal (ZF=1 | SF!=OF)
SMPTypeCategory[NN_cmovnb] = 0;              // Move if Not Below (CF=0)
SMPTypeCategory[NN_cmovno] = 0;              // Move if Not Overflow (OF=0)
SMPTypeCategory[NN_cmovnp] = 0;              // Move if Not Parity (PF=0)
SMPTypeCategory[NN_cmovns] = 0;              // Move if Not Sign (SF=0)
SMPTypeCategory[NN_cmovnz] = 0;              // Move if Not Zero (ZF=0)
SMPTypeCategory[NN_cmovo] = 0;               // Move if Overflow (OF=1)
SMPTypeCategory[NN_cmovp] = 0;               // Move if Parity (PF=1)
SMPTypeCategory[NN_cmovs] = 0;               // Move if Sign (SF=1)
SMPTypeCategory[NN_cmovz] = 0;               // Move if Zero (ZF=1)
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Initial code to build RTLs and infer operand types.  
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SMPTypeCategory[NN_fcmovb] = 1;              // Floating Move if Below          
SMPTypeCategory[NN_fcmove] = 1;              // Floating Move if Equal          
SMPTypeCategory[NN_fcmovbe] = 1;             // Floating Move if Below or Equal 
SMPTypeCategory[NN_fcmovu] = 1;              // Floating Move if Unordered      
SMPTypeCategory[NN_fcmovnb] = 1;             // Floating Move if Not Below      
SMPTypeCategory[NN_fcmovne] = 1;             // Floating Move if Not Equal      
SMPTypeCategory[NN_fcmovnbe] = 1;            // Floating Move if Not Below or Equal
SMPTypeCategory[NN_fcmovnu] = 1;             // Floating Move if Not Unordered     
SMPTypeCategory[NN_fcomi] = 1;               // FP Compare, result in EFLAGS
SMPTypeCategory[NN_fucomi] = 1;              // FP Unordered Compare, result in EFLAGS
SMPTypeCategory[NN_fcomip] = 1;              // FP Compare, result in EFLAGS, pop stack
SMPTypeCategory[NN_fucomip] = 1;             // FP Unordered Compare, result in EFLAGS, pop stack
SMPTypeCategory[NN_rdpmc] = 8;               // Read Performance Monitor Counter

//
//      FPP instructions
//

SMPTypeCategory[NN_fld] = 14;                 // Load Real             ** Infer src is 'n'
SMPTypeCategory[NN_fst] = 9;                 // Store Real            
SMPTypeCategory[NN_fstp] = 9;                // Store Real and Pop   
SMPTypeCategory[NN_fxch] = 1;                // Exchange Registers
SMPTypeCategory[NN_fild] = 14;                // Load Integer          ** Infer src is 'n'
SMPTypeCategory[NN_fist] = 13;                // Store Integer
SMPTypeCategory[NN_fistp] = 13;               // Store Integer and Pop
SMPTypeCategory[NN_fbld] = 1;                // Load BCD
SMPTypeCategory[NN_fbstp] = 13;               // Store BCD and Pop
SMPTypeCategory[NN_fadd] = 14;                // Add Real
SMPTypeCategory[NN_faddp] = 14;               // Add Real and Pop
SMPTypeCategory[NN_fiadd] = 14;               // Add Integer
SMPTypeCategory[NN_fsub] = 14;                // Subtract Real
SMPTypeCategory[NN_fsubp] = 14;               // Subtract Real and Pop
SMPTypeCategory[NN_fisub] = 14;               // Subtract Integer
SMPTypeCategory[NN_fsubr] = 14;               // Subtract Real Reversed
SMPTypeCategory[NN_fsubrp] = 14;              // Subtract Real Reversed and Pop
SMPTypeCategory[NN_fisubr] = 14;              // Subtract Integer Reversed
SMPTypeCategory[NN_fmul] = 14;                // Multiply Real
SMPTypeCategory[NN_fmulp] = 14;               // Multiply Real and Pop
SMPTypeCategory[NN_fimul] = 14;               // Multiply Integer
SMPTypeCategory[NN_fdiv] = 14;                // Divide Real
SMPTypeCategory[NN_fdivp] = 14;               // Divide Real and Pop
SMPTypeCategory[NN_fidiv] = 14;               // Divide Integer
SMPTypeCategory[NN_fdivr] = 14;               // Divide Real Reversed
SMPTypeCategory[NN_fdivrp] = 14;              // Divide Real Reversed and Pop
SMPTypeCategory[NN_fidivr] = 14;              // Divide Integer Reversed
SMPTypeCategory[NN_fsqrt] = 1;               // Square Root
SMPTypeCategory[NN_fscale] = 1;              // Scale:  st(0) <- st(0) * 2^st(1)
SMPTypeCategory[NN_fprem] = 1;               // Partial Remainder
SMPTypeCategory[NN_frndint] = 1;             // Round to Integer
SMPTypeCategory[NN_fxtract] = 1;             // Extract exponent and significand
SMPTypeCategory[NN_fabs] = 1;                // Absolute value
SMPTypeCategory[NN_fchs] = 1;                // Change Sign
SMPTypeCategory[NN_fcom] = 1;                // Compare Real
SMPTypeCategory[NN_fcomp] = 1;               // Compare Real and Pop
SMPTypeCategory[NN_fcompp] = 1;              // Compare Real and Pop Twice
SMPTypeCategory[NN_ficom] = 1;               // Compare Integer
SMPTypeCategory[NN_ficomp] = 1;              // Compare Integer and Pop
SMPTypeCategory[NN_ftst] = 1;                // Test
SMPTypeCategory[NN_fxam] = 1;                // Examine
SMPTypeCategory[NN_fptan] = 1;               // Partial tangent
SMPTypeCategory[NN_fpatan] = 1;              // Partial arctangent
SMPTypeCategory[NN_f2xm1] = 1;               // 2^x - 1
SMPTypeCategory[NN_fyl2x] = 1;               // Y * lg2(X)
SMPTypeCategory[NN_fyl2xp1] = 1;             // Y * lg2(X+1)
SMPTypeCategory[NN_fldz] = 1;                // Load +0.0
SMPTypeCategory[NN_fld1] = 1;                // Load +1.0
SMPTypeCategory[NN_fldpi] = 1;               // Load PI=3.14...
SMPTypeCategory[NN_fldl2t] = 1;              // Load lg2(10)
SMPTypeCategory[NN_fldl2e] = 1;              // Load lg2(e)
SMPTypeCategory[NN_fldlg2] = 1;              // Load lg10(2)
SMPTypeCategory[NN_fldln2] = 1;              // Load ln(2)
SMPTypeCategory[NN_finit] = 1;               // Initialize Processor
SMPTypeCategory[NN_fninit] = 1;              // Initialize Processor (no wait)
SMPTypeCategory[NN_fsetpm] = 1;              // Set Protected Mode
SMPTypeCategory[NN_fldcw] = 14;               // Load Control Word
SMPTypeCategory[NN_fstcw] = 13;               // Store Control Word
SMPTypeCategory[NN_fnstcw] = 13;              // Store Control Word (no wait)
SMPTypeCategory[NN_fstsw] = 2;               // Store Status Word to memory or AX
SMPTypeCategory[NN_fnstsw] = 2;              // Store Status Word (no wait) to memory or AX
SMPTypeCategory[NN_fclex] = 1;               // Clear Exceptions
SMPTypeCategory[NN_fnclex] = 1;              // Clear Exceptions (no wait)
SMPTypeCategory[NN_fstenv] = 13;              // Store Environment
SMPTypeCategory[NN_fnstenv] = 13;             // Store Environment (no wait)
SMPTypeCategory[NN_fldenv] = 14;              // Load Environment
SMPTypeCategory[NN_fsave] = 13;               // Save State
SMPTypeCategory[NN_fnsave] = 13;              // Save State (no wait)
SMPTypeCategory[NN_frstor] = 14;              // Restore State    **  infer src is 'n'
SMPTypeCategory[NN_fincstp] = 1;             // Increment Stack Pointer
SMPTypeCategory[NN_fdecstp] = 1;             // Decrement Stack Pointer
SMPTypeCategory[NN_ffree] = 1;               // Free Register
SMPTypeCategory[NN_fnop] = 1;                // No Operation
SMPTypeCategory[NN_feni] = 1;                // (8087 only)
SMPTypeCategory[NN_fneni] = 1;               // (no wait) (8087 only)
SMPTypeCategory[NN_fdisi] = 1;               // (8087 only)
SMPTypeCategory[NN_fndisi] = 1;              // (no wait) (8087 only)

//
//      80387 instructions
//

SMPTypeCategory[NN_fprem1] = 1;              // Partial Remainder ( < half )
SMPTypeCategory[NN_fsincos] = 1;             // t<-cos(st); st<-sin(st); push t
SMPTypeCategory[NN_fsin] = 1;                // Sine
SMPTypeCategory[NN_fcos] = 1;                // Cosine
SMPTypeCategory[NN_fucom] = 1;               // Compare Unordered Real
SMPTypeCategory[NN_fucomp] = 1;              // Compare Unordered Real and Pop
SMPTypeCategory[NN_fucompp] = 1;             // Compare Unordered Real and Pop Twice

//
//      Instructions added 28.02.96
//

SMPTypeCategory[NN_setalc] = 2;              // Set AL to Carry Flag     **
SMPTypeCategory[NN_svdc] = 0;                // Save Register and Descriptor
SMPTypeCategory[NN_rsdc] = 0;                // Restore Register and Descriptor
SMPTypeCategory[NN_svldt] = 0;               // Save LDTR and Descriptor
SMPTypeCategory[NN_rsldt] = 0;               // Restore LDTR and Descriptor
SMPTypeCategory[NN_svts] = 1;                // Save TR and Descriptor
SMPTypeCategory[NN_rsts] = 1;                // Restore TR and Descriptor
SMPTypeCategory[NN_icebp] = 1;               // ICE Break Point
SMPTypeCategory[NN_loadall] = 0;             // Load the entire CPU state from ES:EDI ???

//
//      MMX instructions
//

SMPTypeCategory[NN_emms] = 1;                // Empty MMX state
SMPTypeCategory[NN_movd] = 15;                // Move 32 bits
SMPTypeCategory[NN_movq] = 15;                // Move 64 bits
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Move conditional moves from type category 12 to 0; most of category 15 to 14...  
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SMPTypeCategory[NN_packsswb] = 14;            // Pack with Signed Saturation (Word->Byte)
SMPTypeCategory[NN_packssdw] = 14;            // Pack with Signed Saturation (Dword->Word)
SMPTypeCategory[NN_packuswb] = 14;            // Pack with Unsigned Saturation (Word->Byte)
SMPTypeCategory[NN_paddb] = 14;               // Packed Add Byte
SMPTypeCategory[NN_paddw] = 14;               // Packed Add Word
SMPTypeCategory[NN_paddd] = 14;               // Packed Add Dword
SMPTypeCategory[NN_paddsb] = 14;              // Packed Add with Saturation (Byte)
SMPTypeCategory[NN_paddsw] = 14;              // Packed Add with Saturation (Word)
SMPTypeCategory[NN_paddusb] = 14;             // Packed Add Unsigned with Saturation (Byte)
SMPTypeCategory[NN_paddusw] = 14;             // Packed Add Unsigned with Saturation (Word)
SMPTypeCategory[NN_pand] = 14;                // Bitwise Logical And
SMPTypeCategory[NN_pandn] = 14;               // Bitwise Logical And Not
SMPTypeCategory[NN_pcmpeqb] = 14;             // Packed Compare for Equal (Byte)
SMPTypeCategory[NN_pcmpeqw] = 14;             // Packed Compare for Equal (Word)
SMPTypeCategory[NN_pcmpeqd] = 14;             // Packed Compare for Equal (Dword)
SMPTypeCategory[NN_pcmpgtb] = 14;             // Packed Compare for Greater Than (Byte)
SMPTypeCategory[NN_pcmpgtw] = 14;             // Packed Compare for Greater Than (Word)
SMPTypeCategory[NN_pcmpgtd] = 14;             // Packed Compare for Greater Than (Dword)
SMPTypeCategory[NN_pmaddwd] = 14;             // Packed Multiply and Add
SMPTypeCategory[NN_pmulhw] = 14;              // Packed Multiply High
SMPTypeCategory[NN_pmullw] = 14;              // Packed Multiply Low
SMPTypeCategory[NN_por] = 14;                 // Bitwise Logical Or
SMPTypeCategory[NN_psllw] = 14;               // Packed Shift Left Logical (Word)
SMPTypeCategory[NN_pslld] = 14;               // Packed Shift Left Logical (Dword)
SMPTypeCategory[NN_psllq] = 14;               // Packed Shift Left Logical (Qword)
SMPTypeCategory[NN_psraw] = 14;               // Packed Shift Right Arithmetic (Word)
SMPTypeCategory[NN_psrad] = 14;               // Packed Shift Right Arithmetic (Dword)
SMPTypeCategory[NN_psrlw] = 14;               // Packed Shift Right Logical (Word)
SMPTypeCategory[NN_psrld] = 14;               // Packed Shift Right Logical (Dword)
SMPTypeCategory[NN_psrlq] = 14;               // Packed Shift Right Logical (Qword)
SMPTypeCategory[NN_psubb] = 14;               // Packed Subtract Byte
SMPTypeCategory[NN_psubw] = 14;               // Packed Subtract Word
SMPTypeCategory[NN_psubd] = 14;               // Packed Subtract Dword
SMPTypeCategory[NN_psubsb] = 14;              // Packed Subtract with Saturation (Byte)
SMPTypeCategory[NN_psubsw] = 14;              // Packed Subtract with Saturation (Word)
SMPTypeCategory[NN_psubusb] = 14;             // Packed Subtract Unsigned with Saturation (Byte)
SMPTypeCategory[NN_psubusw] = 14;             // Packed Subtract Unsigned with Saturation (Word)
SMPTypeCategory[NN_punpckhbw] = 14;           // Unpack High Packed Data (Byte->Word)
SMPTypeCategory[NN_punpckhwd] = 14;           // Unpack High Packed Data (Word->Dword)
SMPTypeCategory[NN_punpckhdq] = 14;           // Unpack High Packed Data (Dword->Qword)
SMPTypeCategory[NN_punpcklbw] = 14;           // Unpack Low Packed Data (Byte->Word)
SMPTypeCategory[NN_punpcklwd] = 14;           // Unpack Low Packed Data (Word->Dword)
SMPTypeCategory[NN_punpckldq] = 14;           // Unpack Low Packed Data (Dword->Qword)
SMPTypeCategory[NN_pxor] = 14;                // Bitwise Logical Exclusive Or
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Initial code to build RTLs and infer operand types.  
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//
//      Undocumented Deschutes processor instructions
//

SMPTypeCategory[NN_fxsave] = 1;              // Fast save FP context            ** to where?
SMPTypeCategory[NN_fxrstor] = 1;             // Fast restore FP context         ** from where?

//      Pentium II instructions

SMPTypeCategory[NN_sysenter] = 1;            // Fast Transition to System Call Entry Point
SMPTypeCategory[NN_sysexit] = 1;             // Fast Transition from System Call Entry Point

//      3DNow! instructions
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Move conditional moves from type category 12 to 0; most of category 15 to 14...  
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SMPTypeCategory[NN_pavgusb] = 14;             // Packed 8-bit Unsigned Integer Averaging
SMPTypeCategory[NN_pfadd] = 14;               // Packed Floating-Point Addition
SMPTypeCategory[NN_pfsub] = 14;               // Packed Floating-Point Subtraction
SMPTypeCategory[NN_pfsubr] = 14;              // Packed Floating-Point Reverse Subtraction
SMPTypeCategory[NN_pfacc] = 14;               // Packed Floating-Point Accumulate
SMPTypeCategory[NN_pfcmpge] = 14;             // Packed Floating-Point Comparison, Greater or Equal
SMPTypeCategory[NN_pfcmpgt] = 14;             // Packed Floating-Point Comparison, Greater
SMPTypeCategory[NN_pfcmpeq] = 14;             // Packed Floating-Point Comparison, Equal
SMPTypeCategory[NN_pfmin] = 14;               // Packed Floating-Point Minimum
SMPTypeCategory[NN_pfmax] = 14;               // Packed Floating-Point Maximum
SMPTypeCategory[NN_pi2fd] = 14;               // Packed 32-bit Integer to Floating-Point
SMPTypeCategory[NN_pf2id] = 14;               // Packed Floating-Point to 32-bit Integer
SMPTypeCategory[NN_pfrcp] = 14;               // Packed Floating-Point Reciprocal Approximation
SMPTypeCategory[NN_pfrsqrt] = 14;             // Packed Floating-Point Reciprocal Square Root Approximation
SMPTypeCategory[NN_pfmul] = 14;               // Packed Floating-Point Multiplication
SMPTypeCategory[NN_pfrcpit1] = 14;            // Packed Floating-Point Reciprocal First Iteration Step
SMPTypeCategory[NN_pfrsqit1] = 14;            // Packed Floating-Point Reciprocal Square Root First Iteration Step
SMPTypeCategory[NN_pfrcpit2] = 14;            // Packed Floating-Point Reciprocal Second Iteration Step
SMPTypeCategory[NN_pmulhrw] = 14;             // Packed Floating-Point 16-bit Integer Multiply with rounding
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SMPTypeCategory[NN_femms] = 1;               // Faster entry/exit of the MMX or floating-point state
SMPTypeCategory[NN_prefetch] = 1;            // Prefetch at least a 32-byte line into L1 data cache
SMPTypeCategory[NN_prefetchw] = 1;           // Prefetch processor cache line into L1 data cache (mark as modified)


//      Pentium III instructions
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Move conditional moves from type category 12 to 0; most of category 15 to 14...  
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SMPTypeCategory[NN_addps] = 14;               // Packed Single-FP Add
SMPTypeCategory[NN_addss] = 14;               // Scalar Single-FP Add
SMPTypeCategory[NN_andnps] = 14;              // Bitwise Logical And Not for Single-FP
SMPTypeCategory[NN_andps] = 14;               // Bitwise Logical And for Single-FP
SMPTypeCategory[NN_cmpps] = 14;               // Packed Single-FP Compare
SMPTypeCategory[NN_cmpss] = 14;               // Scalar Single-FP Compare
SMPTypeCategory[NN_comiss] = 14;              // Scalar Ordered Single-FP Compare and Set EFLAGS
SMPTypeCategory[NN_cvtpi2ps] = 14;            // Packed signed INT32 to Packed Single-FP conversion
SMPTypeCategory[NN_cvtps2pi] = 14;            // Packed Single-FP to Packed INT32 conversion
SMPTypeCategory[NN_cvtsi2ss] = 14;            // Scalar signed INT32 to Single-FP conversion
SMPTypeCategory[NN_cvtss2si] = 14;            // Scalar Single-FP to signed INT32 conversion
SMPTypeCategory[NN_cvttps2pi] = 14;           // Packed Single-FP to Packed INT32 conversion (truncate)
SMPTypeCategory[NN_cvttss2si] = 14;           // Scalar Single-FP to signed INT32 conversion (truncate)
SMPTypeCategory[NN_divps] = 14;               // Packed Single-FP Divide
SMPTypeCategory[NN_divss] = 14;               // Scalar Single-FP Divide
SMPTypeCategory[NN_ldmxcsr] = 14;             // Load Streaming SIMD Extensions Technology Control/Status Register
SMPTypeCategory[NN_maxps] = 14;               // Packed Single-FP Maximum
SMPTypeCategory[NN_maxss] = 14;               // Scalar Single-FP Maximum
SMPTypeCategory[NN_minps] = 14;               // Packed Single-FP Minimum
SMPTypeCategory[NN_minss] = 14;               // Scalar Single-FP Minimum
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SMPTypeCategory[NN_movaps] = 15;              // Move Aligned Four Packed Single-FP  ** infer memsrc 'n'?
SMPTypeCategory[NN_movhlps] = 15;             // Move High to Low Packed Single-FP
SMPTypeCategory[NN_movhps] = 15;              // Move High Packed Single-FP
SMPTypeCategory[NN_movlhps] = 15;             // Move Low to High Packed Single-FP
SMPTypeCategory[NN_movlps] = 15;              // Move Low Packed Single-FP
SMPTypeCategory[NN_movmskps] = 15;            // Move Mask to Register
SMPTypeCategory[NN_movss] = 15;               // Move Scalar Single-FP
SMPTypeCategory[NN_movups] = 15;              // Move Unaligned Four Packed Single-FP
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Move conditional moves from type category 12 to 0; most of category 15 to 14...  
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SMPTypeCategory[NN_mulps] = 14;               // Packed Single-FP Multiply
SMPTypeCategory[NN_mulss] = 14;               // Scalar Single-FP Multiply
SMPTypeCategory[NN_orps] = 14;                // Bitwise Logical OR for Single-FP Data
SMPTypeCategory[NN_rcpps] = 14;               // Packed Single-FP Reciprocal
SMPTypeCategory[NN_rcpss] = 14;               // Scalar Single-FP Reciprocal
SMPTypeCategory[NN_rsqrtps] = 14;             // Packed Single-FP Square Root Reciprocal
SMPTypeCategory[NN_rsqrtss] = 14;             // Scalar Single-FP Square Root Reciprocal
SMPTypeCategory[NN_shufps] = 14;              // Shuffle Single-FP
SMPTypeCategory[NN_sqrtps] = 14;              // Packed Single-FP Square Root
SMPTypeCategory[NN_sqrtss] = 14;              // Scalar Single-FP Square Root
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SMPTypeCategory[NN_stmxcsr] = 15;             // Store Streaming SIMD Extensions Technology Control/Status Register    ** Infer dest is 'n'
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SMPTypeCategory[NN_subps] = 14;               // Packed Single-FP Subtract
SMPTypeCategory[NN_subss] = 14;               // Scalar Single-FP Subtract
SMPTypeCategory[NN_ucomiss] = 14;             // Scalar Unordered Single-FP Compare and Set EFLAGS
SMPTypeCategory[NN_unpckhps] = 14;            // Unpack High Packed Single-FP Data
SMPTypeCategory[NN_unpcklps] = 14;            // Unpack Low Packed Single-FP Data
SMPTypeCategory[NN_xorps] = 14;               // Bitwise Logical XOR for Single-FP Data
SMPTypeCategory[NN_pavgb] = 14;               // Packed Average (Byte)
SMPTypeCategory[NN_pavgw] = 14;               // Packed Average (Word)
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SMPTypeCategory[NN_pextrw] = 15;               // Extract Word
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SMPTypeCategory[NN_pinsrw] = 14;              // Insert Word
SMPTypeCategory[NN_pmaxsw] = 14;              // Packed Signed Integer Word Maximum
SMPTypeCategory[NN_pmaxub] = 14;              // Packed Unsigned Integer Byte Maximum
SMPTypeCategory[NN_pminsw] = 14;              // Packed Signed Integer Word Minimum
SMPTypeCategory[NN_pminub] = 14;              // Packed Unsigned Integer Byte Minimum
SMPTypeCategory[NN_pmovmskb] = 2;             // Move Byte Mask to Integer
SMPTypeCategory[NN_pmulhuw] = 14;             // Packed Multiply High Unsigned
SMPTypeCategory[NN_psadbw] = 14;              // Packed Sum of Absolute Differences
SMPTypeCategory[NN_pshufw] = 14;              // Packed Shuffle Word
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SMPTypeCategory[NN_maskmovq] = 15;            // Byte Mask write   ** Infer dest is 'n'
SMPTypeCategory[NN_movntps] = 13;             // Move Aligned Four Packed Single-FP Non Temporal  * infer dest is 'n'
SMPTypeCategory[NN_movntq] = 13;              // Move 64 Bits Non Temporal    ** Infer dest is 'n'
SMPTypeCategory[NN_prefetcht0] = 1;          // Prefetch to all cache levels
SMPTypeCategory[NN_prefetcht1] = 1;          // Prefetch to all cache levels
SMPTypeCategory[NN_prefetcht2] = 1;          // Prefetch to L2 cache
SMPTypeCategory[NN_prefetchnta] = 1;         // Prefetch to L1 cache
SMPTypeCategory[NN_sfence] = 1;              // Store Fence

// Pentium III Pseudo instructions
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SMPTypeCategory[NN_cmpeqps] = 14;             // Packed Single-FP Compare EQ
SMPTypeCategory[NN_cmpltps] = 14;             // Packed Single-FP Compare LT
SMPTypeCategory[NN_cmpleps] = 14;             // Packed Single-FP Compare LE
SMPTypeCategory[NN_cmpunordps] = 14;          // Packed Single-FP Compare UNORD
SMPTypeCategory[NN_cmpneqps] = 14;            // Packed Single-FP Compare NOT EQ
SMPTypeCategory[NN_cmpnltps] = 14;            // Packed Single-FP Compare NOT LT
SMPTypeCategory[NN_cmpnleps] = 14;            // Packed Single-FP Compare NOT LE
SMPTypeCategory[NN_cmpordps] = 14;            // Packed Single-FP Compare ORDERED
SMPTypeCategory[NN_cmpeqss] = 14;             // Scalar Single-FP Compare EQ
SMPTypeCategory[NN_cmpltss] = 14;             // Scalar Single-FP Compare LT
SMPTypeCategory[NN_cmpless] = 14;             // Scalar Single-FP Compare LE
SMPTypeCategory[NN_cmpunordss] = 14;          // Scalar Single-FP Compare UNORD
SMPTypeCategory[NN_cmpneqss] = 14;            // Scalar Single-FP Compare NOT EQ
SMPTypeCategory[NN_cmpnltss] = 14;            // Scalar Single-FP Compare NOT LT
SMPTypeCategory[NN_cmpnless] = 14;            // Scalar Single-FP Compare NOT LE
SMPTypeCategory[NN_cmpordss] = 14;            // Scalar Single-FP Compare ORDERED
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// AMD K7 instructions

// Revisit AMD if we port to it.
SMPTypeCategory[NN_pf2iw] = 15;               // Packed Floating-Point to Integer with Sign Extend
SMPTypeCategory[NN_pfnacc] = 15;              // Packed Floating-Point Negative Accumulate
SMPTypeCategory[NN_pfpnacc] = 15;             // Packed Floating-Point Mixed Positive-Negative Accumulate
SMPTypeCategory[NN_pi2fw] = 15;               // Packed 16-bit Integer to Floating-Point
SMPTypeCategory[NN_pswapd] = 15;              // Packed Swap Double Word

// Undocumented FP instructions (thanks to norbert.juffa@adm.com)

SMPTypeCategory[NN_fstp1] = 9;               // Alias of Store Real and Pop
SMPTypeCategory[NN_fcom2] = 1;               // Alias of Compare Real
SMPTypeCategory[NN_fcomp3] = 1;              // Alias of Compare Real and Pop
SMPTypeCategory[NN_fxch4] = 1;               // Alias of Exchange Registers
SMPTypeCategory[NN_fcomp5] = 1;              // Alias of Compare Real and Pop
SMPTypeCategory[NN_ffreep] = 1;              // Free Register and Pop
SMPTypeCategory[NN_fxch7] = 1;               // Alias of Exchange Registers
SMPTypeCategory[NN_fstp8] = 9;               // Alias of Store Real and Pop
SMPTypeCategory[NN_fstp9] = 9;               // Alias of Store Real and Pop

// Pentium 4 instructions
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SMPTypeCategory[NN_addpd] = 14;               // Add Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_addsd] = 14;               // Add Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_andnpd] = 14;              // Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_andpd] = 14;               // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
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SMPTypeCategory[NN_clflush] = 1;             // Flush Cache Line
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SMPTypeCategory[NN_cmppd] = 14;               // Compare Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_cmpsd] = 14;               // Compare Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_comisd] = 14;              // Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
SMPTypeCategory[NN_cvtdq2pd] = 14;            // Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_cvtdq2ps] = 14;            // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_cvtpd2dq] = 14;            // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_cvtpd2pi] = 14;            // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_cvtpd2ps] = 14;            // Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_cvtpi2pd] = 14;            // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_cvtps2dq] = 14;            // Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_cvtps2pd] = 14;            // Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_cvtsd2si] = 14;            // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
SMPTypeCategory[NN_cvtsd2ss] = 14;            // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
SMPTypeCategory[NN_cvtsi2sd] = 14;            // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_cvtss2sd] = 14;            // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_cvttpd2dq] = 14;           // Convert With Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_cvttpd2pi] = 14;           // Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_cvttps2dq] = 14;           // Convert With Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_cvttsd2si] = 14;           // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
SMPTypeCategory[NN_divpd] = 14;               // Divide Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_divsd] = 14;               // Divide Scalar Double-Precision Floating-Point Values
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SMPTypeCategory[NN_lfence] = 1;              // Load Fence
SMPTypeCategory[NN_maskmovdqu] = 13;          // Store Selected Bytes of Double Quadword  ** Infer dest is 'n'
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SMPTypeCategory[NN_maxpd] = 14;               // Return Maximum Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_maxsd] = 14;               // Return Maximum Scalar Double-Precision Floating-Point Value
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SMPTypeCategory[NN_mfence] = 1;              // Memory Fence
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SMPTypeCategory[NN_minpd] = 14;               // Return Minimum Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_minsd] = 14;               // Return Minimum Scalar Double-Precision Floating-Point Value
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SMPTypeCategory[NN_movapd] = 15;              // Move Aligned Packed Double-Precision Floating-Point Values  ** Infer dest is 'n'
SMPTypeCategory[NN_movdq2q] = 15;             // Move Quadword from XMM to MMX Register
SMPTypeCategory[NN_movdqa] = 15;              // Move Aligned Double Quadword  ** Infer dest is 'n'
SMPTypeCategory[NN_movdqu] = 15;              // Move Unaligned Double Quadword  ** Infer dest is 'n'
SMPTypeCategory[NN_movhpd] = 15;              // Move High Packed Double-Precision Floating-Point Values  ** Infer dest is 'n'
SMPTypeCategory[NN_movlpd] = 15;              // Move Low Packed Double-Precision Floating-Point Values  ** Infer dest is 'n'
SMPTypeCategory[NN_movmskpd] = 15;            // Extract Packed Double-Precision Floating-Point Sign Mask
SMPTypeCategory[NN_movntdq] = 13;             // Store Double Quadword Using Non-Temporal Hint
SMPTypeCategory[NN_movnti] = 13;              // Store Doubleword Using Non-Temporal Hint
SMPTypeCategory[NN_movntpd] = 13;             // Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
SMPTypeCategory[NN_movq2dq] = 1;             // Move Quadword from MMX to XMM Register
SMPTypeCategory[NN_movsd] = 15;               // Move Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_movupd] = 15;              // Move Unaligned Packed Double-Precision Floating-Point Values
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SMPTypeCategory[NN_mulpd] = 14;               // Multiply Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_mulsd] = 14;               // Multiply Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_orpd] = 14;                // Bitwise Logical OR of Double-Precision Floating-Point Values
SMPTypeCategory[NN_paddq] = 14;               // Add Packed Quadword Integers
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SMPTypeCategory[NN_pause] = 1;               // Spin Loop Hint
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SMPTypeCategory[NN_pmuludq] = 14;             // Multiply Packed Unsigned Doubleword Integers
SMPTypeCategory[NN_pshufd] = 14;              // Shuffle Packed Doublewords
SMPTypeCategory[NN_pshufhw] = 14;             // Shuffle Packed High Words
SMPTypeCategory[NN_pshuflw] = 14;             // Shuffle Packed Low Words
SMPTypeCategory[NN_pslldq] = 14;              // Shift Double Quadword Left Logical
SMPTypeCategory[NN_psrldq] = 14;              // Shift Double Quadword Right Logical
SMPTypeCategory[NN_psubq] = 14;               // Subtract Packed Quadword Integers
SMPTypeCategory[NN_punpckhqdq] = 14;          // Unpack High Data
SMPTypeCategory[NN_punpcklqdq] = 14;          // Unpack Low Data
SMPTypeCategory[NN_shufpd] = 14;              // Shuffle Packed Double-Precision Floating-Point Values
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SMPTypeCategory[NN_sqrtpd] = 1;              // Compute Square Roots of Packed Double-Precision Floating-Point Values
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SMPTypeCategory[NN_sqrtsd] = 14;              // Compute Square Rootof Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_subpd] = 14;               // Subtract Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_subsd] = 14;               // Subtract Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_ucomisd] = 14;             // Unordered Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
SMPTypeCategory[NN_unpckhpd] = 14;            // Unpack and Interleave High Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_unpcklpd] = 14;            // Unpack and Interleave Low Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_xorpd] = 14;               // Bitwise Logical OR of Double-Precision Floating-Point Values
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// AMD syscall/sysret instructions  NOTE: not AMD, found in Intel manual

SMPTypeCategory[NN_syscall] = 1;             // Low latency system call
SMPTypeCategory[NN_sysret] = 1;              // Return from system call

// AMD64 instructions    NOTE: not AMD, found in Intel manual

SMPTypeCategory[NN_swapgs] = 1;              // Exchange GS base with KernelGSBase MSR

// New Pentium instructions (SSE3)
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SMPTypeCategory[NN_movddup] = 14;             // Move One Double-FP and Duplicate
SMPTypeCategory[NN_movshdup] = 14;            // Move Packed Single-FP High and Duplicate
SMPTypeCategory[NN_movsldup] = 14;            // Move Packed Single-FP Low and Duplicate
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// Missing AMD64 instructions  NOTE: also found in Intel manual

SMPTypeCategory[NN_movsxd] = 2;              // Move with Sign-Extend Doubleword
SMPTypeCategory[NN_cmpxchg16b] = 0;          // Compare and Exchange 16 Bytes

// SSE3 instructions
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SMPTypeCategory[NN_addsubpd] = 14;            // Add /Sub packed DP FP numbers
SMPTypeCategory[NN_addsubps] = 14;            // Add /Sub packed SP FP numbers
SMPTypeCategory[NN_haddpd] = 14;              // Add horizontally packed DP FP numbers
SMPTypeCategory[NN_haddps] = 14;              // Add horizontally packed SP FP numbers
SMPTypeCategory[NN_hsubpd] = 14;              // Sub horizontally packed DP FP numbers
SMPTypeCategory[NN_hsubps] = 14;              // Sub horizontally packed SP FP numbers
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SMPTypeCategory[NN_monitor] = 1;             // Set up a linear address range to be monitored by hardware
SMPTypeCategory[NN_mwait] = 1;               // Wait until write-back store performed within the range specified by the MONITOR instruction
SMPTypeCategory[NN_fisttp] = 13;              // Store ST in intXX (chop) and pop
SMPTypeCategory[NN_lddqu] = 14;               // Load unaligned integer 128-bit

// SSSE3 instructions
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SMPTypeCategory[NN_psignb] = 14;              // Packed SIGN Byte
SMPTypeCategory[NN_psignw] = 14;              // Packed SIGN Word
SMPTypeCategory[NN_psignd] = 14;              // Packed SIGN Doubleword
SMPTypeCategory[NN_pshufb] = 14;              // Packed Shuffle Bytes
SMPTypeCategory[NN_pmulhrsw] = 14;            // Packed Multiply High with Round and Scale
SMPTypeCategory[NN_pmaddubsw] = 14;           // Multiply and Add Packed Signed and Unsigned Bytes
SMPTypeCategory[NN_phsubsw] = 14;             // Packed Horizontal Subtract and Saturate
SMPTypeCategory[NN_phaddsw] = 14;             // Packed Horizontal Add and Saturate
SMPTypeCategory[NN_phaddw] = 14;              // Packed Horizontal Add Word
SMPTypeCategory[NN_phaddd] = 14;              // Packed Horizontal Add Doubleword
SMPTypeCategory[NN_phsubw] = 14;              // Packed Horizontal Subtract Word
SMPTypeCategory[NN_phsubd] = 14;              // Packed Horizontal Subtract Doubleword
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SMPTypeCategory[NN_palignr] = 15;             // Packed Align Right
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SMPTypeCategory[NN_pabsb] = 14;               // Packed Absolute Value Byte
SMPTypeCategory[NN_pabsw] = 14;               // Packed Absolute Value Word
SMPTypeCategory[NN_pabsd] = 14;               // Packed Absolute Value Doubleword
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// VMX instructions

SMPTypeCategory[NN_vmcall] = 1;              // Call to VM Monitor
SMPTypeCategory[NN_vmclear] = 0;             // Clear Virtual Machine Control Structure
SMPTypeCategory[NN_vmlaunch] = 1;            // Launch Virtual Machine
SMPTypeCategory[NN_vmresume] = 1;            // Resume Virtual Machine
SMPTypeCategory[NN_vmptrld] = 6;             // Load Pointer to Virtual Machine Control Structure
SMPTypeCategory[NN_vmptrst] = 0;             // Store Pointer to Virtual Machine Control Structure
SMPTypeCategory[NN_vmread] = 0;              // Read Field from Virtual Machine Control Structure
SMPTypeCategory[NN_vmwrite] = 0;             // Write Field from Virtual Machine Control Structure
SMPTypeCategory[NN_vmxoff] = 1;              // Leave VMX Operation
SMPTypeCategory[NN_vmxon] = 1;               // Enter VMX Operation
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#if 599 < IDA_SDK_VERSION

SMPTypeCategory[NN_ud2] = 1;                 // Undefined Instruction

// Added with x86-64

SMPTypeCategory[NN_rdtscp] = 8;              // Read Time-Stamp Counter and Processor ID

// Geode LX 3DNow! extensions

SMPTypeCategory[NN_pfrcpv] = 1;              // Reciprocal Approximation for a Pair of 32-bit Floats
SMPTypeCategory[NN_pfrsqrtv] = 1;            // Reciprocal Square Root Approximation for a Pair of 32-bit Floats

// SSE2 pseudoinstructions

SMPTypeCategory[NN_cmpeqpd] = 1;             // Packed Double-FP Compare EQ
SMPTypeCategory[NN_cmpltpd] = 1;             // Packed Double-FP Compare LT
SMPTypeCategory[NN_cmplepd] = 1;             // Packed Double-FP Compare LE
SMPTypeCategory[NN_cmpunordpd] = 1;          // Packed Double-FP Compare UNORD
SMPTypeCategory[NN_cmpneqpd] = 1;            // Packed Double-FP Compare NOT EQ
SMPTypeCategory[NN_cmpnltpd] = 1;            // Packed Double-FP Compare NOT LT
SMPTypeCategory[NN_cmpnlepd] = 1;            // Packed Double-FP Compare NOT LE
SMPTypeCategory[NN_cmpordpd] = 1;            // Packed Double-FP Compare ORDERED
SMPTypeCategory[NN_cmpeqsd] = 1;             // Scalar Double-FP Compare EQ
SMPTypeCategory[NN_cmpltsd] = 1;             // Scalar Double-FP Compare LT
SMPTypeCategory[NN_cmplesd] = 1;             // Scalar Double-FP Compare LE
SMPTypeCategory[NN_cmpunordsd] = 1;          // Scalar Double-FP Compare UNORD
SMPTypeCategory[NN_cmpneqsd] = 1;            // Scalar Double-FP Compare NOT EQ
SMPTypeCategory[NN_cmpnltsd] = 1;            // Scalar Double-FP Compare NOT LT
SMPTypeCategory[NN_cmpnlesd] = 1;            // Scalar Double-FP Compare NOT LE
SMPTypeCategory[NN_cmpordsd] = 1;            // Scalar Double-FP Compare ORDERED

// SSSE4.1 instructions

SMPTypeCategory[NN_blendpd] = 14;             // Blend Packed Double Precision Floating-Point Values
SMPTypeCategory[NN_blendps] = 14;             // Blend Packed Single Precision Floating-Point Values
SMPTypeCategory[NN_blendvpd] = 14;            // Variable Blend Packed Double Precision Floating-Point Values
SMPTypeCategory[NN_blendvps] = 14;            // Variable Blend Packed Single Precision Floating-Point Values
SMPTypeCategory[NN_dppd] = 14;                // Dot Product of Packed Double Precision Floating-Point Values
SMPTypeCategory[NN_dpps] = 14;                // Dot Product of Packed Single Precision Floating-Point Values
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SMPTypeCategory[NN_extractps] = 15;            // Extract Packed Single Precision Floating-Point Value
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SMPTypeCategory[NN_insertps] = 14;            // Insert Packed Single Precision Floating-Point Value
SMPTypeCategory[NN_movntdqa] = 0;             // Load Double Quadword Non-Temporal Aligned Hint
SMPTypeCategory[NN_mpsadbw] = 1;              // Compute Multiple Packed Sums of Absolute Difference
SMPTypeCategory[NN_packusdw] = 14;            // Pack with Unsigned Saturation
SMPTypeCategory[NN_pblendvb] = 14;            // Variable Blend Packed Bytes
SMPTypeCategory[NN_pblendw] = 14;             // Blend Packed Words
SMPTypeCategory[NN_pcmpeqq] = 14;             // Compare Packed Qword Data for Equal
SMPTypeCategory[NN_pextrb] = 15;              // Extract Byte
SMPTypeCategory[NN_pextrd] = 15;              // Extract Dword
SMPTypeCategory[NN_pextrq] = 15;              // Extract Qword
SMPTypeCategory[NN_phminposuw] = 14;          // Packed Horizontal Word Minimum
SMPTypeCategory[NN_pinsrb] = 14;              // Insert Byte  !!! Could this be used as a generic move???
SMPTypeCategory[NN_pinsrd] = 14;              // Insert Dword  !!! Could this be used as a generic move???
SMPTypeCategory[NN_pinsrq] = 14;              // Insert Qword  !!! Could this be used as a generic move???
SMPTypeCategory[NN_pmaxsb] = 14;              // Maximum of Packed Signed Byte Integers
SMPTypeCategory[NN_pmaxsd] = 14;              // Maximum of Packed Signed Dword Integers
SMPTypeCategory[NN_pmaxud] = 14;              // Maximum of Packed Unsigned Dword Integers
SMPTypeCategory[NN_pmaxuw] = 14;              // Maximum of Packed Word Integers
SMPTypeCategory[NN_pminsb] = 14;              // Minimum of Packed Signed Byte Integers
SMPTypeCategory[NN_pminsd] = 14;              // Minimum of Packed Signed Dword Integers
SMPTypeCategory[NN_pminud] = 14;              // Minimum of Packed Unsigned Dword Integers
SMPTypeCategory[NN_pminuw] = 14;              // Minimum of Packed Word Integers
SMPTypeCategory[NN_pmovsxbw] = 14;            // Packed Move with Sign Extend
SMPTypeCategory[NN_pmovsxbd] = 14;            // Packed Move with Sign Extend
SMPTypeCategory[NN_pmovsxbq] = 14;            // Packed Move with Sign Extend
SMPTypeCategory[NN_pmovsxwd] = 14;            // Packed Move with Sign Extend
SMPTypeCategory[NN_pmovsxwq] = 14;            // Packed Move with Sign Extend
SMPTypeCategory[NN_pmovsxdq] = 14;            // Packed Move with Sign Extend
SMPTypeCategory[NN_pmovzxbw] = 14;            // Packed Move with Zero Extend
SMPTypeCategory[NN_pmovzxbd] = 14;            // Packed Move with Zero Extend
SMPTypeCategory[NN_pmovzxbq] = 14;            // Packed Move with Zero Extend
SMPTypeCategory[NN_pmovzxwd] = 14;            // Packed Move with Zero Extend
SMPTypeCategory[NN_pmovzxwq] = 14;            // Packed Move with Zero Extend
SMPTypeCategory[NN_pmovzxdq] = 14;            // Packed Move with Zero Extend
SMPTypeCategory[NN_pmuldq] = 14;              // Multiply Packed Signed Dword Integers
SMPTypeCategory[NN_pmulld] = 14;              // Multiply Packed Signed Dword Integers and Store Low Result
SMPTypeCategory[NN_ptest] = 1;                // Logical Compare
SMPTypeCategory[NN_roundpd] = 14;             // Round Packed Double Precision Floating-Point Values
SMPTypeCategory[NN_roundps] = 14;             // Round Packed Single Precision Floating-Point Values
SMPTypeCategory[NN_roundsd] = 14;             // Round Scalar Double Precision Floating-Point Values
SMPTypeCategory[NN_roundss] = 14;             // Round Scalar Single Precision Floating-Point Values

// SSSE4.2 instructions
SMPTypeCategory[NN_crc32] = 14;               // Accumulate CRC32 Value
SMPTypeCategory[NN_pcmpestri] = 2;            // Packed Compare Explicit Length Strings, Return Index
SMPTypeCategory[NN_pcmpestrm] = 2;            // Packed Compare Explicit Length Strings, Return Mask
SMPTypeCategory[NN_pcmpistri] = 2;            // Packed Compare Implicit Length Strings, Return Index
SMPTypeCategory[NN_pcmpistrm] = 2;            // Packed Compare Implicit Length Strings, Return Mask
SMPTypeCategory[NN_pcmpgtq] = 14;             // Compare Packed Data for Greater Than
SMPTypeCategory[NN_popcnt] = 2;               // Return the Count of Number of Bits Set to 1

// AMD SSE4a instructions
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SMPTypeCategory[NN_extrq] = 1;               // Extract Field From Register
SMPTypeCategory[NN_insertq] = 1;             // Insert Field
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Handle new opcodes in category tables.  
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SMPTypeCategory[NN_movntsd] = 13;             // Move Non-Temporal Scalar Double-Precision Floating-Point !!! Could this be used as a generic move???
SMPTypeCategory[NN_movntss] = 13;             // Move Non-Temporal Scalar Single-Precision Floating-Point !!! Could this be used as a generic move???
SMPTypeCategory[NN_lzcnt] = 2;                // Leading Zero Count

// xsave/xrstor instructions

SMPTypeCategory[NN_xgetbv] = 8;               // Get Value of Extended Control Register
SMPTypeCategory[NN_xrstor] = 0;               // Restore Processor Extended States
SMPTypeCategory[NN_xsave] = 1;                // Save Processor Extended States
SMPTypeCategory[NN_xsetbv] = 1;               // Set Value of Extended Control Register

// Intel Safer Mode Extensions (SMX)

SMPTypeCategory[NN_getsec] = 1;               // Safer Mode Extensions (SMX) Instruction

// AMD-V Virtualization ISA Extension

SMPTypeCategory[NN_clgi] = 0;                 // Clear Global Interrupt Flag
SMPTypeCategory[NN_invlpga] = 1;              // Invalidate TLB Entry in a Specified ASID
SMPTypeCategory[NN_skinit] = 1;               // Secure Init and Jump with Attestation
SMPTypeCategory[NN_stgi] = 0;                 // Set Global Interrupt Flag
SMPTypeCategory[NN_vmexit] = 1;               // Stop Executing Guest, Begin Executing Host
SMPTypeCategory[NN_vmload] = 0;               // Load State from VMCB
SMPTypeCategory[NN_vmmcall] = 1;              // Call VMM
SMPTypeCategory[NN_vmrun] = 1;                // Run Virtual Machine
SMPTypeCategory[NN_vmsave] = 0;               // Save State to VMCB

// VMX+ instructions

SMPTypeCategory[NN_invept] = 1;               // Invalidate Translations Derived from EPT
SMPTypeCategory[NN_invvpid] = 1;              // Invalidate Translations Based on VPID

// Intel Atom instructions

// !!!! continue work here
SMPTypeCategory[NN_movbe] = 3;                // Move Data After Swapping Bytes

// Intel AES instructions

SMPTypeCategory[NN_aesenc] = 14;              // Perform One Round of an AES Encryption Flow
SMPTypeCategory[NN_aesenclast] = 14;          // Perform the Last Round of an AES Encryption Flow
SMPTypeCategory[NN_aesdec] = 14;              // Perform One Round of an AES Decryption Flow
SMPTypeCategory[NN_aesdeclast] = 14;          // Perform the Last Round of an AES Decryption Flow
SMPTypeCategory[NN_aesimc] = 14;              // Perform the AES InvMixColumn Transformation
SMPTypeCategory[NN_aeskeygenassist] = 14;     // AES Round Key Generation Assist

// Carryless multiplication

SMPTypeCategory[NN_pclmulqdq] = 14;           // Carry-Less Multiplication Quadword
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// Returns modified by operand size prefixes

SMPTypeCategory[NN_retnw] = 0;               // Return Near from Procedure (use16)
SMPTypeCategory[NN_retnd] = 0;               // Return Near from Procedure (use32)
SMPTypeCategory[NN_retnq] = 0;               // Return Near from Procedure (use64)
SMPTypeCategory[NN_retfw] = 0;               // Return Far from Procedure (use16)
SMPTypeCategory[NN_retfd] = 0;               // Return Far from Procedure (use32)
SMPTypeCategory[NN_retfq] = 0;               // Return Far from Procedure (use64)

// RDRAND support

SMPTypeCategory[NN_rdrand] = 2;              // Read Random Number

// new GPR instructions

SMPTypeCategory[NN_adcx] = 5;                 // Unsigned Integer Addition of Two Operands with Carry Flag
SMPTypeCategory[NN_adox] = 5;                 // Unsigned Integer Addition of Two Operands with Overflow Flag
SMPTypeCategory[NN_andn] = 10;                // Logical AND NOT
SMPTypeCategory[NN_bextr] = 14;               // Bit Field Extract
SMPTypeCategory[NN_blsi] = 14;                // Extract Lowest Set Isolated Bit
SMPTypeCategory[NN_blsmsk] = 2;               // Get Mask Up to Lowest Set Bit
SMPTypeCategory[NN_blsr] = 2;                 // Reset Lowest Set Bit
SMPTypeCategory[NN_bzhi] = 2;                 // Zero High Bits Starting with Specified Bit Position
SMPTypeCategory[NN_clac] = 1;                 // Clear AC Flag in EFLAGS Register
SMPTypeCategory[NN_mulx] = 2;                 // Unsigned Multiply Without Affecting Flags
SMPTypeCategory[NN_pdep] = 2;                 // Parallel Bits Deposit
SMPTypeCategory[NN_pext] = 2;                 // Parallel Bits Extract
SMPTypeCategory[NN_rorx] = 2;                 // Rotate Right Logical Without Affecting Flags
SMPTypeCategory[NN_sarx] = 2;                 // Shift Arithmetically Right Without Affecting Flags
SMPTypeCategory[NN_shlx] = 2;                 // Shift Logically Left Without Affecting Flags
SMPTypeCategory[NN_shrx] = 2;                 // Shift Logically Right Without Affecting Flags
SMPTypeCategory[NN_stac] = 1;                  // Set AC Flag in EFLAGS Register
SMPTypeCategory[NN_tzcnt] = 2;                // Count the Number of Trailing Zero Bits
SMPTypeCategory[NN_xsaveopt] = 1;             // Save Processor Extended States Optimized
SMPTypeCategory[NN_invpcid] = 1;              // Invalidate Processor Context ID
SMPTypeCategory[NN_rdseed] = 2;               // Read Random Seed
SMPTypeCategory[NN_rdfsbase] = 6;             // Read FS Segment Base
SMPTypeCategory[NN_rdgsbase] = 6;             // Read GS Segment Base
SMPTypeCategory[NN_wrfsbase] = 6;             // Write FS Segment Base
SMPTypeCategory[NN_wrgsbase] = 6;             // Write GS Segment Base

// new AVX instructions

SMPTypeCategory[NN_vaddpd] = 14;               // Add Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vaddps] = 14;               // Packed Single-FP Add
SMPTypeCategory[NN_vaddsd] = 14;               // Add Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vaddss] = 14;               // Scalar Single-FP Add
SMPTypeCategory[NN_vaddsubpd] = 14;            // Add /Sub packed DP FP numbers
SMPTypeCategory[NN_vaddsubps] = 14;            // Add /Sub packed SP FP numbers
SMPTypeCategory[NN_vaesdec] = 14;              // Perform One Round of an AES Decryption Flow
SMPTypeCategory[NN_vaesdeclast] = 14;          // Perform the Last Round of an AES Decryption Flow
SMPTypeCategory[NN_vaesenc] = 14;              // Perform One Round of an AES Encryption Flow
SMPTypeCategory[NN_vaesenclast] = 14;          // Perform the Last Round of an AES Encryption Flow
SMPTypeCategory[NN_vaesimc] = 14;              // Perform the AES InvMixColumn Transformation
SMPTypeCategory[NN_vaeskeygenassist] = 14;     // AES Round Key Generation Assist
SMPTypeCategory[NN_vandnpd] = 14;              // Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vandnps] = 14;              // Bitwise Logical And Not for Single-FP
SMPTypeCategory[NN_vandpd] = 14;               // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vandps] = 14;               // Bitwise Logical And for Single-FP
SMPTypeCategory[NN_vblendpd] = 14;             // Blend Packed Double Precision Floating-Point Values
SMPTypeCategory[NN_vblendps] = 14;             // Blend Packed Single Precision Floating-Point Values
SMPTypeCategory[NN_vblendvpd] = 14;            // Variable Blend Packed Double Precision Floating-Point Values
SMPTypeCategory[NN_vblendvps] = 14;            // Variable Blend Packed Single Precision Floating-Point Values
SMPTypeCategory[NN_vbroadcastf128] = 14;       // Broadcast 128 Bits of Floating-Point Data
SMPTypeCategory[NN_vbroadcasti128] = 14;       // Broadcast 128 Bits of Integer Data
SMPTypeCategory[NN_vbroadcastsd] = 14;         // Broadcast Double-Precision Floating-Point Element
SMPTypeCategory[NN_vbroadcastss] = 14;         // Broadcast Single-Precision Floating-Point Element
SMPTypeCategory[NN_vcmppd] = 14;               // Compare Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vcmpps] = 14;               // Packed Single-FP Compare
SMPTypeCategory[NN_vcmpsd] = 14;               // Compare Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vcmpss] = 14;               // Scalar Single-FP Compare
SMPTypeCategory[NN_vcomisd] = 14;              // Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
SMPTypeCategory[NN_vcomiss] = 14;              // Scalar Ordered Single-FP Compare and Set EFLAGS
SMPTypeCategory[NN_vcvtdq2pd] = 14;            // Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vcvtdq2ps] = 14;            // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vcvtpd2dq] = 14;            // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_vcvtpd2ps] = 14;            // Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vcvtph2ps] = 14;            // Convert 16-bit FP Values to Single-Precision FP Values
SMPTypeCategory[NN_vcvtps2dq] = 14;            // Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_vcvtps2pd] = 14;            // Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vcvtps2ph] = 14;            // Convert Single-Precision FP value to 16-bit FP value
SMPTypeCategory[NN_vcvtsd2si] = 14;            // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
SMPTypeCategory[NN_vcvtsd2ss] = 14;            // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
SMPTypeCategory[NN_vcvtsi2sd] = 14;            // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_vcvtsi2ss] = 14;            // Scalar signed INT32 to Single-FP conversion
SMPTypeCategory[NN_vcvtss2sd] = 14;            // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_vcvtss2si] = 14;            // Scalar Single-FP to signed INT32 conversion
SMPTypeCategory[NN_vcvttpd2dq] = 14;           // Convert With Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_vcvttps2dq] = 14;           // Convert With Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_vcvttsd2si] = 14;           // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
SMPTypeCategory[NN_vcvttss2si] = 14;           // Scalar Single-FP to signed INT32 conversion (truncate)
SMPTypeCategory[NN_vdivpd] = 14;               // Divide Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vdivps] = 14;               // Packed Single-FP Divide
SMPTypeCategory[NN_vdivsd] = 14;               // Divide Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vdivss] = 14;               // Scalar Single-FP Divide
SMPTypeCategory[NN_vdppd] = 14;                // Dot Product of Packed Double Precision Floating-Point Values
SMPTypeCategory[NN_vdpps] = 14;                // Dot Product of Packed Single Precision Floating-Point Values
SMPTypeCategory[NN_vextractf128] = 14;         // Extract Packed Floating-Point Values
SMPTypeCategory[NN_vextracti128] = 14;         // Extract Packed Integer Values
SMPTypeCategory[NN_vextractps] = 14;           // Extract Packed Floating-Point Values
SMPTypeCategory[NN_vfmadd132pd] = 14;          // Fused Multiply-Add of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmadd132ps] = 14;          // Fused Multiply-Add of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmadd132sd] = 14;          // Fused Multiply-Add of Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmadd132ss] = 14;          // Fused Multiply-Add of Scalar Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmadd213pd] = 14;          // Fused Multiply-Add of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmadd213ps] = 14;          // Fused Multiply-Add of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmadd213sd] = 14;          // Fused Multiply-Add of Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmadd213ss] = 14;          // Fused Multiply-Add of Scalar Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmadd231pd] = 14;          // Fused Multiply-Add of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmadd231ps] = 14;          // Fused Multiply-Add of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmadd231sd] = 14;          // Fused Multiply-Add of Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmadd231ss] = 14;          // Fused Multiply-Add of Scalar Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmaddsub132pd] = 14;       // Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmaddsub132ps] = 14;       // Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmaddsub213pd] = 14;       // Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmaddsub213ps] = 14;       // Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmaddsub231pd] = 14;       // Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmaddsub231ps] = 14;       // Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsub132pd] = 14;          // Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsub132ps] = 14;          // Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsub132sd] = 14;          // Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsub132ss] = 14;          // Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsub213pd] = 14;          // Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsub213ps] = 14;          // Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsub213sd] = 14;          // Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsub213ss] = 14;          // Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsub231pd] = 14;          // Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsub231ps] = 14;          // Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsub231sd] = 14;          // Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsub231ss] = 14;          // Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsubadd132pd] = 14;       // Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsubadd132ps] = 14;       // Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsubadd213pd] = 14;       // Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsubadd213ps] = 14;       // Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsubadd231pd] = 14;       // Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfmsubadd231ps] = 14;       // Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmadd132pd] = 14;         // Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmadd132ps] = 14;         // Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmadd132sd] = 14;         // Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmadd132ss] = 14;         // Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmadd213pd] = 14;         // Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmadd213ps] = 14;         // Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmadd213sd] = 14;         // Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmadd213ss] = 14;         // Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmadd231pd] = 14;         // Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmadd231ps] = 14;         // Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmadd231sd] = 14;         // Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmadd231ss] = 14;         // Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmsub132pd] = 14;         // Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmsub132ps] = 14;         // Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmsub132sd] = 14;         // Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmsub132ss] = 14;         // Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmsub213pd] = 14;         // Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmsub213ps] = 14;         // Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmsub213sd] = 14;         // Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmsub213ss] = 14;         // Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmsub231pd] = 14;         // Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmsub231ps] = 14;         // Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmsub231sd] = 14;         // Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vfnmsub231ss] = 14;         // Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values
SMPTypeCategory[NN_vgatherdps] = 14;           // Gather Packed SP FP Values Using Signed Dword Indices
SMPTypeCategory[NN_vgatherdpd] = 14;           // Gather Packed DP FP Values Using Signed Dword Indices
SMPTypeCategory[NN_vgatherqps] = 14;           // Gather Packed SP FP Values Using Signed Qword Indices
SMPTypeCategory[NN_vgatherqpd] = 14;           // Gather Packed DP FP Values Using Signed Qword Indices
SMPTypeCategory[NN_vhaddpd] = 14;              // Add horizontally packed DP FP numbers
SMPTypeCategory[NN_vhaddps] = 14;              // Add horizontally packed SP FP numbers
SMPTypeCategory[NN_vhsubpd] = 14;              // Sub horizontally packed DP FP numbers
SMPTypeCategory[NN_vhsubps] = 14;              // Sub horizontally packed SP FP numbers
SMPTypeCategory[NN_vinsertf128] = 14;          // Insert Packed Floating-Point Values
SMPTypeCategory[NN_vinserti128] = 14;          // Insert Packed Integer Values
SMPTypeCategory[NN_vinsertps] = 14;            // Insert Packed Single Precision Floating-Point Value
SMPTypeCategory[NN_vlddqu] = 14;               // Load Unaligned Packed Integer Values
SMPTypeCategory[NN_vldmxcsr] = 14;             // Load Streaming SIMD Extensions Technology Control/Status Register
SMPTypeCategory[NN_vmaskmovdqu] = 15;          // Store Selected Bytes of Double Quadword with NT Hint
SMPTypeCategory[NN_vmaskmovpd] = 15;           // Conditionally Load Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vmaskmovps] = 15;           // Conditionally Load Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_vmaxpd] = 14;               // Return Maximum Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vmaxps] = 14;               // Packed Single-FP Maximum
SMPTypeCategory[NN_vmaxsd] = 14;               // Return Maximum Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_vmaxss] = 14;               // Scalar Single-FP Maximum
SMPTypeCategory[NN_vminpd] = 14;               // Return Minimum Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vminps] = 14;               // Packed Single-FP Minimum
SMPTypeCategory[NN_vminsd] = 14;               // Return Minimum Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_vminss] = 14;               // Scalar Single-FP Minimum
SMPTypeCategory[NN_vmovapd] = 15;              // Move Aligned Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vmovaps] = 15;              // Move Aligned Four Packed Single-FP
SMPTypeCategory[NN_vmovd] = 15;                // Move 32 bits
SMPTypeCategory[NN_vmovddup] = 15;             // Move One Double-FP and Duplicate
SMPTypeCategory[NN_vmovdqa] = 15;              // Move Aligned Double Quadword
SMPTypeCategory[NN_vmovdqu] = 15;              // Move Unaligned Double Quadword
SMPTypeCategory[NN_vmovhlps] = 15;             // Move High to Low Packed Single-FP
SMPTypeCategory[NN_vmovhpd] = 15;              // Move High Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vmovhps] = 15;              // Move High Packed Single-FP
SMPTypeCategory[NN_vmovlhps] = 15;             // Move Low to High Packed Single-FP
SMPTypeCategory[NN_vmovlpd] = 15;              // Move Low Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vmovlps] = 15;              // Move Low Packed Single-FP
SMPTypeCategory[NN_vmovmskpd] = 15;            // Extract Packed Double-Precision Floating-Point Sign Mask
SMPTypeCategory[NN_vmovmskps] = 15;            // Move Mask to Register
SMPTypeCategory[NN_vmovntdq] = 15;             // Store Double Quadword Using Non-Temporal Hint
SMPTypeCategory[NN_vmovntdqa] = 15;            // Load Double Quadword Non-Temporal Aligned Hint
SMPTypeCategory[NN_vmovntpd] = 15;             // Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
SMPTypeCategory[NN_vmovntps] = 15;             // Move Aligned Four Packed Single-FP Non Temporal
SMPTypeCategory[NN_vmovntsd] = 15;             // Move Non-Temporal Scalar Double-Precision Floating-Point
SMPTypeCategory[NN_vmovntss] = 15;             // Move Non-Temporal Scalar Single-Precision Floating-Point
SMPTypeCategory[NN_vmovq] = 15;                // Move 64 bits
SMPTypeCategory[NN_vmovsd] = 15;               // Move Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vmovshdup] = 15;            // Move Packed Single-FP High and Duplicate
SMPTypeCategory[NN_vmovsldup] = 15;            // Move Packed Single-FP Low and Duplicate
SMPTypeCategory[NN_vmovss] = 15;               // Move Scalar Single-FP
SMPTypeCategory[NN_vmovupd] = 15;              // Move Unaligned Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vmovups] = 15;              // Move Unaligned Four Packed Single-FP
SMPTypeCategory[NN_vmpsadbw] = 14;             // Compute Multiple Packed Sums of Absolute Difference
SMPTypeCategory[NN_vmulpd] = 14;               // Multiply Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_vmulps] = 14;               // Packed Single-FP Multiply
SMPTypeCategory[NN_vmulsd] = 14;               // Multiply Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_vmulss] = 14;               // Scalar Single-FP Multiply
SMPTypeCategory[NN_vorpd] = 14;                // Bitwise Logical OR of Double-Precision Floating-Point Values
SMPTypeCategory[NN_vorps] = 14;                // Bitwise Logical OR for Single-FP Data
SMPTypeCategory[NN_vpabsb] = 14;               // Packed Absolute Value Byte
SMPTypeCategory[NN_vpabsd] = 14;               // Packed Absolute Value Doubleword
SMPTypeCategory[NN_vpabsw] = 14;               // Packed Absolute Value Word
SMPTypeCategory[NN_vpackssdw] = 14;            // Pack with Signed Saturation (Dword->Word)
SMPTypeCategory[NN_vpacksswb] = 14;            // Pack with Signed Saturation (Word->Byte)
SMPTypeCategory[NN_vpackusdw] = 14;            // Pack with Unsigned Saturation
SMPTypeCategory[NN_vpackuswb] = 14;            // Pack with Unsigned Saturation (Word->Byte)
SMPTypeCategory[NN_vpaddb] = 14;               // Packed Add Byte
SMPTypeCategory[NN_vpaddd] = 14;               // Packed Add Dword
SMPTypeCategory[NN_vpaddq] = 14;               // Add Packed Quadword Integers
SMPTypeCategory[NN_vpaddsb] = 14;              // Packed Add with Saturation (Byte)
SMPTypeCategory[NN_vpaddsw] = 14;              // Packed Add with Saturation (Word)
SMPTypeCategory[NN_vpaddusb] = 14;             // Packed Add Unsigned with Saturation (Byte)
SMPTypeCategory[NN_vpaddusw] = 14;             // Packed Add Unsigned with Saturation (Word)
SMPTypeCategory[NN_vpaddw] = 14;               // Packed Add Word
SMPTypeCategory[NN_vpalignr] = 14;             // Packed Align Right
SMPTypeCategory[NN_vpand] = 14;                // Bitwise Logical And
SMPTypeCategory[NN_vpandn] = 14;               // Bitwise Logical And Not
SMPTypeCategory[NN_vpavgb] = 14;               // Packed Average (Byte)
SMPTypeCategory[NN_vpavgw] = 14;               // Packed Average (Word)
SMPTypeCategory[NN_vpblendd] = 14;             // Blend Packed Dwords
SMPTypeCategory[NN_vpblendvb] = 14;            // Variable Blend Packed Bytes
SMPTypeCategory[NN_vpblendw] = 14;             // Blend Packed Words
SMPTypeCategory[NN_vpbroadcastb] = 14;         // Broadcast a Byte Integer
SMPTypeCategory[NN_vpbroadcastd] = 14;         // Broadcast a Dword Integer
SMPTypeCategory[NN_vpbroadcastq] = 14;         // Broadcast a Qword Integer
SMPTypeCategory[NN_vpbroadcastw] = 14;         // Broadcast a Word Integer
SMPTypeCategory[NN_vpclmulqdq] = 14;           // Carry-Less Multiplication Quadword
SMPTypeCategory[NN_vpcmpeqb] = 14;             // Packed Compare for Equal (Byte)
SMPTypeCategory[NN_vpcmpeqd] = 14;             // Packed Compare for Equal (Dword)
SMPTypeCategory[NN_vpcmpeqq] = 14;             // Compare Packed Qword Data for Equal
SMPTypeCategory[NN_vpcmpeqw] = 14;             // Packed Compare for Equal (Word)
SMPTypeCategory[NN_vpcmpestri] = 14;           // Packed Compare Explicit Length Strings, Return Index
SMPTypeCategory[NN_vpcmpestrm] = 14;           // Packed Compare Explicit Length Strings, Return Mask
SMPTypeCategory[NN_vpcmpgtb] = 14;             // Packed Compare for Greater Than (Byte)
SMPTypeCategory[NN_vpcmpgtd] = 14;             // Packed Compare for Greater Than (Dword)
SMPTypeCategory[NN_vpcmpgtq] = 14;             // Compare Packed Data for Greater Than
SMPTypeCategory[NN_vpcmpgtw] = 14;             // Packed Compare for Greater Than (Word)
SMPTypeCategory[NN_vpcmpistri] = 14;           // Packed Compare Implicit Length Strings, Return Index
SMPTypeCategory[NN_vpcmpistrm] = 14;           // Packed Compare Implicit Length Strings, Return Mask
SMPTypeCategory[NN_vperm2f128] = 14;           // Permute Floating-Point Values
SMPTypeCategory[NN_vperm2i128] = 14;           // Permute Integer Values
SMPTypeCategory[NN_vpermd] = 14;               // Full Doublewords Element Permutation
SMPTypeCategory[NN_vpermilpd] = 14;            // Permute Double-Precision Floating-Point Values
SMPTypeCategory[NN_vpermilps] = 14;            // Permute Single-Precision Floating-Point Values
SMPTypeCategory[NN_vpermpd] = 14;              // Permute Double-Precision Floating-Point Elements
SMPTypeCategory[NN_vpermps] = 14;              // Permute Single-Precision Floating-Point Elements
SMPTypeCategory[NN_vpermq] = 14;               // Qwords Element Permutation
SMPTypeCategory[NN_vpextrb] = 14;              // Extract Byte
SMPTypeCategory[NN_vpextrd] = 14;              // Extract Dword
SMPTypeCategory[NN_vpextrq] = 14;              // Extract Qword
SMPTypeCategory[NN_vpextrw] = 14;              // Extract Word
SMPTypeCategory[NN_vpgatherdd] = 14;           // Gather Packed Dword Values Using Signed Dword Indices
SMPTypeCategory[NN_vpgatherdq] = 14;           // Gather Packed Qword Values Using Signed Dword Indices
SMPTypeCategory[NN_vpgatherqd] = 14;           // Gather Packed Dword Values Using Signed Qword Indices
SMPTypeCategory[NN_vpgatherqq] = 14;           // Gather Packed Qword Values Using Signed Qword Indices
SMPTypeCategory[NN_vphaddd] = 14;              // Packed Horizontal Add Doubleword
SMPTypeCategory[NN_vphaddsw] = 14;          // Packed Horizontal Add and Saturate
SMPTypeCategory[NN_vphaddw] = 14;           // Packed Horizontal Add Word
SMPTypeCategory[NN_vphminposuw] = 14;       // Packed Horizontal Word Minimum
SMPTypeCategory[NN_vphsubd] = 14;           // Packed Horizontal Subtract Doubleword
SMPTypeCategory[NN_vphsubsw] = 14;          // Packed Horizontal Subtract and Saturate
SMPTypeCategory[NN_vphsubw] = 14;           // Packed Horizontal Subtract Word
SMPTypeCategory[NN_vpinsrb] = 14;           // Insert Byte
SMPTypeCategory[NN_vpinsrd] = 14;           // Insert Dword
SMPTypeCategory[NN_vpinsrq] = 14;           // Insert Qword
SMPTypeCategory[NN_vpinsrw] = 14;           // Insert Word
SMPTypeCategory[NN_vpmaddubsw] = 14;        // Multiply and Add Packed Signed and Unsigned Bytes
SMPTypeCategory[NN_vpmaddwd] = 14;          // Packed Multiply and Add
SMPTypeCategory[NN_vpmaskmovd] = 15;        // Conditionally Store Dword Values Using Mask
SMPTypeCategory[NN_vpmaskmovq] = 15;        // Conditionally Store Qword Values Using Mask
SMPTypeCategory[NN_vpmaxsb] = 14;           // Maximum of Packed Signed Byte Integers
SMPTypeCategory[NN_vpmaxsd] = 14;           // Maximum of Packed Signed Dword Integers
SMPTypeCategory[NN_vpmaxsw] = 14;           // Packed Signed Integer Word Maximum
SMPTypeCategory[NN_vpmaxub] = 14;           // Packed Unsigned Integer Byte Maximum
SMPTypeCategory[NN_vpmaxud] = 14;           // Maximum of Packed Unsigned Dword Integers
SMPTypeCategory[NN_vpmaxuw] = 14;           // Maximum of Packed Word Integers
SMPTypeCategory[NN_vpminsb] = 14;           // Minimum of Packed Signed Byte Integers
SMPTypeCategory[NN_vpminsd] = 14;           // Minimum of Packed Signed Dword Integers
SMPTypeCategory[NN_vpminsw] = 14;           // Packed Signed Integer Word Minimum
SMPTypeCategory[NN_vpminub] = 14;           // Packed Unsigned Integer Byte Minimum
SMPTypeCategory[NN_vpminud] = 14;           // Minimum of Packed Unsigned Dword Integers
SMPTypeCategory[NN_vpminuw] = 14;           // Minimum of Packed Word Integers
SMPTypeCategory[NN_vpmovmskb] = 15;         // Move Byte Mask to Integer
SMPTypeCategory[NN_vpmovsxbd] = 15;         // Packed Move with Sign Extend
SMPTypeCategory[NN_vpmovsxbq] = 15;         // Packed Move with Sign Extend
SMPTypeCategory[NN_vpmovsxbw] = 15;         // Packed Move with Sign Extend
SMPTypeCategory[NN_vpmovsxdq] = 15;         // Packed Move with Sign Extend
SMPTypeCategory[NN_vpmovsxwd] = 15;         // Packed Move with Sign Extend
SMPTypeCategory[NN_vpmovsxwq] = 15;         // Packed Move with Sign Extend
SMPTypeCategory[NN_vpmovzxbd] = 15;         // Packed Move with Zero Extend
SMPTypeCategory[NN_vpmovzxbq] = 15;         // Packed Move with Zero Extend
SMPTypeCategory[NN_vpmovzxbw] = 15;         // Packed Move with Zero Extend
SMPTypeCategory[NN_vpmovzxdq] = 15;         // Packed Move with Zero Extend
SMPTypeCategory[NN_vpmovzxwd] = 15;         // Packed Move with Zero Extend
SMPTypeCategory[NN_vpmovzxwq] = 15;         // Packed Move with Zero Extend
SMPTypeCategory[NN_vpmuldq] = 14;           // Multiply Packed Signed Dword Integers
SMPTypeCategory[NN_vpmulhrsw] = 14;         // Packed Multiply High with Round and Scale
SMPTypeCategory[NN_vpmulhuw] = 14;          // Packed Multiply High Unsigned
SMPTypeCategory[NN_vpmulhw] = 14;           // Packed Multiply High
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