SMPDataFlowAnalysis.cpp

SMPDefsFlags[NN_setbe] = false;               // Set Byte if Below or Equal (CF=1 | ZF=1)
SMPDefsFlags[NN_setc] = false;                // Set Byte if Carry (CF=1)
SMPDefsFlags[NN_sete] = false;                // Set Byte if Equal (ZF=1)
SMPDefsFlags[NN_setg] = false;                // Set Byte if Greater (ZF=0 & SF=OF)
SMPDefsFlags[NN_setge] = false;               // Set Byte if Greater or Equal (SF=OF)
SMPDefsFlags[NN_setl] = false;                // Set Byte if Less (SF!=OF)
SMPDefsFlags[NN_setle] = false;               // Set Byte if Less or Equal (ZF=1 | SF!=OF)
SMPDefsFlags[NN_setna] = false;               // Set Byte if Not Above (CF=1 | ZF=1)
SMPDefsFlags[NN_setnae] = false;              // Set Byte if Not Above or Equal (CF=1)
SMPDefsFlags[NN_setnb] = false;               // Set Byte if Not Below (CF=0)
SMPDefsFlags[NN_setnbe] = false;              // Set Byte if Not Below or Equal (CF=0 & ZF=0)
SMPDefsFlags[NN_setnc] = false;               // Set Byte if Not Carry (CF=0)
SMPDefsFlags[NN_setne] = false;               // Set Byte if Not Equal (ZF=0)
SMPDefsFlags[NN_setng] = false;               // Set Byte if Not Greater (ZF=1 | SF!=OF)
SMPDefsFlags[NN_setnge] = false;              // Set Byte if Not Greater or Equal (ZF=1)
SMPDefsFlags[NN_setnl] = false;               // Set Byte if Not Less (SF=OF)
SMPDefsFlags[NN_setnle] = false;              // Set Byte if Not Less or Equal (ZF=0 & SF=OF)
SMPDefsFlags[NN_setno] = false;               // Set Byte if Not Overflow (OF=0)
SMPDefsFlags[NN_setnp] = false;               // Set Byte if Not Parity (PF=0)
SMPDefsFlags[NN_setns] = false;               // Set Byte if Not Sign (SF=0)
SMPDefsFlags[NN_setnz] = false;               // Set Byte if Not Zero (ZF=0)
SMPDefsFlags[NN_seto] = false;                // Set Byte if Overflow (OF=1)
SMPDefsFlags[NN_setp] = false;                // Set Byte if Parity (PF=1)
SMPDefsFlags[NN_setpe] = false;               // Set Byte if Parity Even (PF=1)
SMPDefsFlags[NN_setpo] = false;               // Set Byte if Parity Odd  (PF=0)
SMPDefsFlags[NN_sets] = false;                // Set Byte if Sign (SF=1)
SMPDefsFlags[NN_setz] = false;                // Set Byte if Zero (ZF=1)
SMPDefsFlags[NN_sgdt] = false;                // Store Global Descriptor Table Register
SMPDefsFlags[NN_sidt] = false;                // Store Interrupt Descriptor Table Register
SMPDefsFlags[NN_sldt] = false;                // Store Local Descriptor Table Register
SMPDefsFlags[NN_str] = false;                 // Store Task Register
SMPDefsFlags[NN_wait] = false;                // Wait until BUSY# Pin is Inactive (HIGH)
SMPDefsFlags[NN_xchg] = false;                // Exchange Register/Memory with Register
SMPDefsFlags[NN_xlat] = false;                // Table Lookup Translation

//
//      486 instructions
//

SMPDefsFlags[NN_bswap] = false;               // Swap bytes in register
SMPDefsFlags[NN_invd] = false;                // Invalidate Data Cache
SMPDefsFlags[NN_wbinvd] = false;              // Invalidate Data Cache (write changes)
SMPDefsFlags[NN_invlpg] = false;              // Invalidate TLB entry

//
//      Pentium instructions
//

SMPDefsFlags[NN_rdmsr] = false;               // Read Machine Status Register
SMPDefsFlags[NN_wrmsr] = false;               // Write Machine Status Register
SMPDefsFlags[NN_cpuid] = false;               // Get CPU ID
SMPDefsFlags[NN_rdtsc] = false;               // Read Time Stamp Counter

//
//      Pentium Pro instructions
//

SMPDefsFlags[NN_cmova] = false;               // Move if Above (CF=0 & ZF=0)
SMPDefsFlags[NN_cmovb] = false;               // Move if Below (CF=1)
SMPDefsFlags[NN_cmovbe] = false;              // Move if Below or Equal (CF=1 | ZF=1)
SMPDefsFlags[NN_cmovg] = false;               // Move if Greater (ZF=0 & SF=OF)
SMPDefsFlags[NN_cmovge] = false;              // Move if Greater or Equal (SF=OF)
SMPDefsFlags[NN_cmovl] = false;               // Move if Less (SF!=OF)
SMPDefsFlags[NN_cmovle] = false;              // Move if Less or Equal (ZF=1 | SF!=OF)
SMPDefsFlags[NN_cmovnb] = false;              // Move if Not Below (CF=0)
SMPDefsFlags[NN_cmovno] = false;              // Move if Not Overflow (OF=0)
SMPDefsFlags[NN_cmovnp] = false;              // Move if Not Parity (PF=0)
SMPDefsFlags[NN_cmovns] = false;              // Move if Not Sign (SF=0)
SMPDefsFlags[NN_cmovnz] = false;              // Move if Not Zero (ZF=0)
SMPDefsFlags[NN_cmovo] = false;               // Move if Overflow (OF=1)
SMPDefsFlags[NN_cmovp] = false;               // Move if Parity (PF=1)
SMPDefsFlags[NN_cmovs] = false;               // Move if Sign (SF=1)
SMPDefsFlags[NN_cmovz] = false;               // Move if Zero (ZF=1)
SMPDefsFlags[NN_fcmovb] = false;              // Floating Move if Below          
SMPDefsFlags[NN_fcmove] = false;              // Floating Move if Equal          
SMPDefsFlags[NN_fcmovbe] = false;             // Floating Move if Below or Equal 
SMPDefsFlags[NN_fcmovu] = false;              // Floating Move if Unordered      
SMPDefsFlags[NN_fcmovnb] = false;             // Floating Move if Not Below      
SMPDefsFlags[NN_fcmovne] = false;             // Floating Move if Not Equal      
SMPDefsFlags[NN_fcmovnbe] = false;            // Floating Move if Not Below or Equal
SMPDefsFlags[NN_fcmovnu] = false;             // Floating Move if Not Unordered     
SMPDefsFlags[NN_rdpmc] = false;               // Read Performance Monitor Counter

//
//      FPP instructions
//

SMPDefsFlags[NN_fld] = false;                 // Load Real              
SMPDefsFlags[NN_fst] = false;                 // Store Real            
SMPDefsFlags[NN_fstp] = false;                // Store Real and Pop   
SMPDefsFlags[NN_fxch] = false;                // Exchange Registers
SMPDefsFlags[NN_fild] = false;                // Load Integer           
SMPDefsFlags[NN_fist] = false;                // Store Integer
SMPDefsFlags[NN_fistp] = false;               // Store Integer and Pop
SMPDefsFlags[NN_fbld] = false;                // Load BCD
SMPDefsFlags[NN_fbstp] = false;               // Store BCD and Pop
SMPDefsFlags[NN_fadd] = false;                // Add Real
SMPDefsFlags[NN_faddp] = false;               // Add Real and Pop
SMPDefsFlags[NN_fiadd] = false;               // Add Integer
SMPDefsFlags[NN_fsub] = false;                // Subtract Real
SMPDefsFlags[NN_fsubp] = false;               // Subtract Real and Pop
SMPDefsFlags[NN_fisub] = false;               // Subtract Integer
SMPDefsFlags[NN_fsubr] = false;               // Subtract Real Reversed
SMPDefsFlags[NN_fsubrp] = false;              // Subtract Real Reversed and Pop
SMPDefsFlags[NN_fisubr] = false;              // Subtract Integer Reversed
SMPDefsFlags[NN_fmul] = false;                // Multiply Real
SMPDefsFlags[NN_fmulp] = false;               // Multiply Real and Pop
SMPDefsFlags[NN_fimul] = false;               // Multiply Integer
SMPDefsFlags[NN_fdiv] = false;                // Divide Real
SMPDefsFlags[NN_fdivp] = false;               // Divide Real and Pop
SMPDefsFlags[NN_fidiv] = false;               // Divide Integer
SMPDefsFlags[NN_fdivr] = false;               // Divide Real Reversed
SMPDefsFlags[NN_fdivrp] = false;              // Divide Real Reversed and Pop
SMPDefsFlags[NN_fidivr] = false;              // Divide Integer Reversed
SMPDefsFlags[NN_fsqrt] = false;               // Square Root
SMPDefsFlags[NN_fscale] = false;              // Scale:  st(0) <- st(0) * 2^st(1)
SMPDefsFlags[NN_fprem] = false;               // Partial Remainder
SMPDefsFlags[NN_frndint] = false;             // Round to Integer
SMPDefsFlags[NN_fxtract] = false;             // Extract exponent and significand
SMPDefsFlags[NN_fabs] = false;                // Absolute value
SMPDefsFlags[NN_fchs] = false;                // Change Sign
SMPDefsFlags[NN_ficom] = false;               // Compare Integer
SMPDefsFlags[NN_ficomp] = false;              // Compare Integer and Pop
SMPDefsFlags[NN_ftst] = false;                // Test
SMPDefsFlags[NN_fxam] = false;                // Examine
SMPDefsFlags[NN_fptan] = false;               // Partial tangent
SMPDefsFlags[NN_fpatan] = false;              // Partial arctangent
SMPDefsFlags[NN_f2xm1] = false;               // 2^x - 1
SMPDefsFlags[NN_fyl2x] = false;               // Y * lg2(X)
SMPDefsFlags[NN_fyl2xp1] = false;             // Y * lg2(X+1)
SMPDefsFlags[NN_fldz] = false;                // Load +0.0
SMPDefsFlags[NN_fld1] = false;                // Load +1.0
SMPDefsFlags[NN_fldpi] = false;               // Load PI=3.14...
SMPDefsFlags[NN_fldl2t] = false;              // Load lg2(10)
SMPDefsFlags[NN_fldl2e] = false;              // Load lg2(e)
SMPDefsFlags[NN_fldlg2] = false;              // Load lg10(2)
SMPDefsFlags[NN_fldln2] = false;              // Load ln(2)
SMPDefsFlags[NN_finit] = false;               // Initialize Processor
SMPDefsFlags[NN_fninit] = false;              // Initialize Processor (no wait)
SMPDefsFlags[NN_fsetpm] = false;              // Set Protected Mode
SMPDefsFlags[NN_fldcw] = false;               // Load Control Word
SMPDefsFlags[NN_fstcw] = false;               // Store Control Word
SMPDefsFlags[NN_fnstcw] = false;              // Store Control Word (no wait)
SMPDefsFlags[NN_fstsw] = false;               // Store Status Word to memory or AX
SMPDefsFlags[NN_fnstsw] = false;              // Store Status Word (no wait) to memory or AX
SMPDefsFlags[NN_fclex] = false;               // Clear Exceptions
SMPDefsFlags[NN_fnclex] = false;              // Clear Exceptions (no wait)
SMPDefsFlags[NN_fstenv] = false;              // Store Environment
SMPDefsFlags[NN_fnstenv] = false;             // Store Environment (no wait)
SMPDefsFlags[NN_fldenv] = false;              // Load Environment
SMPDefsFlags[NN_fsave] = false;               // Save State
SMPDefsFlags[NN_fnsave] = false;              // Save State (no wait)
SMPDefsFlags[NN_frstor] = false;              // Restore State      
SMPDefsFlags[NN_fincstp] = false;             // Increment Stack Pointer
SMPDefsFlags[NN_fdecstp] = false;             // Decrement Stack Pointer
SMPDefsFlags[NN_ffree] = false;               // Free Register
SMPDefsFlags[NN_fnop] = false;                // No Operation
SMPDefsFlags[NN_feni] = false;                // (8087 only)
SMPDefsFlags[NN_fneni] = false;               // (no wait) (8087 only)
SMPDefsFlags[NN_fdisi] = false;               // (8087 only)
SMPDefsFlags[NN_fndisi] = false;              // (no wait) (8087 only)

//
//      80387 instructions
//

SMPDefsFlags[NN_fprem1] = false;              // Partial Remainder ( < half )
SMPDefsFlags[NN_fsincos] = false;             // t<-cos(st); st<-sin(st); push t
SMPDefsFlags[NN_fsin] = false;                // Sine
SMPDefsFlags[NN_fcos] = false;                // Cosine
SMPDefsFlags[NN_fucom] = false;               // Compare Unordered Real
SMPDefsFlags[NN_fucomp] = false;              // Compare Unordered Real and Pop
SMPDefsFlags[NN_fucompp] = false;             // Compare Unordered Real and Pop Twice

//
//      Instructions added 28.02.96
//

SMPDefsFlags[NN_svdc] = false;                // Save Register and Descriptor
SMPDefsFlags[NN_rsdc] = false;                // Restore Register and Descriptor
SMPDefsFlags[NN_svldt] = false;               // Save LDTR and Descriptor
SMPDefsFlags[NN_rsldt] = false;               // Restore LDTR and Descriptor
SMPDefsFlags[NN_svts] = false;                // Save TR and Descriptor
SMPDefsFlags[NN_rsts] = false;                // Restore TR and Descriptor
SMPDefsFlags[NN_icebp] = false;               // ICE Break Point

//
//      MMX instructions
//

SMPDefsFlags[NN_emms] = false;                // Empty MMX state
SMPDefsFlags[NN_movd] = false;                // Move 32 bits
SMPDefsFlags[NN_movq] = false;                // Move 64 bits
SMPDefsFlags[NN_packsswb] = false;            // Pack with Signed Saturation (Word->Byte)
SMPDefsFlags[NN_packssdw] = false;            // Pack with Signed Saturation (Dword->Word)
SMPDefsFlags[NN_packuswb] = false;            // Pack with Unsigned Saturation (Word->Byte)
SMPDefsFlags[NN_paddb] = false;               // Packed Add Byte
SMPDefsFlags[NN_paddw] = false;               // Packed Add Word
SMPDefsFlags[NN_paddd] = false;               // Packed Add Dword
SMPDefsFlags[NN_paddsb] = false;              // Packed Add with Saturation (Byte)
SMPDefsFlags[NN_paddsw] = false;              // Packed Add with Saturation (Word)
SMPDefsFlags[NN_paddusb] = false;             // Packed Add Unsigned with Saturation (Byte)
SMPDefsFlags[NN_paddusw] = false;             // Packed Add Unsigned with Saturation (Word)
SMPDefsFlags[NN_pand] = false;                // Bitwise Logical And
SMPDefsFlags[NN_pandn] = false;               // Bitwise Logical And Not
SMPDefsFlags[NN_pcmpeqb] = false;             // Packed Compare for Equal (Byte)
SMPDefsFlags[NN_pcmpeqw] = false;             // Packed Compare for Equal (Word)
SMPDefsFlags[NN_pcmpeqd] = false;             // Packed Compare for Equal (Dword)
SMPDefsFlags[NN_pcmpgtb] = false;             // Packed Compare for Greater Than (Byte)
SMPDefsFlags[NN_pcmpgtw] = false;             // Packed Compare for Greater Than (Word)
SMPDefsFlags[NN_pcmpgtd] = false;             // Packed Compare for Greater Than (Dword)
SMPDefsFlags[NN_pmaddwd] = false;             // Packed Multiply and Add
SMPDefsFlags[NN_pmulhw] = false;              // Packed Multiply High
SMPDefsFlags[NN_pmullw] = false;              // Packed Multiply Low
SMPDefsFlags[NN_por] = false;                 // Bitwise Logical Or
SMPDefsFlags[NN_psllw] = false;               // Packed Shift Left Logical (Word)
SMPDefsFlags[NN_pslld] = false;               // Packed Shift Left Logical (Dword)
SMPDefsFlags[NN_psllq] = false;               // Packed Shift Left Logical (Qword)
SMPDefsFlags[NN_psraw] = false;               // Packed Shift Right Arithmetic (Word)
SMPDefsFlags[NN_psrad] = false;               // Packed Shift Right Arithmetic (Dword)
SMPDefsFlags[NN_psrlw] = false;               // Packed Shift Right Logical (Word)
SMPDefsFlags[NN_psrld] = false;               // Packed Shift Right Logical (Dword)
SMPDefsFlags[NN_psrlq] = false;               // Packed Shift Right Logical (Qword)
SMPDefsFlags[NN_psubb] = false;               // Packed Subtract Byte
SMPDefsFlags[NN_psubw] = false;               // Packed Subtract Word
SMPDefsFlags[NN_psubd] = false;               // Packed Subtract Dword
SMPDefsFlags[NN_psubsb] = false;              // Packed Subtract with Saturation (Byte)
SMPDefsFlags[NN_psubsw] = false;              // Packed Subtract with Saturation (Word)
SMPDefsFlags[NN_psubusb] = false;             // Packed Subtract Unsigned with Saturation (Byte)
SMPDefsFlags[NN_psubusw] = false;             // Packed Subtract Unsigned with Saturation (Word)
SMPDefsFlags[NN_punpckhbw] = false;           // Unpack High Packed Data (Byte->Word)
SMPDefsFlags[NN_punpckhwd] = false;           // Unpack High Packed Data (Word->Dword)
SMPDefsFlags[NN_punpckhdq] = false;           // Unpack High Packed Data (Dword->Qword)
SMPDefsFlags[NN_punpcklbw] = false;           // Unpack Low Packed Data (Byte->Word)
SMPDefsFlags[NN_punpcklwd] = false;           // Unpack Low Packed Data (Word->Dword)
SMPDefsFlags[NN_punpckldq] = false;           // Unpack Low Packed Data (Dword->Qword)
SMPDefsFlags[NN_pxor] = false;                // Bitwise Logical Exclusive Or

//
//      Undocumented Deschutes processor instructions
//

SMPDefsFlags[NN_fxsave] = false;              // Fast save FP context        
SMPDefsFlags[NN_fxrstor] = false;             // Fast restore FP context     

//      Pentium II instructions

SMPDefsFlags[NN_sysexit] = false;             // Fast Transition from System Call Entry Point

//      3DNow! instructions

SMPDefsFlags[NN_pavgusb] = false;             // Packed 8-bit Unsigned Integer Averaging
SMPDefsFlags[NN_pfadd] = false;               // Packed Floating-Point Addition
SMPDefsFlags[NN_pfsub] = false;               // Packed Floating-Point Subtraction
SMPDefsFlags[NN_pfsubr] = false;              // Packed Floating-Point Reverse Subtraction
SMPDefsFlags[NN_pfacc] = false;               // Packed Floating-Point Accumulate
SMPDefsFlags[NN_pfcmpge] = false;             // Packed Floating-Point Comparison, Greater or Equal
SMPDefsFlags[NN_pfcmpgt] = false;             // Packed Floating-Point Comparison, Greater
SMPDefsFlags[NN_pfcmpeq] = false;             // Packed Floating-Point Comparison, Equal
SMPDefsFlags[NN_pfmin] = false;               // Packed Floating-Point Minimum
SMPDefsFlags[NN_pfmax] = false;               // Packed Floating-Point Maximum
SMPDefsFlags[NN_pi2fd] = false;               // Packed 32-bit Integer to Floating-Point
SMPDefsFlags[NN_pf2id] = false;               // Packed Floating-Point to 32-bit Integer
SMPDefsFlags[NN_pfrcp] = false;               // Packed Floating-Point Reciprocal Approximation
SMPDefsFlags[NN_pfrsqrt] = false;             // Packed Floating-Point Reciprocal Square Root Approximation
SMPDefsFlags[NN_pfmul] = false;               // Packed Floating-Point Multiplication
SMPDefsFlags[NN_pfrcpit1] = false;            // Packed Floating-Point Reciprocal First Iteration Step
SMPDefsFlags[NN_pfrsqit1] = false;            // Packed Floating-Point Reciprocal Square Root First Iteration Step
SMPDefsFlags[NN_pfrcpit2] = false;            // Packed Floating-Point Reciprocal Second Iteration Step
SMPDefsFlags[NN_pmulhrw] = false;             // Packed Floating-Point 16-bit Integer Multiply with rounding
SMPDefsFlags[NN_femms] = false;               // Faster entry/exit of the MMX or floating-point state
SMPDefsFlags[NN_prefetch] = false;            // Prefetch at least a 32-byte line into L1 data cache
SMPDefsFlags[NN_prefetchw] = false;           // Prefetch processor cache line into L1 data cache (mark as modified)


//      Pentium III instructions

SMPDefsFlags[NN_addps] = false;               // Packed Single-FP Add
SMPDefsFlags[NN_addss] = false;               // Scalar Single-FP Add
SMPDefsFlags[NN_andnps] = false;              // Bitwise Logical And Not for Single-FP
SMPDefsFlags[NN_andps] = false;               // Bitwise Logical And for Single-FP
SMPDefsFlags[NN_cmpps] = false;               // Packed Single-FP Compare
SMPDefsFlags[NN_cmpss] = false;               // Scalar Single-FP Compare
SMPDefsFlags[NN_cvtpi2ps] = false;            // Packed signed INT32 to Packed Single-FP conversion
SMPDefsFlags[NN_cvtps2pi] = false;            // Packed Single-FP to Packed INT32 conversion
SMPDefsFlags[NN_cvtsi2ss] = false;            // Scalar signed INT32 to Single-FP conversion
SMPDefsFlags[NN_cvtss2si] = false;            // Scalar Single-FP to signed INT32 conversion
SMPDefsFlags[NN_cvttps2pi] = false;           // Packed Single-FP to Packed INT32 conversion (truncate)
SMPDefsFlags[NN_cvttss2si] = false;           // Scalar Single-FP to signed INT32 conversion (truncate)
SMPDefsFlags[NN_divps] = false;               // Packed Single-FP Divide
SMPDefsFlags[NN_divss] = false;               // Scalar Single-FP Divide
SMPDefsFlags[NN_ldmxcsr] = false;             // Load Streaming SIMD Extensions Technology Control/Status Register
SMPDefsFlags[NN_maxps] = false;               // Packed Single-FP Maximum
SMPDefsFlags[NN_maxss] = false;               // Scalar Single-FP Maximum
SMPDefsFlags[NN_minps] = false;               // Packed Single-FP Minimum
SMPDefsFlags[NN_minss] = false;               // Scalar Single-FP Minimum
SMPDefsFlags[NN_movaps] = false;              // Move Aligned Four Packed Single-FP  
SMPDefsFlags[NN_movhlps] = false;             // Move High to Low Packed Single-FP
SMPDefsFlags[NN_movhps] = false;              // Move High Packed Single-FP
SMPDefsFlags[NN_movlhps] = false;             // Move Low to High Packed Single-FP
SMPDefsFlags[NN_movlps] = false;              // Move Low Packed Single-FP
SMPDefsFlags[NN_movmskps] = false;            // Move Mask to Register
SMPDefsFlags[NN_movss] = false;               // Move Scalar Single-FP
SMPDefsFlags[NN_movups] = false;              // Move Unaligned Four Packed Single-FP
SMPDefsFlags[NN_mulps] = false;               // Packed Single-FP Multiply
SMPDefsFlags[NN_mulss] = false;               // Scalar Single-FP Multiply
SMPDefsFlags[NN_orps] = false;                // Bitwise Logical OR for Single-FP Data
SMPDefsFlags[NN_rcpps] = false;               // Packed Single-FP Reciprocal
SMPDefsFlags[NN_rcpss] = false;               // Scalar Single-FP Reciprocal
SMPDefsFlags[NN_rsqrtps] = false;             // Packed Single-FP Square Root Reciprocal
SMPDefsFlags[NN_rsqrtss] = false;             // Scalar Single-FP Square Root Reciprocal
SMPDefsFlags[NN_shufps] = false;              // Shuffle Single-FP
SMPDefsFlags[NN_sqrtps] = false;              // Packed Single-FP Square Root
SMPDefsFlags[NN_sqrtss] = false;              // Scalar Single-FP Square Root
SMPDefsFlags[NN_stmxcsr] = false;             // Store Streaming SIMD Extensions Technology Control/Status Register 
SMPDefsFlags[NN_subps] = false;               // Packed Single-FP Subtract
SMPDefsFlags[NN_subss] = false;               // Scalar Single-FP Subtract
SMPDefsFlags[NN_unpckhps] = false;            // Unpack High Packed Single-FP Data
SMPDefsFlags[NN_unpcklps] = false;            // Unpack Low Packed Single-FP Data
SMPDefsFlags[NN_xorps] = false;               // Bitwise Logical XOR for Single-FP Data
SMPDefsFlags[NN_pavgb] = false;               // Packed Average (Byte)
SMPDefsFlags[NN_pavgw] = false;               // Packed Average (Word)
SMPDefsFlags[NN_pextrw] = false;              // Extract Word
SMPDefsFlags[NN_pinsrw] = false;              // Insert Word
SMPDefsFlags[NN_pmaxsw] = false;              // Packed Signed Integer Word Maximum
SMPDefsFlags[NN_pmaxub] = false;              // Packed Unsigned Integer Byte Maximum
SMPDefsFlags[NN_pminsw] = false;              // Packed Signed Integer Word Minimum
SMPDefsFlags[NN_pminub] = false;              // Packed Unsigned Integer Byte Minimum
SMPDefsFlags[NN_pmovmskb] = false;            // Move Byte Mask to Integer
SMPDefsFlags[NN_pmulhuw] = false;             // Packed Multiply High Unsigned
SMPDefsFlags[NN_psadbw] = false;              // Packed Sum of Absolute Differences
SMPDefsFlags[NN_pshufw] = false;              // Packed Shuffle Word
SMPDefsFlags[NN_maskmovq] = false;            // Byte Mask write  
SMPDefsFlags[NN_movntps] = false;             // Move Aligned Four Packed Single-FP Non Temporal
SMPDefsFlags[NN_movntq] = false;              // Move 64 Bits Non Temporal   
SMPDefsFlags[NN_prefetcht0] = false;          // Prefetch to all cache levels
SMPDefsFlags[NN_prefetcht1] = false;          // Prefetch to all cache levels
SMPDefsFlags[NN_prefetcht2] = false;          // Prefetch to L2 cache
SMPDefsFlags[NN_prefetchnta] = false;         // Prefetch to L1 cache
SMPDefsFlags[NN_sfence] = false;              // Store Fence

// Pentium III Pseudo instructions

SMPDefsFlags[NN_cmpeqps] = false;             // Packed Single-FP Compare EQ
SMPDefsFlags[NN_cmpltps] = false;             // Packed Single-FP Compare LT
SMPDefsFlags[NN_cmpleps] = false;             // Packed Single-FP Compare LE
SMPDefsFlags[NN_cmpunordps] = false;          // Packed Single-FP Compare UNORD
SMPDefsFlags[NN_cmpneqps] = false;            // Packed Single-FP Compare NOT EQ
SMPDefsFlags[NN_cmpnltps] = false;            // Packed Single-FP Compare NOT LT
SMPDefsFlags[NN_cmpnleps] = false;            // Packed Single-FP Compare NOT LE
SMPDefsFlags[NN_cmpordps] = false;            // Packed Single-FP Compare ORDERED
SMPDefsFlags[NN_cmpeqss] = false;             // Scalar Single-FP Compare EQ
SMPDefsFlags[NN_cmpltss] = false;             // Scalar Single-FP Compare LT
SMPDefsFlags[NN_cmpless] = false;             // Scalar Single-FP Compare LE
SMPDefsFlags[NN_cmpunordss] = false;          // Scalar Single-FP Compare UNORD
SMPDefsFlags[NN_cmpneqss] = false;            // Scalar Single-FP Compare NOT EQ
SMPDefsFlags[NN_cmpnltss] = false;            // Scalar Single-FP Compare NOT LT
SMPDefsFlags[NN_cmpnless] = false;            // Scalar Single-FP Compare NOT LE
SMPDefsFlags[NN_cmpordss] = false;            // Scalar Single-FP Compare ORDERED

// AMD K7 instructions

// Revisit AMD if we port to it.
SMPDefsFlags[NN_pf2iw] = false;               // Packed Floating-Point to Integer with Sign Extend
SMPDefsFlags[NN_pfnacc] = false;              // Packed Floating-Point Negative Accumulate
SMPDefsFlags[NN_pfpnacc] = false;             // Packed Floating-Point Mixed Positive-Negative Accumulate
SMPDefsFlags[NN_pi2fw] = false;               // Packed 16-bit Integer to Floating-Point
SMPDefsFlags[NN_pswapd] = false;              // Packed Swap Double Word

// Undocumented FP instructions (thanks to norbert.juffa@adm.com)

SMPDefsFlags[NN_fstp1] = false;               // Alias of Store Real and Pop
SMPDefsFlags[NN_fxch4] = false;               // Alias of Exchange Registers
SMPDefsFlags[NN_ffreep] = false;              // Free Register and Pop
SMPDefsFlags[NN_fxch7] = false;               // Alias of Exchange Registers
SMPDefsFlags[NN_fstp8] = false;               // Alias of Store Real and Pop
SMPDefsFlags[NN_fstp9] = false;               // Alias of Store Real and Pop

// Pentium 4 instructions

SMPDefsFlags[NN_addpd] = false;               // Add Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_addsd] = false;               // Add Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_andnpd] = false;              // Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_andpd] = false;               // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_clflush] = false;             // Flush Cache Line
SMPDefsFlags[NN_cmppd] = false;               // Compare Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_cmpsd] = false;               // Compare Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_cvtdq2pd] = false;            // Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_cvtdq2ps] = false;            // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_cvtpd2dq] = false;            // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_cvtpd2pi] = false;            // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_cvtpd2ps] = false;            // Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_cvtpi2pd] = false;            // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_cvtps2dq] = false;            // Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_cvtps2pd] = false;            // Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_cvtsd2si] = false;            // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
SMPDefsFlags[NN_cvtsd2ss] = false;            // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
SMPDefsFlags[NN_cvtsi2sd] = false;            // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_cvtss2sd] = false;            // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_cvttpd2dq] = false;           // Convert With Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_cvttpd2pi] = false;           // Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_cvttps2dq] = false;           // Convert With Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_cvttsd2si] = false;           // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
SMPDefsFlags[NN_divpd] = false;               // Divide Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_divsd] = false;               // Divide Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_lfence] = false;              // Load Fence
SMPDefsFlags[NN_maskmovdqu] = false;          // Store Selected Bytes of Double Quadword 
SMPDefsFlags[NN_maxpd] = false;               // Return Maximum Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_maxsd] = false;               // Return Maximum Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_mfence] = false;              // Memory Fence
SMPDefsFlags[NN_minpd] = false;               // Return Minimum Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_minsd] = false;               // Return Minimum Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_movapd] = false;              // Move Aligned Packed Double-Precision Floating-Point Values 
SMPDefsFlags[NN_movdq2q] = false;             // Move Quadword from XMM to MMX Register
SMPDefsFlags[NN_movdqa] = false;              // Move Aligned Double Quadword  
SMPDefsFlags[NN_movdqu] = false;              // Move Unaligned Double Quadword  
SMPDefsFlags[NN_movhpd] = false;              // Move High Packed Double-Precision Floating-Point Values 
SMPDefsFlags[NN_movlpd] = false;              // Move Low Packed Double-Precision Floating-Point Values 
SMPDefsFlags[NN_movmskpd] = false;            // Extract Packed Double-Precision Floating-Point Sign Mask
SMPDefsFlags[NN_movntdq] = false;             // Store Double Quadword Using Non-Temporal Hint
SMPDefsFlags[NN_movnti] = false;              // Store Doubleword Using Non-Temporal Hint
SMPDefsFlags[NN_movntpd] = false;             // Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
SMPDefsFlags[NN_movq2dq] = false;             // Move Quadword from MMX to XMM Register
SMPDefsFlags[NN_movsd] = false;               // Move Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_movupd] = false;              // Move Unaligned Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_mulpd] = false;               // Multiply Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_mulsd] = false;               // Multiply Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_orpd] = false;                // Bitwise Logical OR of Double-Precision Floating-Point Values
SMPDefsFlags[NN_paddq] = false;               // Add Packed Quadword Integers
SMPDefsFlags[NN_pause] = false;               // Spin Loop Hint
SMPDefsFlags[NN_pmuludq] = false;             // Multiply Packed Unsigned Doubleword Integers
SMPDefsFlags[NN_pshufd] = false;              // Shuffle Packed Doublewords
SMPDefsFlags[NN_pshufhw] = false;             // Shuffle Packed High Words
SMPDefsFlags[NN_pshuflw] = false;             // Shuffle Packed Low Words
SMPDefsFlags[NN_pslldq] = false;              // Shift Double Quadword Left Logical
SMPDefsFlags[NN_psrldq] = false;              // Shift Double Quadword Right Logical
SMPDefsFlags[NN_psubq] = false;               // Subtract Packed Quadword Integers
SMPDefsFlags[NN_punpckhqdq] = false;          // Unpack High Data
SMPDefsFlags[NN_punpcklqdq] = false;          // Unpack Low Data
SMPDefsFlags[NN_shufpd] = false;              // Shuffle Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_sqrtpd] = false;              // Compute Square Roots of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_sqrtsd] = false;              // Compute Square Rootof Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_subpd] = false;               // Subtract Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_subsd] = false;               // Subtract Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_unpckhpd] = false;            // Unpack and Interleave High Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_unpcklpd] = false;            // Unpack and Interleave Low Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_xorpd] = false;               // Bitwise Logical OR of Double-Precision Floating-Point Values


// AMD syscall/sysret instructions  NOTE: not AMD, found in Intel manual


// AMD64 instructions    NOTE: not AMD, found in Intel manual

SMPDefsFlags[NN_swapgs] = false;              // Exchange GS base with KernelGSBase MSR

// New Pentium instructions (SSE3)

SMPDefsFlags[NN_movddup] = false;             // Move One Double-FP and Duplicate
SMPDefsFlags[NN_movshdup] = false;            // Move Packed Single-FP High and Duplicate
SMPDefsFlags[NN_movsldup] = false;            // Move Packed Single-FP Low and Duplicate

// Missing AMD64 instructions  NOTE: also found in Intel manual

SMPDefsFlags[NN_movsxd] = false;              // Move with Sign-Extend Doubleword

// SSE3 instructions

SMPDefsFlags[NN_addsubpd] = false;            // Add /Sub packed DP FP numbers
SMPDefsFlags[NN_addsubps] = false;            // Add /Sub packed SP FP numbers
SMPDefsFlags[NN_haddpd] = false;              // Add horizontally packed DP FP numbers
SMPDefsFlags[NN_haddps] = false;              // Add horizontally packed SP FP numbers
SMPDefsFlags[NN_hsubpd] = false;              // Sub horizontally packed DP FP numbers
SMPDefsFlags[NN_hsubps] = false;              // Sub horizontally packed SP FP numbers
SMPDefsFlags[NN_monitor] = false;             // Set up a linear address range to be monitored by hardware
SMPDefsFlags[NN_mwait] = false;               // Wait until write-back store performed within the range specified by the MONITOR instruction
SMPDefsFlags[NN_fisttp] = false;              // Store ST in intXX (chop) and pop
SMPDefsFlags[NN_lddqu] = false;               // Load unaligned integer 128-bit

// SSSE3 instructions

SMPDefsFlags[NN_psignb] = false;              // Packed SIGN Byte
SMPDefsFlags[NN_psignw] = false;              // Packed SIGN Word
SMPDefsFlags[NN_psignd] = false;              // Packed SIGN Doubleword
SMPDefsFlags[NN_pshufb] = false;              // Packed Shuffle Bytes
SMPDefsFlags[NN_pmulhrsw] = false;            // Packed Multiply High with Round and Scale
SMPDefsFlags[NN_pmaddubsw] = false;           // Multiply and Add Packed Signed and Unsigned Bytes
SMPDefsFlags[NN_phsubsw] = false;             // Packed Horizontal Subtract and Saturate
SMPDefsFlags[NN_phaddsw] = false;             // Packed Horizontal Add and Saturate
SMPDefsFlags[NN_phaddw] = false;              // Packed Horizontal Add Word
SMPDefsFlags[NN_phaddd] = false;              // Packed Horizontal Add Doubleword
SMPDefsFlags[NN_phsubw] = false;              // Packed Horizontal Subtract Word
SMPDefsFlags[NN_phsubd] = false;              // Packed Horizontal Subtract Doubleword
SMPDefsFlags[NN_palignr] = false;             // Packed Align Right
SMPDefsFlags[NN_pabsb] = false;               // Packed Absolute Value Byte
SMPDefsFlags[NN_pabsw] = false;               // Packed Absolute Value Word
SMPDefsFlags[NN_pabsd] = false;               // Packed Absolute Value Doubleword

// VMX instructions

#if 599 < IDA_SDK_VERSION

SMPDefsFlags[NN_ud2] = false;                 // Undefined Instruction

// Added with x86-64

SMPDefsFlags[NN_rdtscp] = false;              // Read Time-Stamp Counter and Processor ID

// Geode LX 3DNow! extensions

SMPDefsFlags[NN_pfrcpv] = false;              // Reciprocal Approximation for a Pair of 32-bit Floats
SMPDefsFlags[NN_pfrsqrtv] = false;            // Reciprocal Square Root Approximation for a Pair of 32-bit Floats

// SSE2 pseudoinstructions

SMPDefsFlags[NN_cmpeqpd] = false;             // Packed Double-FP Compare EQ
SMPDefsFlags[NN_cmpltpd] = false;             // Packed Double-FP Compare LT
SMPDefsFlags[NN_cmplepd] = false;             // Packed Double-FP Compare LE
SMPDefsFlags[NN_cmpunordpd] = false;          // Packed Double-FP Compare UNORD
SMPDefsFlags[NN_cmpneqpd] = false;            // Packed Double-FP Compare NOT EQ
SMPDefsFlags[NN_cmpnltpd] = false;            // Packed Double-FP Compare NOT LT
SMPDefsFlags[NN_cmpnlepd] = false;            // Packed Double-FP Compare NOT LE
SMPDefsFlags[NN_cmpordpd] = false;            // Packed Double-FP Compare ORDERED
SMPDefsFlags[NN_cmpeqsd] = false;             // Scalar Double-FP Compare EQ
SMPDefsFlags[NN_cmpltsd] = false;             // Scalar Double-FP Compare LT
SMPDefsFlags[NN_cmplesd] = false;             // Scalar Double-FP Compare LE
SMPDefsFlags[NN_cmpunordsd] = false;          // Scalar Double-FP Compare UNORD
SMPDefsFlags[NN_cmpneqsd] = false;            // Scalar Double-FP Compare NOT EQ
SMPDefsFlags[NN_cmpnltsd] = false;            // Scalar Double-FP Compare NOT LT
SMPDefsFlags[NN_cmpnlesd] = false;            // Scalar Double-FP Compare NOT LE
SMPDefsFlags[NN_cmpordsd] = false;            // Scalar Double-FP Compare ORDERED

// SSSE4.1 instructions

SMPDefsFlags[NN_blendpd] = false;              // Blend Packed Double Precision Floating-Point Values
SMPDefsFlags[NN_blendps] = false;              // Blend Packed Single Precision Floating-Point Values
SMPDefsFlags[NN_blendvpd] = false;             // Variable Blend Packed Double Precision Floating-Point Values
SMPDefsFlags[NN_blendvps] = false;             // Variable Blend Packed Single Precision Floating-Point Values
SMPDefsFlags[NN_dppd] = false;                 // Dot Product of Packed Double Precision Floating-Point Values
SMPDefsFlags[NN_dpps] = false;                 // Dot Product of Packed Single Precision Floating-Point Values
SMPDefsFlags[NN_extractps] = 2;            // Extract Packed Single Precision Floating-Point Value
SMPDefsFlags[NN_insertps] = false;             // Insert Packed Single Precision Floating-Point Value
SMPDefsFlags[NN_movntdqa] = false;             // Load Double Quadword Non-Temporal Aligned Hint
SMPDefsFlags[NN_mpsadbw] = false;              // Compute Multiple Packed Sums of Absolute Difference
SMPDefsFlags[NN_packusdw] = false;             // Pack with Unsigned Saturation
SMPDefsFlags[NN_pblendvb] = false;             // Variable Blend Packed Bytes
SMPDefsFlags[NN_pblendw] = false;              // Blend Packed Words
SMPDefsFlags[NN_pcmpeqq] = false;              // Compare Packed Qword Data for Equal
SMPDefsFlags[NN_pextrb] = false;               // Extract Byte
SMPDefsFlags[NN_pextrd] = false;               // Extract Dword
SMPDefsFlags[NN_pextrq] = false;               // Extract Qword
SMPDefsFlags[NN_phminposuw] = false;           // Packed Horizontal Word Minimum
SMPDefsFlags[NN_pinsrb] = false;               // Insert Byte
SMPDefsFlags[NN_pinsrd] = false;               // Insert Dword
SMPDefsFlags[NN_pinsrq] = false;               // Insert Qword
SMPDefsFlags[NN_pmaxsb] = false;               // Maximum of Packed Signed Byte Integers
SMPDefsFlags[NN_pmaxsd] = false;               // Maximum of Packed Signed Dword Integers
SMPDefsFlags[NN_pmaxud] = false;               // Maximum of Packed Unsigned Dword Integers
SMPDefsFlags[NN_pmaxuw] = false;               // Maximum of Packed Word Integers
SMPDefsFlags[NN_pminsb] = false;               // Minimum of Packed Signed Byte Integers
SMPDefsFlags[NN_pminsd] = false;               // Minimum of Packed Signed Dword Integers
SMPDefsFlags[NN_pminud] = false;               // Minimum of Packed Unsigned Dword Integers
SMPDefsFlags[NN_pminuw] = false;               // Minimum of Packed Word Integers
SMPDefsFlags[NN_pmovsxbw] = false;             // Packed Move with Sign Extend
SMPDefsFlags[NN_pmovsxbd] = false;             // Packed Move with Sign Extend
SMPDefsFlags[NN_pmovsxbq] = false;             // Packed Move with Sign Extend
SMPDefsFlags[NN_pmovsxwd] = false;             // Packed Move with Sign Extend
SMPDefsFlags[NN_pmovsxwq] = false;             // Packed Move with Sign Extend
SMPDefsFlags[NN_pmovsxdq] = false;             // Packed Move with Sign Extend
SMPDefsFlags[NN_pmovzxbw] = false;             // Packed Move with Zero Extend
SMPDefsFlags[NN_pmovzxbd] = false;             // Packed Move with Zero Extend
SMPDefsFlags[NN_pmovzxbq] = false;             // Packed Move with Zero Extend
SMPDefsFlags[NN_pmovzxwd] = false;             // Packed Move with Zero Extend
SMPDefsFlags[NN_pmovzxwq] = false;             // Packed Move with Zero Extend
SMPDefsFlags[NN_pmovzxdq] = false;             // Packed Move with Zero Extend
SMPDefsFlags[NN_pmuldq] = false;               // Multiply Packed Signed Dword Integers
SMPDefsFlags[NN_pmulld] = false;               // Multiply Packed Signed Dword Integers and Store Low Result
SMPDefsFlags[NN_roundpd] = false;              // Round Packed Double Precision Floating-Point Values
SMPDefsFlags[NN_roundps] = false;              // Round Packed Single Precision Floating-Point Values
SMPDefsFlags[NN_roundsd] = false;              // Round Scalar Double Precision Floating-Point Values
SMPDefsFlags[NN_roundss] = false;              // Round Scalar Single Precision Floating-Point Values

// SSSE4.2 instructions
SMPDefsFlags[NN_crc32] = false;                // Accumulate CRC32 Value
SMPDefsFlags[NN_pcmpgtq] = false;              // Compare Packed Data for Greater Than

// AMD SSE4a instructions

SMPDefsFlags[NN_extrq] = false;                // Extract Field From Register
SMPDefsFlags[NN_insertq] = false;              // Insert Field
SMPDefsFlags[NN_movntsd] = false;              // Move Non-Temporal Scalar Double-Precision Floating-Point
SMPDefsFlags[NN_movntss] = false;              // Move Non-Temporal Scalar Single-Precision Floating-Point

// xsave/xrstor instructions

SMPDefsFlags[NN_xgetbv] = false;               // Get Value of Extended Control Register
SMPDefsFlags[NN_xrstor] = false;               // Restore Processor Extended States
SMPDefsFlags[NN_xsave] = false;                // Save Processor Extended States
SMPDefsFlags[NN_xsetbv] = false;               // Set Value of Extended Control Register

// Intel Safer Mode Extensions (SMX)

// AMD-V Virtualization ISA Extension

SMPDefsFlags[NN_invlpga] = false;              // Invalidate TLB Entry in a Specified ASID
SMPDefsFlags[NN_skinit] = false;               // Secure Init and Jump with Attestation
SMPDefsFlags[NN_vmexit] = false;               // Stop Executing Guest, Begin Executing Host
SMPDefsFlags[NN_vmload] = false;               // Load State from VMCB
SMPDefsFlags[NN_vmmcall] = false;              // Call VMM
SMPDefsFlags[NN_vmrun] = false;                // Run Virtual Machine
SMPDefsFlags[NN_vmsave] = false;               // Save State to VMCB

// VMX+ instructions

SMPDefsFlags[NN_invept] = false;               // Invalidate Translations Derived from EPT
SMPDefsFlags[NN_invvpid] = false;              // Invalidate Translations Based on VPID

// Intel Atom instructions

SMPDefsFlags[NN_movbe] = false;                // Move Data After Swapping Bytes

// Intel AES instructions

SMPDefsFlags[NN_aesenc] = false;                // Perform One Round of an AES Encryption Flow
SMPDefsFlags[NN_aesenclast] = false;            // Perform the Last Round of an AES Encryption Flow
SMPDefsFlags[NN_aesdec] = false;                // Perform One Round of an AES Decryption Flow
SMPDefsFlags[NN_aesdeclast] = false;            // Perform the Last Round of an AES Decryption Flow
SMPDefsFlags[NN_aesimc] = false;                // Perform the AES InvMixColumn Transformation
SMPDefsFlags[NN_aeskeygenassist] = false;       // AES Round Key Generation Assist

// Carryless multiplication

SMPDefsFlags[NN_pclmulqdq] = false;            // Carry-Less Multiplication Quadword

#endif // 599 < IDA_SDK_VERSION

SMPDefsFlags[NN_last] = false;

  return;

} // end InitSMPDefsFlags()

// Initialize the SMPUsesFlags[] array to define how we emit
//   optimizing annotations.
void InitSMPUsesFlags(void) {
	// Default value is false. Few instructions use the flags.
	(void) memset(SMPUsesFlags, false, sizeof(SMPUsesFlags));

SMPUsesFlags[NN_null] = true;            // Unknown Operation
SMPUsesFlags[NN_aaa] = true;                 // ASCII adjust after addition
SMPUsesFlags[NN_aas] = true;				 // ASCII adjust after subtraction
SMPUsesFlags[NN_adc] = true;                 // Add with Carry
SMPUsesFlags[NN_cmps] = true;                // Compare Strings (uses DF direction flag)
SMPUsesFlags[NN_daa] = true;                 // Decimal Adjust AL after Addition
SMPUsesFlags[NN_das] = true;                 // Decimal Adjust AL after Subtraction
SMPUsesFlags[NN_ins] = true;                 // Input Byte(s) from Port to String        
SMPUsesFlags[NN_into] = true;                // Call to Interrupt Procedure if Overflow Flag = 1
SMPUsesFlags[NN_ja] = true;                  // Jump if Above (CF=0 & ZF=0)
SMPUsesFlags[NN_jae] = true;                 // Jump if Above or Equal (CF=0)
SMPUsesFlags[NN_jb] = true;                  // Jump if Below (CF=1)
SMPUsesFlags[NN_jbe] = true;                 // Jump if Below or Equal (CF=1 | ZF=1)
SMPUsesFlags[NN_jc] = true;                  // Jump if Carry (CF=1)
SMPUsesFlags[NN_jcxz] = true;                // Jump if CX is 0
SMPUsesFlags[NN_jecxz] = true;               // Jump if ECX is 0
SMPUsesFlags[NN_jrcxz] = true;               // Jump if RCX is 0
SMPUsesFlags[NN_je] = true;                  // Jump if Equal (ZF=1)
SMPUsesFlags[NN_jg] = true;                  // Jump if Greater (ZF=0 & SF=OF)
SMPUsesFlags[NN_jge] = true;                 // Jump if Greater or Equal (SF=OF)
SMPUsesFlags[NN_jl] = true;                  // Jump if Less (SF!=OF)
SMPUsesFlags[NN_jle] = true;                 // Jump if Less or Equal (ZF=1 | SF!=OF)
SMPUsesFlags[NN_jna] = true;                 // Jump if Not Above (CF=1 | ZF=1)
SMPUsesFlags[NN_jnae] = true;                // Jump if Not Above or Equal (CF=1)
SMPUsesFlags[NN_jnb] = true;                 // Jump if Not Below (CF=0)
SMPUsesFlags[NN_jnbe] = true;                // Jump if Not Below or Equal (CF=0 & ZF=0)
SMPUsesFlags[NN_jnc] = true;                 // Jump if Not Carry (CF=0)
SMPUsesFlags[NN_jne] = true;                 // Jump if Not Equal (ZF=0)
SMPUsesFlags[NN_jng] = true;                 // Jump if Not Greater (ZF=1 | SF!=OF)
SMPUsesFlags[NN_jnge] = true;                // Jump if Not Greater or Equal (ZF=1)
SMPUsesFlags[NN_jnl] = true;                 // Jump if Not Less (SF=OF)
SMPUsesFlags[NN_jnle] = true;                // Jump if Not Less or Equal (ZF=0 & SF=OF)
SMPUsesFlags[NN_jno] = true;                 // Jump if Not Overflow (OF=0)
SMPUsesFlags[NN_jnp] = true;                 // Jump if Not Parity (PF=0)
SMPUsesFlags[NN_jns] = true;                 // Jump if Not Sign (SF=0)
SMPUsesFlags[NN_jnz] = true;                 // Jump if Not Zero (ZF=0)
SMPUsesFlags[NN_jo] = true;                  // Jump if Overflow (OF=1)
SMPUsesFlags[NN_jp] = true;                  // Jump if Parity (PF=1)
SMPUsesFlags[NN_jpe] = true;                 // Jump if Parity Even (PF=1)
SMPUsesFlags[NN_jpo] = true;                 // Jump if Parity Odd  (PF=0)
SMPUsesFlags[NN_js] = true;                  // Jump if Sign (SF=1)
SMPUsesFlags[NN_jz] = true;                  // Jump if Zero (ZF=1)
SMPUsesFlags[NN_lahf] = true;                // Load Flags into AH Register
SMPUsesFlags[NN_lods] = true;                // Load String
SMPUsesFlags[NN_loopwe] = true;              // Loop while CX != 0 and ZF=1
SMPUsesFlags[NN_loope] = true;               // Loop while rCX != 0 and ZF=1
SMPUsesFlags[NN_loopde] = true;              // Loop while ECX != 0 and ZF=1
SMPUsesFlags[NN_loopqe] = true;              // Loop while RCX != 0 and ZF=1
SMPUsesFlags[NN_loopwne] = true;             // Loop while CX != 0 and ZF=0
SMPUsesFlags[NN_loopne] = true;              // Loop while rCX != 0 and ZF=0
SMPUsesFlags[NN_loopdne] = true;             // Loop while ECX != 0 and ZF=0
SMPUsesFlags[NN_loopqne] = true;             // Loop while RCX != 0 and ZF=0
SMPUsesFlags[NN_movs] = true;  		         // Move String (uses flags if REP prefix)
SMPUsesFlags[NN_outs] = true;                // Output Byte(s) to Port
SMPUsesFlags[NN_pushfw] = true;              // Push Flags Register onto the Stack
SMPUsesFlags[NN_pushf] = true;               // Push Flags Register onto the Stack
SMPUsesFlags[NN_pushfd] = true;              // Push Flags Register onto the Stack (use32)
SMPUsesFlags[NN_pushfq] = true;              // Push Flags Register onto the Stack (use64)
SMPUsesFlags[NN_rcl] = true;                 // Rotate Through Carry Left
SMPUsesFlags[NN_rcr] = true;                 // Rotate Through Carry Right
SMPUsesFlags[NN_repe] = true;                // Repeat String Operation while ZF=1
SMPUsesFlags[NN_repne] = true;               // Repeat String Operation while ZF=0
SMPUsesFlags[NN_sbb] = true;                 // Integer Subtraction with Borrow
SMPUsesFlags[NN_scas] = true;                // Compare String (uses DF direction flag)
SMPUsesFlags[NN_seta] = true;                // Set Byte if Above (CF=0 & ZF=0)
SMPUsesFlags[NN_setae] = true;               // Set Byte if Above or Equal (CF=0)
SMPUsesFlags[NN_setb] = true;                // Set Byte if Below (CF=1)
SMPUsesFlags[NN_setbe] = true;               // Set Byte if Below or Equal (CF=1 | ZF=1)
SMPUsesFlags[NN_setc] = true;                // Set Byte if Carry (CF=1)
SMPUsesFlags[NN_sete] = true;                // Set Byte if Equal (ZF=1)
SMPUsesFlags[NN_setg] = true;                // Set Byte if Greater (ZF=0 & SF=OF)
SMPUsesFlags[NN_setge] = true;               // Set Byte if Greater or Equal (SF=OF)
SMPUsesFlags[NN_setl] = true;                // Set Byte if Less (SF!=OF)
SMPUsesFlags[NN_setle] = true;               // Set Byte if Less or Equal (ZF=1 | SF!=OF)
SMPUsesFlags[NN_setna] = true;               // Set Byte if Not Above (CF=1 | ZF=1)
SMPUsesFlags[NN_setnae] = true;              // Set Byte if Not Above or Equal (CF=1)
SMPUsesFlags[NN_setnb] = true;               // Set Byte if Not Below (CF=0)
SMPUsesFlags[NN_setnbe] = true;              // Set Byte if Not Below or Equal (CF=0 & ZF=0)
SMPUsesFlags[NN_setnc] = true;               // Set Byte if Not Carry (CF=0)
SMPUsesFlags[NN_setne] = true;               // Set Byte if Not Equal (ZF=0)
SMPUsesFlags[NN_setng] = true;               // Set Byte if Not Greater (ZF=1 | SF!=OF)
SMPUsesFlags[NN_setnge] = true;              // Set Byte if Not Greater or Equal (ZF=1)
SMPUsesFlags[NN_setnl] = true;               // Set Byte if Not Less (SF=OF)
SMPUsesFlags[NN_setnle] = true;              // Set Byte if Not Less or Equal (ZF=0 & SF=OF)
SMPUsesFlags[NN_setno] = true;               // Set Byte if Not Overflow (OF=0)
SMPUsesFlags[NN_setnp] = true;               // Set Byte if Not Parity (PF=0)
SMPUsesFlags[NN_setns] = true;               // Set Byte if Not Sign (SF=0)
SMPUsesFlags[NN_setnz] = true;               // Set Byte if Not Zero (ZF=0)
SMPUsesFlags[NN_seto] = true;                // Set Byte if Overflow (OF=1)
SMPUsesFlags[NN_setp] = true;                // Set Byte if Parity (PF=1)
SMPUsesFlags[NN_setpe] = true;               // Set Byte if Parity Even (PF=1)
SMPUsesFlags[NN_setpo] = true;               // Set Byte if Parity Odd  (PF=0)
SMPUsesFlags[NN_sets] = true;                // Set Byte if Sign (SF=1)
SMPUsesFlags[NN_setz] = true;                // Set Byte if Zero (ZF=1)
SMPUsesFlags[NN_stos] = true;                // Store String

//
//      486 instructions
//

//
//      Pentium instructions
//

#if 0
SMPUsesFlags[NN_cpuid] = true;               // Get CPU ID
SMPUsesFlags[NN_cmpxchg8b] = true;           // Compare and Exchange Eight Bytes
#endif

//
//      Pentium Pro instructions
//

SMPUsesFlags[NN_cmova] = true;               // Move if Above (CF=0 & ZF=0)
SMPUsesFlags[NN_cmovb] = true;               // Move if Below (CF=1)
SMPUsesFlags[NN_cmovbe] = true;              // Move if Below or Equal (CF=1 | ZF=1)
SMPUsesFlags[NN_cmovg] = true;               // Move if Greater (ZF=0 & SF=OF)
SMPUsesFlags[NN_cmovge] = true;              // Move if Greater or Equal (SF=OF)
SMPUsesFlags[NN_cmovl] = true;               // Move if Less (SF!=OF)
SMPUsesFlags[NN_cmovle] = true;              // Move if Less or Equal (ZF=1 | SF!=OF)
SMPUsesFlags[NN_cmovnb] = true;              // Move if Not Below (CF=0)
SMPUsesFlags[NN_cmovno] = true;              // Move if Not Overflow (OF=0)
SMPUsesFlags[NN_cmovnp] = true;              // Move if Not Parity (PF=0)
SMPUsesFlags[NN_cmovns] = true;              // Move if Not Sign (SF=0)
SMPUsesFlags[NN_cmovnz] = true;              // Move if Not Zero (ZF=0)
SMPUsesFlags[NN_cmovo] = true;               // Move if Overflow (OF=1)
SMPUsesFlags[NN_cmovp] = true;               // Move if Parity (PF=1)
SMPUsesFlags[NN_cmovs] = true;               // Move if Sign (SF=1)
SMPUsesFlags[NN_cmovz] = true;               // Move if Zero (ZF=1)
SMPUsesFlags[NN_fcmovb] = true;              // Floating Move if Below          
SMPUsesFlags[NN_fcmove] = true;              // Floating Move if Equal          
SMPUsesFlags[NN_fcmovbe] = true;             // Floating Move if Below or Equal 
SMPUsesFlags[NN_fcmovu] = true;              // Floating Move if Unordered      
SMPUsesFlags[NN_fcmovnb] = true;             // Floating Move if Not Below      
SMPUsesFlags[NN_fcmovne] = true;             // Floating Move if Not Equal      
SMPUsesFlags[NN_fcmovnbe] = true;            // Floating Move if Not Below or Equal
SMPUsesFlags[NN_fcmovnu] = true;             // Floating Move if Not Unordered     

//
//      FPP instructions
//


//
//      80387 instructions
//


//
//      Instructions added 28.02.96
//

SMPUsesFlags[NN_setalc] = true;              // Set AL to Carry Flag      

//
//      MMX instructions
//


//
//      Undocumented Deschutes processor instructions
//


//      Pentium II instructions


//      3DNow! instructions


//      Pentium III instructions


// Pentium III Pseudo instructions


// AMD K7 instructions

// Revisit AMD if we port to it.

// Undocumented FP instructions (thanks to norbert.juffa@adm.com)

// Pentium 4 instructions



// AMD syscall/sysret instructions  NOTE: not AMD, found in Intel manual

// AMD64 instructions    NOTE: not AMD, found in Intel manual


// New Pentium instructions (SSE3)


// Missing AMD64 instructions  NOTE: also found in Intel manual


// SSE3 instructions


// SSSE3 instructions


// VMX instructions

// Added with x86-64

// Geode LX 3DNow! extensions

// SSE2 pseudoinstructions

// SSSE4.1 instructions

// SSSE4.2 instructions

// AMD SSE4a instructions

// xsave/xrstor instructions

// Intel Safer Mode Extensions (SMX)

// AMD-V Virtualization ISA Extension

// VMX+ instructions

// Intel Atom instructions

// Intel AES instructions

// Carryless multiplication

SMPUsesFlags[NN_last] = false;

  return;

} // end InitSMPUsesFlags()


// Initialize the SMPTypeCategory[] array to define how we infer
//   numeric or pointer operand types for optimizing annotations.
void InitTypeCategory(void) {
	// Default category is 0, no type inference without knowing context.
	(void) memset(SMPTypeCategory, 0, sizeof(SMPTypeCategory));
	// Category 1 instructions will need no mmStrata instrumentation
	//  and are irrelevant to our type system, so we do not attempt
	//  to make type inferences. Many of these operate on numeric
	//  operands such as floating point or MMX/SSE registers. mmStrata
	//  assumes that such registers are always numeric, so we do not
	//  need annotations informing mmStrata that FP/MMX/SSE regs are numeric.
	// Category 2 instructions always have a result type of 'n' (number).
	// Category 3 instructions have a result type of 'n' (number)
	//  whenever the second source operand is an operand of type 'n'.
	//  NOTE: MOV is the only current example, and this will take some thought if 
    //   other examples arise.
	// Category 4 instructions have a result type identical to the 1st source operand type.
	//  NOTE: This is currently set for single-operand instructions such as
	//   INC, DEC. As a result, these are treated pretty much as if
	//   they were category 1 instructions, as there is no metadata update,
	//   even if the operand is a memory operand.
	//   If new instructions are added to this category that are not single
	//   operand and do require some updating, the category should be split.
	// Category 5 instructions have a result type identical to the 1st source operand
	//  type whenever the 2nd source operand is an operand of type 'n' & vice versa.
	//  Examples are add, sub, adc, and sbb. There are subtle exceptions
	//  handled in the SMPInstr::EmitTypeAnnotations() method.
	// Category 6 instructions always have a result type of 'p' (pointer).
	// Category 7 instructions are category 2 instructions with two destinations,
	//  such as multiply and divide instructions that affect EDX:EAX. There are
	//  forms of these instructions that only have one destination, so they have
	//  to be distinguished via the operand info.
    // Category 8 instructions implicitly write a numeric value to EDX:EAX, but
    //  EDX and EAX are not listed as operands. RDTSC, RDPMC, RDMSR, and other
    //  instructions that copy machine registers into EDX:EAX are category 8.
	//  Some instructions in category 8 also write to ECX.
    // Category 9 instructions are floating point instructions that either
    //  have a memory destination (treat as category 13) or a FP reg destination
    //  (treat as category 1, as FP regs are always 'n' and ignored in our system).
	// Category 10 instructions have 'n' results if the sources are all 'n';
	//  we cannot infer the type of the result if the sources are of mixed types.
	//  Bitwise OR and AND and LEA (load effective address) are examples.
	// Category 11 instructions need to have their types and locations on the stack
	//  frame tracked, e.g. push and pop instructions. No direct type inference.
	// Category 12 instructions are similar to category 10, except that we do not
	//  output 'n' annotations when all sources are 'n'; rather, the instruction can
	//  be simply ignored (not instrumented by mmStrata) in that case. Conditional
	//  exchange instructions are examples; we do or do not
	//  move a numeric value into a register that already has numeric metadata.
	// Category 13 instructions imply that their memory destination is 'n'.
	// Category 14 instructions imply that their reg or memory source operand is 'n';
	//  if source is not memory, they are category 1 (inferences, but no instrumentation).
	//  There should never be a memory destination (usual destination is fpreg or flags).
	// Category 15 instructions always have 'n' source AND destination operands;
	//  if addressed using indirect or indexed addressing, they are a subset of category 0
	//  (must be instrumented by mmStrata to keep index in bounds). Memory destinations
	//  are common in this category.

	// NOTE: The Memory Monitor SDT needs just three categories, corresponding
	//  to categories 0, 1, and all others. For all categories > 1, the
	//  annotation should tell the SDT exactly how to update its metadata.
	//  For example, a division instruction will write type 'n' (NUM) as
	//  the metadata for result registers EDX:EAX. So, the annotation should
	//  list 'n', EDX, EAX, and a terminator of ZZ. CWD (convert word to
	//  doubleword) should have a list of n EAX ZZ.

SMPTypeCategory[NN_null] = 0;            // Unknown Operation
SMPTypeCategory[NN_aaa] = 2;                 // ASCII Adjust after Addition
SMPTypeCategory[NN_aad] = 2;                 // ASCII Adjust AX before Division
SMPTypeCategory[NN_aam] = 2;                 // ASCII Adjust AX after Multiply
SMPTypeCategory[NN_aas] = 2;                 // ASCII Adjust AL after Subtraction
SMPTypeCategory[NN_adc] = 5;                 // Add with Carry
SMPTypeCategory[NN_add] = 5;                 // Add
SMPTypeCategory[NN_and] = 10;                // Logical AND
SMPTypeCategory[NN_arpl] = 1;                // Adjust RPL Field of Selector
SMPTypeCategory[NN_bound] = 1;               // Check Array Index Against Bounds
SMPTypeCategory[NN_bsf] = 2;                 // Bit Scan Forward
SMPTypeCategory[NN_bsr] = 2;                 // Bit Scan Reverse
SMPTypeCategory[NN_bt] = 10;                  // Bit Test
SMPTypeCategory[NN_btc] = 10;                 // Bit Test and Complement
SMPTypeCategory[NN_btr] = 10;                 // Bit Test and Reset
SMPTypeCategory[NN_bts] = 10;                 // Bit Test and Set
SMPTypeCategory[NN_call] = 1;                // Call Procedure
SMPTypeCategory[NN_callfi] = 1;              // Indirect Call Far Procedure
SMPTypeCategory[NN_callni] = 1;              // Indirect Call Near Procedure
SMPTypeCategory[NN_cbw] = 2;                 // AL -> AX (with sign)            ** No ops?
SMPTypeCategory[NN_cwde] = 2;                // AX -> EAX (with sign)           **
SMPTypeCategory[NN_cdqe] = 2;                // EAX -> RAX (with sign)          **
SMPTypeCategory[NN_clc] = 1;                 // Clear Carry Flag
SMPTypeCategory[NN_cld] = 1;                 // Clear Direction Flag
SMPTypeCategory[NN_cli] = 1;                 // Clear Interrupt Flag
SMPTypeCategory[NN_clts] = 1;                // Clear Task-Switched Flag in CR0
SMPTypeCategory[NN_cmc] = 1;                 // Complement Carry Flag
SMPTypeCategory[NN_cmp] = 1;                 // Compare Two Operands
SMPTypeCategory[NN_cmps] = 14;                // Compare Strings
SMPTypeCategory[NN_cwd] = 2;                 // AX -> DX:AX (with sign)
SMPTypeCategory[NN_cdq] = 2;                 // EAX -> EDX:EAX (with sign)
SMPTypeCategory[NN_cqo] = 2;                 // RAX -> RDX:RAX (with sign)
SMPTypeCategory[NN_daa] = 2;                 // Decimal Adjust AL after Addition
SMPTypeCategory[NN_das] = 2;                 // Decimal Adjust AL after Subtraction
SMPTypeCategory[NN_dec] = 4;                 // Decrement by 1
SMPTypeCategory[NN_div] = 7;                 // Unsigned Divide
SMPTypeCategory[NN_enterw] = 0;              // Make Stack Frame for Procedure Parameters  **
SMPTypeCategory[NN_enter] = 0;               // Make Stack Frame for Procedure Parameters  **
SMPTypeCategory[NN_enterd] = 0;              // Make Stack Frame for Procedure Parameters  **
SMPTypeCategory[NN_enterq] = 0;              // Make Stack Frame for Procedure Parameters  **
SMPTypeCategory[NN_hlt] = 0;                 // Halt
SMPTypeCategory[NN_idiv] = 7;                // Signed Divide
SMPTypeCategory[NN_imul] = 7;                // Signed Multiply
SMPTypeCategory[NN_in] = 0;                  // Input from Port                         **
SMPTypeCategory[NN_inc] = 4;                 // Increment by 1
SMPTypeCategory[NN_ins] = 2;                 // Input Byte(s) from Port to String       **
SMPTypeCategory[NN_int] = 0;                 // Call to Interrupt Procedure
SMPTypeCategory[NN_into] = 0;                // Call to Interrupt Procedure if Overflow Flag = 1