SMPDataFlowAnalysis.cpp

SMPUsesFlags[NN_setc] = true;                // Set Byte if Carry (CF=1)
SMPUsesFlags[NN_sete] = true;                // Set Byte if Equal (ZF=1)
SMPUsesFlags[NN_setg] = true;                // Set Byte if Greater (ZF=0 & SF=OF)
SMPUsesFlags[NN_setge] = true;               // Set Byte if Greater or Equal (SF=OF)
SMPUsesFlags[NN_setl] = true;                // Set Byte if Less (SF!=OF)
SMPUsesFlags[NN_setle] = true;               // Set Byte if Less or Equal (ZF=1 | SF!=OF)
SMPUsesFlags[NN_setna] = true;               // Set Byte if Not Above (CF=1 | ZF=1)
SMPUsesFlags[NN_setnae] = true;              // Set Byte if Not Above or Equal (CF=1)
SMPUsesFlags[NN_setnb] = true;               // Set Byte if Not Below (CF=0)
SMPUsesFlags[NN_setnbe] = true;              // Set Byte if Not Below or Equal (CF=0 & ZF=0)
SMPUsesFlags[NN_setnc] = true;               // Set Byte if Not Carry (CF=0)
SMPUsesFlags[NN_setne] = true;               // Set Byte if Not Equal (ZF=0)
SMPUsesFlags[NN_setng] = true;               // Set Byte if Not Greater (ZF=1 | SF!=OF)
SMPUsesFlags[NN_setnge] = true;              // Set Byte if Not Greater or Equal (ZF=1)
SMPUsesFlags[NN_setnl] = true;               // Set Byte if Not Less (SF=OF)
SMPUsesFlags[NN_setnle] = true;              // Set Byte if Not Less or Equal (ZF=0 & SF=OF)
SMPUsesFlags[NN_setno] = true;               // Set Byte if Not Overflow (OF=0)
SMPUsesFlags[NN_setnp] = true;               // Set Byte if Not Parity (PF=0)
SMPUsesFlags[NN_setns] = true;               // Set Byte if Not Sign (SF=0)
SMPUsesFlags[NN_setnz] = true;               // Set Byte if Not Zero (ZF=0)
SMPUsesFlags[NN_seto] = true;                // Set Byte if Overflow (OF=1)
SMPUsesFlags[NN_setp] = true;                // Set Byte if Parity (PF=1)
SMPUsesFlags[NN_setpe] = true;               // Set Byte if Parity Even (PF=1)
SMPUsesFlags[NN_setpo] = true;               // Set Byte if Parity Odd  (PF=0)
SMPUsesFlags[NN_sets] = true;                // Set Byte if Sign (SF=1)
SMPUsesFlags[NN_setz] = true;                // Set Byte if Zero (ZF=1)
SMPUsesFlags[NN_stos] = true;                // Store String

//
//      486 instructions
//

//
//      Pentium instructions
//

SMPUsesFlags[NN_cpuid] = true;               // Get CPU ID
#if 0
SMPUsesFlags[NN_cmpxchg8b] = true;           // Compare and Exchange Eight Bytes
#endif

//
//      Pentium Pro instructions
//

SMPUsesFlags[NN_cmova] = true;               // Move if Above (CF=0 & ZF=0)
SMPUsesFlags[NN_cmovb] = true;               // Move if Below (CF=1)
SMPUsesFlags[NN_cmovbe] = true;              // Move if Below or Equal (CF=1 | ZF=1)
SMPUsesFlags[NN_cmovg] = true;               // Move if Greater (ZF=0 & SF=OF)
SMPUsesFlags[NN_cmovge] = true;              // Move if Greater or Equal (SF=OF)
SMPUsesFlags[NN_cmovl] = true;               // Move if Less (SF!=OF)
SMPUsesFlags[NN_cmovle] = true;              // Move if Less or Equal (ZF=1 | SF!=OF)
SMPUsesFlags[NN_cmovnb] = true;              // Move if Not Below (CF=0)
SMPUsesFlags[NN_cmovno] = true;              // Move if Not Overflow (OF=0)
SMPUsesFlags[NN_cmovnp] = true;              // Move if Not Parity (PF=0)
SMPUsesFlags[NN_cmovns] = true;              // Move if Not Sign (SF=0)
SMPUsesFlags[NN_cmovnz] = true;              // Move if Not Zero (ZF=0)
SMPUsesFlags[NN_cmovo] = true;               // Move if Overflow (OF=1)
SMPUsesFlags[NN_cmovp] = true;               // Move if Parity (PF=1)
SMPUsesFlags[NN_cmovs] = true;               // Move if Sign (SF=1)
SMPUsesFlags[NN_cmovz] = true;               // Move if Zero (ZF=1)
SMPUsesFlags[NN_fcmovb] = true;              // Floating Move if Below          
SMPUsesFlags[NN_fcmove] = true;              // Floating Move if Equal          
SMPUsesFlags[NN_fcmovbe] = true;             // Floating Move if Below or Equal 
SMPUsesFlags[NN_fcmovu] = true;              // Floating Move if Unordered      
SMPUsesFlags[NN_fcmovnb] = true;             // Floating Move if Not Below      
SMPUsesFlags[NN_fcmovne] = true;             // Floating Move if Not Equal      
SMPUsesFlags[NN_fcmovnbe] = true;            // Floating Move if Not Below or Equal
SMPUsesFlags[NN_fcmovnu] = true;             // Floating Move if Not Unordered     

//
//      FPP instructions
//


//
//      80387 instructions
//


//
//      Instructions added 28.02.96
//

SMPUsesFlags[NN_setalc] = true;              // Set AL to Carry Flag      

//
//      MMX instructions
//


//
//      Undocumented Deschutes processor instructions
//


//      Pentium II instructions


//      3DNow! instructions


//      Pentium III instructions


// Pentium III Pseudo instructions


// AMD K7 instructions

// Revisit AMD if we port to it.

// Undocumented FP instructions (thanks to norbert.juffa@adm.com)

// Pentium 4 instructions



// AMD syscall/sysret instructions  NOTE: not AMD, found in Intel manual

// AMD64 instructions    NOTE: not AMD, found in Intel manual


// New Pentium instructions (SSE3)


// Missing AMD64 instructions  NOTE: also found in Intel manual


// SSE3 instructions


// SSSE3 instructions


// VMX instructions

// Added with x86-64

// Geode LX 3DNow! extensions

// SSE2 pseudoinstructions

// SSSE4.1 instructions

// SSSE4.2 instructions

// AMD SSE4a instructions

// xsave/xrstor instructions

// Intel Safer Mode Extensions (SMX)

// AMD-V Virtualization ISA Extension

// VMX+ instructions

// Intel Atom instructions

// Intel AES instructions

// Carryless multiplication

SMPUsesFlags[NN_last] = false;

  return;

} // end InitSMPUsesFlags()


// Initialize the SMPTypeCategory[] array to define how we infer
//   numeric or pointer operand types for optimizing annotations.
void InitTypeCategory(void) {
	// Default category is 0, no type inference without knowing context.
	(void) memset(SMPTypeCategory, 0, sizeof(SMPTypeCategory));
	// Category 1 instructions will need no mmStrata instrumentation
	//  and are irrelevant to our type system, so we do not attempt
	//  to make type inferences. Many of these operate on numeric
	//  operands such as floating point or MMX/SSE registers. mmStrata
	//  assumes that such registers are always numeric, so we do not
	//  need annotations informing mmStrata that FP/MMX/SSE regs are numeric.
	// Category 2 instructions always have a result type of 'n' (number).
	// Category 3 instructions have a result type of 'n' (number)
	//  whenever the second source operand is an operand of type 'n'.
	//  NOTE: MOV is the only current example, and this will take some thought if 
    //   other examples arise.
	// Category 4 instructions have a result type identical to the 1st source operand type.
	//  NOTE: This is currently set for single-operand instructions such as
	//   INC, DEC. As a result, these are treated pretty much as if
	//   they were category 1 instructions, as there is no metadata update,
	//   even if the operand is a memory operand.
	//   If new instructions are added to this category that are not single
	//   operand and do require some updating, the category should be split.
	// Category 5 instructions have a result type identical to the 1st source operand
	//  type whenever the 2nd source operand is an operand of type 'n' & vice versa.
	//  Examples are add, sub, adc, and sbb. There are subtle exceptions
	//  handled in the SMPInstr::EmitTypeAnnotations() method.
	// Category 6 instructions always have a result type of 'p' (pointer).
	// Category 7 instructions are category 2 instructions with two destinations,
	//  such as multiply and divide instructions that affect EDX:EAX. There are
	//  forms of these instructions that only have one destination, so they have
	//  to be distinguished via the operand info.
    // Category 8 instructions implicitly write a numeric value to EDX:EAX, but
    //  EDX and EAX are not listed as operands. RDTSC, RDPMC, RDMSR, and other
    //  instructions that copy machine registers into EDX:EAX are category 8.
	//  Some instructions in category 8 also write to ECX.
    // Category 9 instructions are floating point instructions that either
    //  have a memory destination (treat as category 13) or a FP reg destination
    //  (treat as category 1, as FP regs are always 'n' and ignored in our system).
	// Category 10 instructions have 'n' results if the sources are all 'n';
	//  we cannot infer the type of the result if the sources are of mixed types.
	//  Bitwise OR and AND and LEA (load effective address) are examples.
	// Category 11 instructions need to have their types and locations on the stack
	//  frame tracked, e.g. push and pop instructions. No direct type inference.
	// Category 12 instructions are similar to category 10, except that we do not
	//  output 'n' annotations when all sources are 'n'; rather, the instruction can
	//  be simply ignored (not instrumented by mmStrata) in that case. Conditional
	//  exchange instructions are examples; we do or do not
	//  move a numeric value into a register that already has numeric metadata.
	// Category 13 instructions imply that their memory destination is 'n'.
	// Category 14 instructions imply that their reg or memory source operand is 'n';
	//  if source is not memory, they are category 1 (inferences, but no instrumentation).
	//  There should never be a memory destination (usual destination is fpreg or flags).
	// Category 15 instructions always have 'n' source AND destination operands;
	//  if addressed using indirect or indexed addressing, they are a subset of category 0
	//  (must be instrumented by mmStrata to keep index in bounds). Memory destinations
	//  are common in this category.

	// NOTE: The Memory Monitor SDT needs just three categories, corresponding
	//  to categories 0, 1, and all others. For all categories > 1, the
	//  annotation should tell the SDT exactly how to update its metadata.
	//  For example, a division instruction will write type 'n' (NUM) as
	//  the metadata for result registers EDX:EAX. So, the annotation should
	//  list 'n', EDX, EAX, and a terminator of ZZ. CWD (convert word to
	//  doubleword) should have a list of n EAX ZZ.

SMPTypeCategory[NN_null] = 0;            // Unknown Operation
SMPTypeCategory[NN_aaa] = 2;                 // ASCII Adjust after Addition
SMPTypeCategory[NN_aad] = 2;                 // ASCII Adjust AX before Division
SMPTypeCategory[NN_aam] = 2;                 // ASCII Adjust AX after Multiply
SMPTypeCategory[NN_aas] = 2;                 // ASCII Adjust AL after Subtraction
SMPTypeCategory[NN_adc] = 5;                 // Add with Carry
SMPTypeCategory[NN_add] = 5;                 // Add
SMPTypeCategory[NN_and] = 10;                 // Logical AND
SMPTypeCategory[NN_arpl] = 1;                // Adjust RPL Field of Selector
SMPTypeCategory[NN_bound] = 1;               // Check Array Index Against Bounds
SMPTypeCategory[NN_bsf] = 2;                 // Bit Scan Forward
SMPTypeCategory[NN_bsr] = 2;                 // Bit Scan Reverse
SMPTypeCategory[NN_bt] = 2;                  // Bit Test
SMPTypeCategory[NN_btc] = 2;                 // Bit Test and Complement
SMPTypeCategory[NN_btr] = 2;                 // Bit Test and Reset
SMPTypeCategory[NN_bts] = 2;                 // Bit Test and Set
SMPTypeCategory[NN_call] = 1;                // Call Procedure
SMPTypeCategory[NN_callfi] = 1;              // Indirect Call Far Procedure
SMPTypeCategory[NN_callni] = 1;              // Indirect Call Near Procedure
SMPTypeCategory[NN_cbw] = 2;                 // AL -> AX (with sign)            ** No ops?
SMPTypeCategory[NN_cwde] = 2;                // AX -> EAX (with sign)           **
SMPTypeCategory[NN_cdqe] = 2;                // EAX -> RAX (with sign)          **
SMPTypeCategory[NN_clc] = 1;                 // Clear Carry Flag
SMPTypeCategory[NN_cld] = 1;                 // Clear Direction Flag
SMPTypeCategory[NN_cli] = 1;                 // Clear Interrupt Flag
SMPTypeCategory[NN_clts] = 1;                // Clear Task-Switched Flag in CR0
SMPTypeCategory[NN_cmc] = 1;                 // Complement Carry Flag
SMPTypeCategory[NN_cmp] = 1;                 // Compare Two Operands
SMPTypeCategory[NN_cmps] = 14;                // Compare Strings
SMPTypeCategory[NN_cwd] = 2;                 // AX -> DX:AX (with sign)
SMPTypeCategory[NN_cdq] = 2;                 // EAX -> EDX:EAX (with sign)
SMPTypeCategory[NN_cqo] = 2;                 // RAX -> RDX:RAX (with sign)
SMPTypeCategory[NN_daa] = 2;                 // Decimal Adjust AL after Addition
SMPTypeCategory[NN_das] = 2;                 // Decimal Adjust AL after Subtraction
SMPTypeCategory[NN_dec] = 4;                 // Decrement by 1
SMPTypeCategory[NN_div] = 7;                 // Unsigned Divide
SMPTypeCategory[NN_enterw] = 0;              // Make Stack Frame for Procedure Parameters  **
SMPTypeCategory[NN_enter] = 0;               // Make Stack Frame for Procedure Parameters  **
SMPTypeCategory[NN_enterd] = 0;              // Make Stack Frame for Procedure Parameters  **
SMPTypeCategory[NN_enterq] = 0;              // Make Stack Frame for Procedure Parameters  **
SMPTypeCategory[NN_hlt] = 0;                 // Halt
SMPTypeCategory[NN_idiv] = 7;                // Signed Divide
SMPTypeCategory[NN_imul] = 7;                // Signed Multiply
SMPTypeCategory[NN_in] = 0;                  // Input from Port                         **
SMPTypeCategory[NN_inc] = 4;                 // Increment by 1
SMPTypeCategory[NN_ins] = 2;                 // Input Byte(s) from Port to String       **
SMPTypeCategory[NN_int] = 0;                 // Call to Interrupt Procedure
SMPTypeCategory[NN_into] = 0;                // Call to Interrupt Procedure if Overflow Flag = 1
SMPTypeCategory[NN_int3] = 0;                // Trap to Debugger
SMPTypeCategory[NN_iretw] = 0;               // Interrupt Return
SMPTypeCategory[NN_iret] = 0;                // Interrupt Return
SMPTypeCategory[NN_iretd] = 0;               // Interrupt Return (use32)
SMPTypeCategory[NN_iretq] = 0;               // Interrupt Return (use64)
SMPTypeCategory[NN_ja] = 1;                  // Jump if Above (CF=0 & ZF=0)
SMPTypeCategory[NN_jae] = 1;                 // Jump if Above or Equal (CF=0)
SMPTypeCategory[NN_jb] = 1;                  // Jump if Below (CF=1)
SMPTypeCategory[NN_jbe] = 1;                 // Jump if Below or Equal (CF=1 | ZF=1)
SMPTypeCategory[NN_jc] = 1;                  // Jump if Carry (CF=1)
SMPTypeCategory[NN_jcxz] = 1;                // Jump if CX is 0
SMPTypeCategory[NN_jecxz] = 1;               // Jump if ECX is 0
SMPTypeCategory[NN_jrcxz] = 1;               // Jump if RCX is 0
SMPTypeCategory[NN_je] = 1;                  // Jump if Equal (ZF=1)
SMPTypeCategory[NN_jg] = 1;                  // Jump if Greater (ZF=0 & SF=OF)
SMPTypeCategory[NN_jge] = 1;                 // Jump if Greater or Equal (SF=OF)
SMPTypeCategory[NN_jl] = 1;                  // Jump if Less (SF!=OF)
SMPTypeCategory[NN_jle] = 1;                 // Jump if Less or Equal (ZF=1 | SF!=OF)
SMPTypeCategory[NN_jna] = 1;                 // Jump if Not Above (CF=1 | ZF=1)
SMPTypeCategory[NN_jnae] = 1;                // Jump if Not Above or Equal (CF=1)
SMPTypeCategory[NN_jnb] = 1;                 // Jump if Not Below (CF=0)
SMPTypeCategory[NN_jnbe] = 1;                // Jump if Not Below or Equal (CF=0 & ZF=0)
SMPTypeCategory[NN_jnc] = 1;                 // Jump if Not Carry (CF=0)
SMPTypeCategory[NN_jne] = 1;                 // Jump if Not Equal (ZF=0)
SMPTypeCategory[NN_jng] = 1;                 // Jump if Not Greater (ZF=1 | SF!=OF)
SMPTypeCategory[NN_jnge] = 1;                // Jump if Not Greater or Equal (ZF=1)
SMPTypeCategory[NN_jnl] = 1;                 // Jump if Not Less (SF=OF)
SMPTypeCategory[NN_jnle] = 1;                // Jump if Not Less or Equal (ZF=0 & SF=OF)
SMPTypeCategory[NN_jno] = 1;                 // Jump if Not Overflow (OF=0)
SMPTypeCategory[NN_jnp] = 1;                 // Jump if Not Parity (PF=0)
SMPTypeCategory[NN_jns] = 1;                 // Jump if Not Sign (SF=0)
SMPTypeCategory[NN_jnz] = 1;                 // Jump if Not Zero (ZF=0)
SMPTypeCategory[NN_jo] = 1;                  // Jump if Overflow (OF=1)
SMPTypeCategory[NN_jp] = 1;                  // Jump if Parity (PF=1)
SMPTypeCategory[NN_jpe] = 1;                 // Jump if Parity Even (PF=1)
SMPTypeCategory[NN_jpo] = 1;                 // Jump if Parity Odd  (PF=0)
SMPTypeCategory[NN_js] = 1;                  // Jump if Sign (SF=1)
SMPTypeCategory[NN_jz] = 1;                  // Jump if Zero (ZF=1)
SMPTypeCategory[NN_jmp] = 1;                 // Jump
SMPTypeCategory[NN_jmpfi] = 1;               // Indirect Far Jump
SMPTypeCategory[NN_jmpni] = 1;               // Indirect Near Jump
SMPTypeCategory[NN_jmpshort] = 1;            // Jump Short (not used)
SMPTypeCategory[NN_lahf] = 2;                // Load Flags into AH Register
SMPTypeCategory[NN_lar] = 2;                 // Load Access Rights Byte
SMPTypeCategory[NN_lea] = 10;                // Load Effective Address           **
SMPTypeCategory[NN_leavew] = 0;              // High Level Procedure Exit        **
SMPTypeCategory[NN_leave] = 0;               // High Level Procedure Exit        **
SMPTypeCategory[NN_leaved] = 0;              // High Level Procedure Exit        **
SMPTypeCategory[NN_leaveq] = 0;              // High Level Procedure Exit        **
SMPTypeCategory[NN_lgdt] = 0;                // Load Global Descriptor Table Register
SMPTypeCategory[NN_lidt] = 0;                // Load Interrupt Descriptor Table Register
SMPTypeCategory[NN_lgs] = 6;                 // Load Full Pointer to GS:xx
SMPTypeCategory[NN_lss] = 6;                 // Load Full Pointer to SS:xx
SMPTypeCategory[NN_lds] = 6;                 // Load Full Pointer to DS:xx
SMPTypeCategory[NN_les] = 6;                 // Load Full Pointer to ES:xx
SMPTypeCategory[NN_lfs] = 6;                 // Load Full Pointer to FS:xx
SMPTypeCategory[NN_lldt] = 0;                // Load Local Descriptor Table Register
SMPTypeCategory[NN_lmsw] = 1;                // Load Machine Status Word
SMPTypeCategory[NN_lock] = 1;                // Assert LOCK# Signal Prefix
SMPTypeCategory[NN_lods] = 0;                // Load String
SMPTypeCategory[NN_loopw] = 1;               // Loop while ECX != 0
SMPTypeCategory[NN_loop] = 1;                // Loop while CX != 0
SMPTypeCategory[NN_loopd] = 1;               // Loop while ECX != 0
SMPTypeCategory[NN_loopq] = 1;               // Loop while RCX != 0
SMPTypeCategory[NN_loopwe] = 1;              // Loop while CX != 0 and ZF=1
SMPTypeCategory[NN_loope] = 1;               // Loop while rCX != 0 and ZF=1
SMPTypeCategory[NN_loopde] = 1;              // Loop while ECX != 0 and ZF=1
SMPTypeCategory[NN_loopqe] = 1;              // Loop while RCX != 0 and ZF=1
SMPTypeCategory[NN_loopwne] = 1;             // Loop while CX != 0 and ZF=0
SMPTypeCategory[NN_loopne] = 1;              // Loop while rCX != 0 and ZF=0
SMPTypeCategory[NN_loopdne] = 1;             // Loop while ECX != 0 and ZF=0
SMPTypeCategory[NN_loopqne] = 1;             // Loop while RCX != 0 and ZF=0
SMPTypeCategory[NN_lsl] = 6;                 // Load Segment Limit
SMPTypeCategory[NN_ltr] = 1;                 // Load Task Register
SMPTypeCategory[NN_mov] = 3;                 // Move Data
SMPTypeCategory[NN_movsp] = 3;               // Move to/from Special Registers
SMPTypeCategory[NN_movs] = 0;                // Move Byte(s) from String to String
SMPTypeCategory[NN_movsx] = 3;               // Move with Sign-Extend
SMPTypeCategory[NN_movzx] = 3;               // Move with Zero-Extend
SMPTypeCategory[NN_mul] = 7;                 // Unsigned Multiplication of AL or AX
SMPTypeCategory[NN_neg] = 2;                 // Two's Complement Negation
SMPTypeCategory[NN_nop] = 1;                 // No Operation
SMPTypeCategory[NN_not] = 2;                 // One's Complement Negation
SMPTypeCategory[NN_or] = 10;                  // Logical Inclusive OR
SMPTypeCategory[NN_out] = 0;                 // Output to Port
SMPTypeCategory[NN_outs] = 0;                // Output Byte(s) to Port
SMPTypeCategory[NN_pop] = 11;                 // Pop a word from the Stack
SMPTypeCategory[NN_popaw] = 11;               // Pop all General Registers
SMPTypeCategory[NN_popa] = 11;                // Pop all General Registers
SMPTypeCategory[NN_popad] = 11;               // Pop all General Registers (use32)
SMPTypeCategory[NN_popaq] = 11;               // Pop all General Registers (use64)
SMPTypeCategory[NN_popfw] = 11;               // Pop Stack into Flags Register         **
SMPTypeCategory[NN_popf] = 11;                // Pop Stack into Flags Register         **
SMPTypeCategory[NN_popfd] = 11;               // Pop Stack into Eflags Register        **
SMPTypeCategory[NN_popfq] = 11;               // Pop Stack into Rflags Register        **
SMPTypeCategory[NN_push] = 11;                // Push Operand onto the Stack
SMPTypeCategory[NN_pushaw] = 11;              // Push all General Registers
SMPTypeCategory[NN_pusha] = 11;               // Push all General Registers
SMPTypeCategory[NN_pushad] = 11;              // Push all General Registers (use32)
SMPTypeCategory[NN_pushaq] = 11;              // Push all General Registers (use64)
SMPTypeCategory[NN_pushfw] = 11;              // Push Flags Register onto the Stack
SMPTypeCategory[NN_pushf] = 11;               // Push Flags Register onto the Stack
SMPTypeCategory[NN_pushfd] = 11;              // Push Flags Register onto the Stack (use32)
SMPTypeCategory[NN_pushfq] = 11;              // Push Flags Register onto the Stack (use64)
SMPTypeCategory[NN_rcl] = 2;                 // Rotate Through Carry Left
SMPTypeCategory[NN_rcr] = 2;                 // Rotate Through Carry Right
SMPTypeCategory[NN_rol] = 2;                 // Rotate Left
SMPTypeCategory[NN_ror] = 2;                 // Rotate Right
SMPTypeCategory[NN_rep] = 0;                 // Repeat String Operation
SMPTypeCategory[NN_repe] = 0;                // Repeat String Operation while ZF=1
SMPTypeCategory[NN_repne] = 0;               // Repeat String Operation while ZF=0
SMPTypeCategory[NN_retn] = 0;                // Return Near from Procedure
SMPTypeCategory[NN_retf] = 0;                // Return Far from Procedure
SMPTypeCategory[NN_sahf] = 14;                // Store AH into Flags Register
SMPTypeCategory[NN_sal] = 2;                 // Shift Arithmetic Left
SMPTypeCategory[NN_sar] = 2;                 // Shift Arithmetic Right
SMPTypeCategory[NN_shl] = 2;                 // Shift Logical Left
SMPTypeCategory[NN_shr] = 2;                 // Shift Logical Right
SMPTypeCategory[NN_sbb] = 5;                 // Integer Subtraction with Borrow
SMPTypeCategory[NN_scas] = 14;                // Compare String
SMPTypeCategory[NN_seta] = 2;                // Set Byte if Above (CF=0 & ZF=0)
SMPTypeCategory[NN_setae] = 2;               // Set Byte if Above or Equal (CF=0)
SMPTypeCategory[NN_setb] = 2;                // Set Byte if Below (CF=1)
SMPTypeCategory[NN_setbe] = 2;               // Set Byte if Below or Equal (CF=1 | ZF=1)
SMPTypeCategory[NN_setc] = 2;                // Set Byte if Carry (CF=1)
SMPTypeCategory[NN_sete] = 2;                // Set Byte if Equal (ZF=1)
SMPTypeCategory[NN_setg] = 2;                // Set Byte if Greater (ZF=0 & SF=OF)
SMPTypeCategory[NN_setge] = 2;               // Set Byte if Greater or Equal (SF=OF)
SMPTypeCategory[NN_setl] = 2;                // Set Byte if Less (SF!=OF)
SMPTypeCategory[NN_setle] = 2;               // Set Byte if Less or Equal (ZF=1 | SF!=OF)
SMPTypeCategory[NN_setna] = 2;               // Set Byte if Not Above (CF=1 | ZF=1)
SMPTypeCategory[NN_setnae] = 2;              // Set Byte if Not Above or Equal (CF=1)
SMPTypeCategory[NN_setnb] = 2;               // Set Byte if Not Below (CF=0)
SMPTypeCategory[NN_setnbe] = 2;              // Set Byte if Not Below or Equal (CF=0 & ZF=0)
SMPTypeCategory[NN_setnc] = 2;               // Set Byte if Not Carry (CF=0)
SMPTypeCategory[NN_setne] = 2;               // Set Byte if Not Equal (ZF=0)
SMPTypeCategory[NN_setng] = 2;               // Set Byte if Not Greater (ZF=1 | SF!=OF)
SMPTypeCategory[NN_setnge] = 2;              // Set Byte if Not Greater or Equal (ZF=1)
SMPTypeCategory[NN_setnl] = 2;               // Set Byte if Not Less (SF=OF)
SMPTypeCategory[NN_setnle] = 2;              // Set Byte if Not Less or Equal (ZF=0 & SF=OF)
SMPTypeCategory[NN_setno] = 2;               // Set Byte if Not Overflow (OF=0)
SMPTypeCategory[NN_setnp] = 2;               // Set Byte if Not Parity (PF=0)
SMPTypeCategory[NN_setns] = 2;               // Set Byte if Not Sign (SF=0)
SMPTypeCategory[NN_setnz] = 2;               // Set Byte if Not Zero (ZF=0)
SMPTypeCategory[NN_seto] = 2;                // Set Byte if Overflow (OF=1)
SMPTypeCategory[NN_setp] = 2;                // Set Byte if Parity (PF=1)
SMPTypeCategory[NN_setpe] = 2;               // Set Byte if Parity Even (PF=1)
SMPTypeCategory[NN_setpo] = 2;               // Set Byte if Parity Odd  (PF=0)
SMPTypeCategory[NN_sets] = 2;                // Set Byte if Sign (SF=1)
SMPTypeCategory[NN_setz] = 2;                // Set Byte if Zero (ZF=1)
SMPTypeCategory[NN_sgdt] = 0;                // Store Global Descriptor Table Register
SMPTypeCategory[NN_sidt] = 0;                // Store Interrupt Descriptor Table Register
SMPTypeCategory[NN_shld] = 2;                // Double Precision Shift Left
SMPTypeCategory[NN_shrd] = 2;                // Double Precision Shift Right
SMPTypeCategory[NN_sldt] = 6;                // Store Local Descriptor Table Register
SMPTypeCategory[NN_smsw] = 2;                // Store Machine Status Word
SMPTypeCategory[NN_stc] = 1;                 // Set Carry Flag
SMPTypeCategory[NN_std] = 1;                 // Set Direction Flag
SMPTypeCategory[NN_sti] = 1;                 // Set Interrupt Flag
SMPTypeCategory[NN_stos] = 0;                // Store String
SMPTypeCategory[NN_str] = 6;                 // Store Task Register
SMPTypeCategory[NN_sub] = 5;                 // Integer Subtraction
SMPTypeCategory[NN_test] = 1;                // Logical Compare
SMPTypeCategory[NN_verr] = 1;                // Verify a Segment for Reading
SMPTypeCategory[NN_verw] = 1;                // Verify a Segment for Writing
SMPTypeCategory[NN_wait] = 1;                // Wait until BUSY# Pin is Inactive (HIGH)
SMPTypeCategory[NN_xchg] = 12;                // Exchange Register/Memory with Register
SMPTypeCategory[NN_xlat] = 0;                // Table Lookup Translation
SMPTypeCategory[NN_xor] = 2;                 // Logical Exclusive OR

//
//      486 instructions
//

SMPTypeCategory[NN_cmpxchg] = 12;             // Compare and Exchange
SMPTypeCategory[NN_bswap] = 1;               // Swap bytes in register
SMPTypeCategory[NN_xadd] = 12;                // t<-dest; dest<-src+dest; src<-t
SMPTypeCategory[NN_invd] = 1;                // Invalidate Data Cache
SMPTypeCategory[NN_wbinvd] = 1;              // Invalidate Data Cache (write changes)
SMPTypeCategory[NN_invlpg] = 1;              // Invalidate TLB entry

//
//      Pentium instructions
//

SMPTypeCategory[NN_rdmsr] = 8;               // Read Machine Status Register
SMPTypeCategory[NN_wrmsr] = 1;               // Write Machine Status Register
SMPTypeCategory[NN_cpuid] = 8;               // Get CPU ID
SMPTypeCategory[NN_cmpxchg8b] = 12;           // Compare and Exchange Eight Bytes
SMPTypeCategory[NN_rdtsc] = 8;               // Read Time Stamp Counter
SMPTypeCategory[NN_rsm] = 1;                 // Resume from System Management Mode

//
//      Pentium Pro instructions
//

SMPTypeCategory[NN_cmova] = 0;               // Move if Above (CF=0 & ZF=0)
SMPTypeCategory[NN_cmovb] = 0;               // Move if Below (CF=1)
SMPTypeCategory[NN_cmovbe] = 0;              // Move if Below or Equal (CF=1 | ZF=1)
SMPTypeCategory[NN_cmovg] = 0;               // Move if Greater (ZF=0 & SF=OF)
SMPTypeCategory[NN_cmovge] = 0;              // Move if Greater or Equal (SF=OF)
SMPTypeCategory[NN_cmovl] = 0;               // Move if Less (SF!=OF)
SMPTypeCategory[NN_cmovle] = 0;              // Move if Less or Equal (ZF=1 | SF!=OF)
SMPTypeCategory[NN_cmovnb] = 0;              // Move if Not Below (CF=0)
SMPTypeCategory[NN_cmovno] = 0;              // Move if Not Overflow (OF=0)
SMPTypeCategory[NN_cmovnp] = 0;              // Move if Not Parity (PF=0)
SMPTypeCategory[NN_cmovns] = 0;              // Move if Not Sign (SF=0)
SMPTypeCategory[NN_cmovnz] = 0;              // Move if Not Zero (ZF=0)
SMPTypeCategory[NN_cmovo] = 0;               // Move if Overflow (OF=1)
SMPTypeCategory[NN_cmovp] = 0;               // Move if Parity (PF=1)
SMPTypeCategory[NN_cmovs] = 0;               // Move if Sign (SF=1)
SMPTypeCategory[NN_cmovz] = 0;               // Move if Zero (ZF=1)
SMPTypeCategory[NN_fcmovb] = 1;              // Floating Move if Below          
SMPTypeCategory[NN_fcmove] = 1;              // Floating Move if Equal          
SMPTypeCategory[NN_fcmovbe] = 1;             // Floating Move if Below or Equal 
SMPTypeCategory[NN_fcmovu] = 1;              // Floating Move if Unordered      
SMPTypeCategory[NN_fcmovnb] = 1;             // Floating Move if Not Below      
SMPTypeCategory[NN_fcmovne] = 1;             // Floating Move if Not Equal      
SMPTypeCategory[NN_fcmovnbe] = 1;            // Floating Move if Not Below or Equal
SMPTypeCategory[NN_fcmovnu] = 1;             // Floating Move if Not Unordered     
SMPTypeCategory[NN_fcomi] = 1;               // FP Compare, result in EFLAGS
SMPTypeCategory[NN_fucomi] = 1;              // FP Unordered Compare, result in EFLAGS
SMPTypeCategory[NN_fcomip] = 1;              // FP Compare, result in EFLAGS, pop stack
SMPTypeCategory[NN_fucomip] = 1;             // FP Unordered Compare, result in EFLAGS, pop stack
SMPTypeCategory[NN_rdpmc] = 8;               // Read Performance Monitor Counter

//
//      FPP instructions
//

SMPTypeCategory[NN_fld] = 14;                 // Load Real             ** Infer src is 'n'
SMPTypeCategory[NN_fst] = 9;                 // Store Real            
SMPTypeCategory[NN_fstp] = 9;                // Store Real and Pop   
SMPTypeCategory[NN_fxch] = 1;                // Exchange Registers
SMPTypeCategory[NN_fild] = 14;                // Load Integer          ** Infer src is 'n'
SMPTypeCategory[NN_fist] = 13;                // Store Integer
SMPTypeCategory[NN_fistp] = 13;               // Store Integer and Pop
SMPTypeCategory[NN_fbld] = 1;                // Load BCD
SMPTypeCategory[NN_fbstp] = 13;               // Store BCD and Pop
SMPTypeCategory[NN_fadd] = 14;                // Add Real
SMPTypeCategory[NN_faddp] = 14;               // Add Real and Pop
SMPTypeCategory[NN_fiadd] = 14;               // Add Integer
SMPTypeCategory[NN_fsub] = 14;                // Subtract Real
SMPTypeCategory[NN_fsubp] = 14;               // Subtract Real and Pop
SMPTypeCategory[NN_fisub] = 14;               // Subtract Integer
SMPTypeCategory[NN_fsubr] = 14;               // Subtract Real Reversed
SMPTypeCategory[NN_fsubrp] = 14;              // Subtract Real Reversed and Pop
SMPTypeCategory[NN_fisubr] = 14;              // Subtract Integer Reversed
SMPTypeCategory[NN_fmul] = 14;                // Multiply Real
SMPTypeCategory[NN_fmulp] = 14;               // Multiply Real and Pop
SMPTypeCategory[NN_fimul] = 14;               // Multiply Integer
SMPTypeCategory[NN_fdiv] = 14;                // Divide Real
SMPTypeCategory[NN_fdivp] = 14;               // Divide Real and Pop
SMPTypeCategory[NN_fidiv] = 14;               // Divide Integer
SMPTypeCategory[NN_fdivr] = 14;               // Divide Real Reversed
SMPTypeCategory[NN_fdivrp] = 14;              // Divide Real Reversed and Pop
SMPTypeCategory[NN_fidivr] = 14;              // Divide Integer Reversed
SMPTypeCategory[NN_fsqrt] = 1;               // Square Root
SMPTypeCategory[NN_fscale] = 1;              // Scale:  st(0) <- st(0) * 2^st(1)
SMPTypeCategory[NN_fprem] = 1;               // Partial Remainder
SMPTypeCategory[NN_frndint] = 1;             // Round to Integer
SMPTypeCategory[NN_fxtract] = 1;             // Extract exponent and significand
SMPTypeCategory[NN_fabs] = 1;                // Absolute value
SMPTypeCategory[NN_fchs] = 1;                // Change Sign
SMPTypeCategory[NN_fcom] = 1;                // Compare Real
SMPTypeCategory[NN_fcomp] = 1;               // Compare Real and Pop
SMPTypeCategory[NN_fcompp] = 1;              // Compare Real and Pop Twice
SMPTypeCategory[NN_ficom] = 1;               // Compare Integer
SMPTypeCategory[NN_ficomp] = 1;              // Compare Integer and Pop
SMPTypeCategory[NN_ftst] = 1;                // Test
SMPTypeCategory[NN_fxam] = 1;                // Examine
SMPTypeCategory[NN_fptan] = 1;               // Partial tangent
SMPTypeCategory[NN_fpatan] = 1;              // Partial arctangent
SMPTypeCategory[NN_f2xm1] = 1;               // 2^x - 1
SMPTypeCategory[NN_fyl2x] = 1;               // Y * lg2(X)
SMPTypeCategory[NN_fyl2xp1] = 1;             // Y * lg2(X+1)
SMPTypeCategory[NN_fldz] = 1;                // Load +0.0
SMPTypeCategory[NN_fld1] = 1;                // Load +1.0
SMPTypeCategory[NN_fldpi] = 1;               // Load PI=3.14...
SMPTypeCategory[NN_fldl2t] = 1;              // Load lg2(10)
SMPTypeCategory[NN_fldl2e] = 1;              // Load lg2(e)
SMPTypeCategory[NN_fldlg2] = 1;              // Load lg10(2)
SMPTypeCategory[NN_fldln2] = 1;              // Load ln(2)
SMPTypeCategory[NN_finit] = 1;               // Initialize Processor
SMPTypeCategory[NN_fninit] = 1;              // Initialize Processor (no wait)
SMPTypeCategory[NN_fsetpm] = 1;              // Set Protected Mode
SMPTypeCategory[NN_fldcw] = 14;               // Load Control Word
SMPTypeCategory[NN_fstcw] = 13;               // Store Control Word
SMPTypeCategory[NN_fnstcw] = 13;              // Store Control Word (no wait)
SMPTypeCategory[NN_fstsw] = 2;               // Store Status Word to memory or AX
SMPTypeCategory[NN_fnstsw] = 2;              // Store Status Word (no wait) to memory or AX
SMPTypeCategory[NN_fclex] = 1;               // Clear Exceptions
SMPTypeCategory[NN_fnclex] = 1;              // Clear Exceptions (no wait)
SMPTypeCategory[NN_fstenv] = 13;              // Store Environment
SMPTypeCategory[NN_fnstenv] = 13;             // Store Environment (no wait)
SMPTypeCategory[NN_fldenv] = 14;              // Load Environment
SMPTypeCategory[NN_fsave] = 13;               // Save State
SMPTypeCategory[NN_fnsave] = 13;              // Save State (no wait)
SMPTypeCategory[NN_frstor] = 14;              // Restore State    **  infer src is 'n'
SMPTypeCategory[NN_fincstp] = 1;             // Increment Stack Pointer
SMPTypeCategory[NN_fdecstp] = 1;             // Decrement Stack Pointer
SMPTypeCategory[NN_ffree] = 1;               // Free Register
SMPTypeCategory[NN_fnop] = 1;                // No Operation
SMPTypeCategory[NN_feni] = 1;                // (8087 only)
SMPTypeCategory[NN_fneni] = 1;               // (no wait) (8087 only)
SMPTypeCategory[NN_fdisi] = 1;               // (8087 only)
SMPTypeCategory[NN_fndisi] = 1;              // (no wait) (8087 only)

//
//      80387 instructions
//

SMPTypeCategory[NN_fprem1] = 1;              // Partial Remainder ( < half )
SMPTypeCategory[NN_fsincos] = 1;             // t<-cos(st); st<-sin(st); push t
SMPTypeCategory[NN_fsin] = 1;                // Sine
SMPTypeCategory[NN_fcos] = 1;                // Cosine
SMPTypeCategory[NN_fucom] = 1;               // Compare Unordered Real
SMPTypeCategory[NN_fucomp] = 1;              // Compare Unordered Real and Pop
SMPTypeCategory[NN_fucompp] = 1;             // Compare Unordered Real and Pop Twice

//
//      Instructions added 28.02.96
//

SMPTypeCategory[NN_setalc] = 2;              // Set AL to Carry Flag     **
SMPTypeCategory[NN_svdc] = 0;                // Save Register and Descriptor
SMPTypeCategory[NN_rsdc] = 0;                // Restore Register and Descriptor
SMPTypeCategory[NN_svldt] = 0;               // Save LDTR and Descriptor
SMPTypeCategory[NN_rsldt] = 0;               // Restore LDTR and Descriptor
SMPTypeCategory[NN_svts] = 1;                // Save TR and Descriptor
SMPTypeCategory[NN_rsts] = 1;                // Restore TR and Descriptor
SMPTypeCategory[NN_icebp] = 1;               // ICE Break Point
SMPTypeCategory[NN_loadall] = 0;             // Load the entire CPU state from ES:EDI ???

//
//      MMX instructions
//

SMPTypeCategory[NN_emms] = 1;                // Empty MMX state
SMPTypeCategory[NN_movd] = 15;                // Move 32 bits
SMPTypeCategory[NN_movq] = 15;                // Move 64 bits
SMPTypeCategory[NN_packsswb] = 14;            // Pack with Signed Saturation (Word->Byte)
SMPTypeCategory[NN_packssdw] = 14;            // Pack with Signed Saturation (Dword->Word)
SMPTypeCategory[NN_packuswb] = 14;            // Pack with Unsigned Saturation (Word->Byte)
SMPTypeCategory[NN_paddb] = 14;               // Packed Add Byte
SMPTypeCategory[NN_paddw] = 14;               // Packed Add Word
SMPTypeCategory[NN_paddd] = 14;               // Packed Add Dword
SMPTypeCategory[NN_paddsb] = 14;              // Packed Add with Saturation (Byte)
SMPTypeCategory[NN_paddsw] = 14;              // Packed Add with Saturation (Word)
SMPTypeCategory[NN_paddusb] = 14;             // Packed Add Unsigned with Saturation (Byte)
SMPTypeCategory[NN_paddusw] = 14;             // Packed Add Unsigned with Saturation (Word)
SMPTypeCategory[NN_pand] = 14;                // Bitwise Logical And
SMPTypeCategory[NN_pandn] = 14;               // Bitwise Logical And Not
SMPTypeCategory[NN_pcmpeqb] = 14;             // Packed Compare for Equal (Byte)
SMPTypeCategory[NN_pcmpeqw] = 14;             // Packed Compare for Equal (Word)
SMPTypeCategory[NN_pcmpeqd] = 14;             // Packed Compare for Equal (Dword)
SMPTypeCategory[NN_pcmpgtb] = 14;             // Packed Compare for Greater Than (Byte)
SMPTypeCategory[NN_pcmpgtw] = 14;             // Packed Compare for Greater Than (Word)
SMPTypeCategory[NN_pcmpgtd] = 14;             // Packed Compare for Greater Than (Dword)
SMPTypeCategory[NN_pmaddwd] = 14;             // Packed Multiply and Add
SMPTypeCategory[NN_pmulhw] = 14;              // Packed Multiply High
SMPTypeCategory[NN_pmullw] = 14;              // Packed Multiply Low
SMPTypeCategory[NN_por] = 14;                 // Bitwise Logical Or
SMPTypeCategory[NN_psllw] = 14;               // Packed Shift Left Logical (Word)
SMPTypeCategory[NN_pslld] = 14;               // Packed Shift Left Logical (Dword)
SMPTypeCategory[NN_psllq] = 14;               // Packed Shift Left Logical (Qword)
SMPTypeCategory[NN_psraw] = 14;               // Packed Shift Right Arithmetic (Word)
SMPTypeCategory[NN_psrad] = 14;               // Packed Shift Right Arithmetic (Dword)
SMPTypeCategory[NN_psrlw] = 14;               // Packed Shift Right Logical (Word)
SMPTypeCategory[NN_psrld] = 14;               // Packed Shift Right Logical (Dword)
SMPTypeCategory[NN_psrlq] = 14;               // Packed Shift Right Logical (Qword)
SMPTypeCategory[NN_psubb] = 14;               // Packed Subtract Byte
SMPTypeCategory[NN_psubw] = 14;               // Packed Subtract Word
SMPTypeCategory[NN_psubd] = 14;               // Packed Subtract Dword
SMPTypeCategory[NN_psubsb] = 14;              // Packed Subtract with Saturation (Byte)
SMPTypeCategory[NN_psubsw] = 14;              // Packed Subtract with Saturation (Word)
SMPTypeCategory[NN_psubusb] = 14;             // Packed Subtract Unsigned with Saturation (Byte)
SMPTypeCategory[NN_psubusw] = 14;             // Packed Subtract Unsigned with Saturation (Word)
SMPTypeCategory[NN_punpckhbw] = 14;           // Unpack High Packed Data (Byte->Word)
SMPTypeCategory[NN_punpckhwd] = 14;           // Unpack High Packed Data (Word->Dword)
SMPTypeCategory[NN_punpckhdq] = 14;           // Unpack High Packed Data (Dword->Qword)
SMPTypeCategory[NN_punpcklbw] = 14;           // Unpack Low Packed Data (Byte->Word)
SMPTypeCategory[NN_punpcklwd] = 14;           // Unpack Low Packed Data (Word->Dword)
SMPTypeCategory[NN_punpckldq] = 14;           // Unpack Low Packed Data (Dword->Qword)
SMPTypeCategory[NN_pxor] = 14;                // Bitwise Logical Exclusive Or

//
//      Undocumented Deschutes processor instructions
//

SMPTypeCategory[NN_fxsave] = 1;              // Fast save FP context            ** to where?
SMPTypeCategory[NN_fxrstor] = 1;             // Fast restore FP context         ** from where?

//      Pentium II instructions

SMPTypeCategory[NN_sysenter] = 1;            // Fast Transition to System Call Entry Point
SMPTypeCategory[NN_sysexit] = 1;             // Fast Transition from System Call Entry Point

//      3DNow! instructions

SMPTypeCategory[NN_pavgusb] = 14;             // Packed 8-bit Unsigned Integer Averaging
SMPTypeCategory[NN_pfadd] = 14;               // Packed Floating-Point Addition
SMPTypeCategory[NN_pfsub] = 14;               // Packed Floating-Point Subtraction
SMPTypeCategory[NN_pfsubr] = 14;              // Packed Floating-Point Reverse Subtraction
SMPTypeCategory[NN_pfacc] = 14;               // Packed Floating-Point Accumulate
SMPTypeCategory[NN_pfcmpge] = 14;             // Packed Floating-Point Comparison, Greater or Equal
SMPTypeCategory[NN_pfcmpgt] = 14;             // Packed Floating-Point Comparison, Greater
SMPTypeCategory[NN_pfcmpeq] = 14;             // Packed Floating-Point Comparison, Equal
SMPTypeCategory[NN_pfmin] = 14;               // Packed Floating-Point Minimum
SMPTypeCategory[NN_pfmax] = 14;               // Packed Floating-Point Maximum
SMPTypeCategory[NN_pi2fd] = 14;               // Packed 32-bit Integer to Floating-Point
SMPTypeCategory[NN_pf2id] = 14;               // Packed Floating-Point to 32-bit Integer
SMPTypeCategory[NN_pfrcp] = 14;               // Packed Floating-Point Reciprocal Approximation
SMPTypeCategory[NN_pfrsqrt] = 14;             // Packed Floating-Point Reciprocal Square Root Approximation
SMPTypeCategory[NN_pfmul] = 14;               // Packed Floating-Point Multiplication
SMPTypeCategory[NN_pfrcpit1] = 14;            // Packed Floating-Point Reciprocal First Iteration Step
SMPTypeCategory[NN_pfrsqit1] = 14;            // Packed Floating-Point Reciprocal Square Root First Iteration Step
SMPTypeCategory[NN_pfrcpit2] = 14;            // Packed Floating-Point Reciprocal Second Iteration Step
SMPTypeCategory[NN_pmulhrw] = 14;             // Packed Floating-Point 16-bit Integer Multiply with rounding
SMPTypeCategory[NN_femms] = 1;               // Faster entry/exit of the MMX or floating-point state
SMPTypeCategory[NN_prefetch] = 1;            // Prefetch at least a 32-byte line into L1 data cache
SMPTypeCategory[NN_prefetchw] = 1;           // Prefetch processor cache line into L1 data cache (mark as modified)


//      Pentium III instructions

SMPTypeCategory[NN_addps] = 14;               // Packed Single-FP Add
SMPTypeCategory[NN_addss] = 14;               // Scalar Single-FP Add
SMPTypeCategory[NN_andnps] = 14;              // Bitwise Logical And Not for Single-FP
SMPTypeCategory[NN_andps] = 14;               // Bitwise Logical And for Single-FP
SMPTypeCategory[NN_cmpps] = 14;               // Packed Single-FP Compare
SMPTypeCategory[NN_cmpss] = 14;               // Scalar Single-FP Compare
SMPTypeCategory[NN_comiss] = 14;              // Scalar Ordered Single-FP Compare and Set EFLAGS
SMPTypeCategory[NN_cvtpi2ps] = 14;            // Packed signed INT32 to Packed Single-FP conversion
SMPTypeCategory[NN_cvtps2pi] = 14;            // Packed Single-FP to Packed INT32 conversion
SMPTypeCategory[NN_cvtsi2ss] = 14;            // Scalar signed INT32 to Single-FP conversion
SMPTypeCategory[NN_cvtss2si] = 14;            // Scalar Single-FP to signed INT32 conversion
SMPTypeCategory[NN_cvttps2pi] = 14;           // Packed Single-FP to Packed INT32 conversion (truncate)
SMPTypeCategory[NN_cvttss2si] = 14;           // Scalar Single-FP to signed INT32 conversion (truncate)
SMPTypeCategory[NN_divps] = 14;               // Packed Single-FP Divide
SMPTypeCategory[NN_divss] = 14;               // Scalar Single-FP Divide
SMPTypeCategory[NN_ldmxcsr] = 14;             // Load Streaming SIMD Extensions Technology Control/Status Register
SMPTypeCategory[NN_maxps] = 14;               // Packed Single-FP Maximum
SMPTypeCategory[NN_maxss] = 14;               // Scalar Single-FP Maximum
SMPTypeCategory[NN_minps] = 14;               // Packed Single-FP Minimum
SMPTypeCategory[NN_minss] = 14;               // Scalar Single-FP Minimum
SMPTypeCategory[NN_movaps] = 15;              // Move Aligned Four Packed Single-FP  ** infer memsrc 'n'?
SMPTypeCategory[NN_movhlps] = 15;             // Move High to Low Packed Single-FP
SMPTypeCategory[NN_movhps] = 15;              // Move High Packed Single-FP
SMPTypeCategory[NN_movlhps] = 15;             // Move Low to High Packed Single-FP
SMPTypeCategory[NN_movlps] = 15;              // Move Low Packed Single-FP
SMPTypeCategory[NN_movmskps] = 15;            // Move Mask to Register
SMPTypeCategory[NN_movss] = 15;               // Move Scalar Single-FP
SMPTypeCategory[NN_movups] = 15;              // Move Unaligned Four Packed Single-FP
SMPTypeCategory[NN_mulps] = 14;               // Packed Single-FP Multiply
SMPTypeCategory[NN_mulss] = 14;               // Scalar Single-FP Multiply
SMPTypeCategory[NN_orps] = 14;                // Bitwise Logical OR for Single-FP Data
SMPTypeCategory[NN_rcpps] = 14;               // Packed Single-FP Reciprocal
SMPTypeCategory[NN_rcpss] = 14;               // Scalar Single-FP Reciprocal
SMPTypeCategory[NN_rsqrtps] = 14;             // Packed Single-FP Square Root Reciprocal
SMPTypeCategory[NN_rsqrtss] = 14;             // Scalar Single-FP Square Root Reciprocal
SMPTypeCategory[NN_shufps] = 14;              // Shuffle Single-FP
SMPTypeCategory[NN_sqrtps] = 14;              // Packed Single-FP Square Root
SMPTypeCategory[NN_sqrtss] = 14;              // Scalar Single-FP Square Root
SMPTypeCategory[NN_stmxcsr] = 15;             // Store Streaming SIMD Extensions Technology Control/Status Register    ** Infer dest is 'n'
SMPTypeCategory[NN_subps] = 14;               // Packed Single-FP Subtract
SMPTypeCategory[NN_subss] = 14;               // Scalar Single-FP Subtract
SMPTypeCategory[NN_ucomiss] = 14;             // Scalar Unordered Single-FP Compare and Set EFLAGS
SMPTypeCategory[NN_unpckhps] = 14;            // Unpack High Packed Single-FP Data
SMPTypeCategory[NN_unpcklps] = 14;            // Unpack Low Packed Single-FP Data
SMPTypeCategory[NN_xorps] = 14;               // Bitwise Logical XOR for Single-FP Data
SMPTypeCategory[NN_pavgb] = 14;               // Packed Average (Byte)
SMPTypeCategory[NN_pavgw] = 14;               // Packed Average (Word)
SMPTypeCategory[NN_pextrw] = 2;               // Extract Word
SMPTypeCategory[NN_pinsrw] = 14;              // Insert Word
SMPTypeCategory[NN_pmaxsw] = 14;              // Packed Signed Integer Word Maximum
SMPTypeCategory[NN_pmaxub] = 14;              // Packed Unsigned Integer Byte Maximum
SMPTypeCategory[NN_pminsw] = 14;              // Packed Signed Integer Word Minimum
SMPTypeCategory[NN_pminub] = 14;              // Packed Unsigned Integer Byte Minimum
SMPTypeCategory[NN_pmovmskb] = 2;             // Move Byte Mask to Integer
SMPTypeCategory[NN_pmulhuw] = 14;             // Packed Multiply High Unsigned
SMPTypeCategory[NN_psadbw] = 14;              // Packed Sum of Absolute Differences
SMPTypeCategory[NN_pshufw] = 14;              // Packed Shuffle Word
SMPTypeCategory[NN_maskmovq] = 15;            // Byte Mask write   ** Infer dest is 'n'
SMPTypeCategory[NN_movntps] = 13;             // Move Aligned Four Packed Single-FP Non Temporal  * infer dest is 'n'
SMPTypeCategory[NN_movntq] = 13;              // Move 64 Bits Non Temporal    ** Infer dest is 'n'
SMPTypeCategory[NN_prefetcht0] = 1;          // Prefetch to all cache levels
SMPTypeCategory[NN_prefetcht1] = 1;          // Prefetch to all cache levels
SMPTypeCategory[NN_prefetcht2] = 1;          // Prefetch to L2 cache
SMPTypeCategory[NN_prefetchnta] = 1;         // Prefetch to L1 cache
SMPTypeCategory[NN_sfence] = 1;              // Store Fence

// Pentium III Pseudo instructions

SMPTypeCategory[NN_cmpeqps] = 14;             // Packed Single-FP Compare EQ
SMPTypeCategory[NN_cmpltps] = 14;             // Packed Single-FP Compare LT
SMPTypeCategory[NN_cmpleps] = 14;             // Packed Single-FP Compare LE
SMPTypeCategory[NN_cmpunordps] = 14;          // Packed Single-FP Compare UNORD
SMPTypeCategory[NN_cmpneqps] = 14;            // Packed Single-FP Compare NOT EQ
SMPTypeCategory[NN_cmpnltps] = 14;            // Packed Single-FP Compare NOT LT
SMPTypeCategory[NN_cmpnleps] = 14;            // Packed Single-FP Compare NOT LE
SMPTypeCategory[NN_cmpordps] = 14;            // Packed Single-FP Compare ORDERED
SMPTypeCategory[NN_cmpeqss] = 14;             // Scalar Single-FP Compare EQ
SMPTypeCategory[NN_cmpltss] = 14;             // Scalar Single-FP Compare LT
SMPTypeCategory[NN_cmpless] = 14;             // Scalar Single-FP Compare LE
SMPTypeCategory[NN_cmpunordss] = 14;          // Scalar Single-FP Compare UNORD
SMPTypeCategory[NN_cmpneqss] = 14;            // Scalar Single-FP Compare NOT EQ
SMPTypeCategory[NN_cmpnltss] = 14;            // Scalar Single-FP Compare NOT LT
SMPTypeCategory[NN_cmpnless] = 14;            // Scalar Single-FP Compare NOT LE
SMPTypeCategory[NN_cmpordss] = 14;            // Scalar Single-FP Compare ORDERED

// AMD K7 instructions

// Revisit AMD if we port to it.
SMPTypeCategory[NN_pf2iw] = 15;               // Packed Floating-Point to Integer with Sign Extend
SMPTypeCategory[NN_pfnacc] = 15;              // Packed Floating-Point Negative Accumulate
SMPTypeCategory[NN_pfpnacc] = 15;             // Packed Floating-Point Mixed Positive-Negative Accumulate
SMPTypeCategory[NN_pi2fw] = 15;               // Packed 16-bit Integer to Floating-Point
SMPTypeCategory[NN_pswapd] = 15;              // Packed Swap Double Word

// Undocumented FP instructions (thanks to norbert.juffa@adm.com)

SMPTypeCategory[NN_fstp1] = 9;               // Alias of Store Real and Pop
SMPTypeCategory[NN_fcom2] = 1;               // Alias of Compare Real
SMPTypeCategory[NN_fcomp3] = 1;              // Alias of Compare Real and Pop
SMPTypeCategory[NN_fxch4] = 1;               // Alias of Exchange Registers
SMPTypeCategory[NN_fcomp5] = 1;              // Alias of Compare Real and Pop
SMPTypeCategory[NN_ffreep] = 1;              // Free Register and Pop
SMPTypeCategory[NN_fxch7] = 1;               // Alias of Exchange Registers
SMPTypeCategory[NN_fstp8] = 9;               // Alias of Store Real and Pop
SMPTypeCategory[NN_fstp9] = 9;               // Alias of Store Real and Pop

// Pentium 4 instructions

SMPTypeCategory[NN_addpd] = 14;               // Add Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_addsd] = 14;               // Add Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_andnpd] = 14;              // Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_andpd] = 14;               // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_clflush] = 1;             // Flush Cache Line
SMPTypeCategory[NN_cmppd] = 14;               // Compare Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_cmpsd] = 14;               // Compare Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_comisd] = 14;              // Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
SMPTypeCategory[NN_cvtdq2pd] = 14;            // Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_cvtdq2ps] = 14;            // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_cvtpd2dq] = 14;            // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_cvtpd2pi] = 14;            // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_cvtpd2ps] = 14;            // Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_cvtpi2pd] = 14;            // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_cvtps2dq] = 14;            // Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_cvtps2pd] = 14;            // Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_cvtsd2si] = 14;            // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
SMPTypeCategory[NN_cvtsd2ss] = 14;            // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
SMPTypeCategory[NN_cvtsi2sd] = 14;            // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_cvtss2sd] = 14;            // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_cvttpd2dq] = 14;           // Convert With Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_cvttpd2pi] = 14;           // Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_cvttps2dq] = 14;           // Convert With Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_cvttsd2si] = 14;           // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
SMPTypeCategory[NN_divpd] = 14;               // Divide Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_divsd] = 14;               // Divide Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_lfence] = 1;              // Load Fence
SMPTypeCategory[NN_maskmovdqu] = 13;          // Store Selected Bytes of Double Quadword  ** Infer dest is 'n'
SMPTypeCategory[NN_maxpd] = 14;               // Return Maximum Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_maxsd] = 14;               // Return Maximum Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_mfence] = 1;              // Memory Fence
SMPTypeCategory[NN_minpd] = 14;               // Return Minimum Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_minsd] = 14;               // Return Minimum Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_movapd] = 15;              // Move Aligned Packed Double-Precision Floating-Point Values  ** Infer dest is 'n'
SMPTypeCategory[NN_movdq2q] = 15;             // Move Quadword from XMM to MMX Register
SMPTypeCategory[NN_movdqa] = 15;              // Move Aligned Double Quadword  ** Infer dest is 'n'
SMPTypeCategory[NN_movdqu] = 15;              // Move Unaligned Double Quadword  ** Infer dest is 'n'
SMPTypeCategory[NN_movhpd] = 15;              // Move High Packed Double-Precision Floating-Point Values  ** Infer dest is 'n'
SMPTypeCategory[NN_movlpd] = 15;              // Move Low Packed Double-Precision Floating-Point Values  ** Infer dest is 'n'
SMPTypeCategory[NN_movmskpd] = 15;            // Extract Packed Double-Precision Floating-Point Sign Mask
SMPTypeCategory[NN_movntdq] = 13;             // Store Double Quadword Using Non-Temporal Hint
SMPTypeCategory[NN_movnti] = 13;              // Store Doubleword Using Non-Temporal Hint
SMPTypeCategory[NN_movntpd] = 13;             // Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
SMPTypeCategory[NN_movq2dq] = 1;             // Move Quadword from MMX to XMM Register
SMPTypeCategory[NN_movsd] = 15;               // Move Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_movupd] = 15;              // Move Unaligned Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_mulpd] = 14;               // Multiply Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_mulsd] = 14;               // Multiply Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_orpd] = 14;                // Bitwise Logical OR of Double-Precision Floating-Point Values
SMPTypeCategory[NN_paddq] = 14;               // Add Packed Quadword Integers
SMPTypeCategory[NN_pause] = 1;               // Spin Loop Hint
SMPTypeCategory[NN_pmuludq] = 14;             // Multiply Packed Unsigned Doubleword Integers
SMPTypeCategory[NN_pshufd] = 14;              // Shuffle Packed Doublewords
SMPTypeCategory[NN_pshufhw] = 14;             // Shuffle Packed High Words
SMPTypeCategory[NN_pshuflw] = 14;             // Shuffle Packed Low Words
SMPTypeCategory[NN_pslldq] = 14;              // Shift Double Quadword Left Logical
SMPTypeCategory[NN_psrldq] = 14;              // Shift Double Quadword Right Logical
SMPTypeCategory[NN_psubq] = 14;               // Subtract Packed Quadword Integers
SMPTypeCategory[NN_punpckhqdq] = 14;          // Unpack High Data
SMPTypeCategory[NN_punpcklqdq] = 14;          // Unpack Low Data
SMPTypeCategory[NN_shufpd] = 14;              // Shuffle Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_sqrtpd] = 1;              // Compute Square Roots of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_sqrtsd] = 14;              // Compute Square Rootof Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_subpd] = 14;               // Subtract Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_subsd] = 14;               // Subtract Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_ucomisd] = 14;             // Unordered Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
SMPTypeCategory[NN_unpckhpd] = 14;            // Unpack and Interleave High Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_unpcklpd] = 14;            // Unpack and Interleave Low Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_xorpd] = 14;               // Bitwise Logical OR of Double-Precision Floating-Point Values


// AMD syscall/sysret instructions  NOTE: not AMD, found in Intel manual

SMPTypeCategory[NN_syscall] = 1;             // Low latency system call
SMPTypeCategory[NN_sysret] = 1;              // Return from system call

// AMD64 instructions    NOTE: not AMD, found in Intel manual

SMPTypeCategory[NN_swapgs] = 1;              // Exchange GS base with KernelGSBase MSR

// New Pentium instructions (SSE3)

SMPTypeCategory[NN_movddup] = 14;             // Move One Double-FP and Duplicate
SMPTypeCategory[NN_movshdup] = 14;            // Move Packed Single-FP High and Duplicate
SMPTypeCategory[NN_movsldup] = 14;            // Move Packed Single-FP Low and Duplicate

// Missing AMD64 instructions  NOTE: also found in Intel manual

SMPTypeCategory[NN_movsxd] = 2;              // Move with Sign-Extend Doubleword
SMPTypeCategory[NN_cmpxchg16b] = 0;          // Compare and Exchange 16 Bytes

// SSE3 instructions

SMPTypeCategory[NN_addsubpd] = 14;            // Add /Sub packed DP FP numbers
SMPTypeCategory[NN_addsubps] = 14;            // Add /Sub packed SP FP numbers
SMPTypeCategory[NN_haddpd] = 14;              // Add horizontally packed DP FP numbers
SMPTypeCategory[NN_haddps] = 14;              // Add horizontally packed SP FP numbers
SMPTypeCategory[NN_hsubpd] = 14;              // Sub horizontally packed DP FP numbers
SMPTypeCategory[NN_hsubps] = 14;              // Sub horizontally packed SP FP numbers
SMPTypeCategory[NN_monitor] = 1;             // Set up a linear address range to be monitored by hardware
SMPTypeCategory[NN_mwait] = 1;               // Wait until write-back store performed within the range specified by the MONITOR instruction
SMPTypeCategory[NN_fisttp] = 13;              // Store ST in intXX (chop) and pop
SMPTypeCategory[NN_lddqu] = 14;               // Load unaligned integer 128-bit

// SSSE3 instructions

SMPTypeCategory[NN_psignb] = 14;              // Packed SIGN Byte
SMPTypeCategory[NN_psignw] = 14;              // Packed SIGN Word
SMPTypeCategory[NN_psignd] = 14;              // Packed SIGN Doubleword
SMPTypeCategory[NN_pshufb] = 14;              // Packed Shuffle Bytes
SMPTypeCategory[NN_pmulhrsw] = 14;            // Packed Multiply High with Round and Scale
SMPTypeCategory[NN_pmaddubsw] = 14;           // Multiply and Add Packed Signed and Unsigned Bytes
SMPTypeCategory[NN_phsubsw] = 14;             // Packed Horizontal Subtract and Saturate
SMPTypeCategory[NN_phaddsw] = 14;             // Packed Horizontal Add and Saturate
SMPTypeCategory[NN_phaddw] = 14;              // Packed Horizontal Add Word
SMPTypeCategory[NN_phaddd] = 14;              // Packed Horizontal Add Doubleword
SMPTypeCategory[NN_phsubw] = 14;              // Packed Horizontal Subtract Word
SMPTypeCategory[NN_phsubd] = 14;              // Packed Horizontal Subtract Doubleword
SMPTypeCategory[NN_palignr] = 15;             // Packed Align Right
SMPTypeCategory[NN_pabsb] = 14;               // Packed Absolute Value Byte
SMPTypeCategory[NN_pabsw] = 14;               // Packed Absolute Value Word
SMPTypeCategory[NN_pabsd] = 14;               // Packed Absolute Value Doubleword

// VMX instructions

SMPTypeCategory[NN_vmcall] = 1;              // Call to VM Monitor
SMPTypeCategory[NN_vmclear] = 0;             // Clear Virtual Machine Control Structure
SMPTypeCategory[NN_vmlaunch] = 1;            // Launch Virtual Machine
SMPTypeCategory[NN_vmresume] = 1;            // Resume Virtual Machine
SMPTypeCategory[NN_vmptrld] = 6;             // Load Pointer to Virtual Machine Control Structure
SMPTypeCategory[NN_vmptrst] = 0;             // Store Pointer to Virtual Machine Control Structure
SMPTypeCategory[NN_vmread] = 0;              // Read Field from Virtual Machine Control Structure
SMPTypeCategory[NN_vmwrite] = 0;             // Write Field from Virtual Machine Control Structure
SMPTypeCategory[NN_vmxoff] = 1;              // Leave VMX Operation
SMPTypeCategory[NN_vmxon] = 1;               // Enter VMX Operation

#if 599 < IDA_SDK_VERSION

SMPTypeCategory[NN_ud2] = 1;                 // Undefined Instruction

// Added with x86-64

SMPTypeCategory[NN_rdtscp] = 8;              // Read Time-Stamp Counter and Processor ID

// Geode LX 3DNow! extensions

SMPTypeCategory[NN_pfrcpv] = 1;              // Reciprocal Approximation for a Pair of 32-bit Floats
SMPTypeCategory[NN_pfrsqrtv] = 1;            // Reciprocal Square Root Approximation for a Pair of 32-bit Floats

// SSE2 pseudoinstructions

SMPTypeCategory[NN_cmpeqpd] = 1;             // Packed Double-FP Compare EQ
SMPTypeCategory[NN_cmpltpd] = 1;             // Packed Double-FP Compare LT
SMPTypeCategory[NN_cmplepd] = 1;             // Packed Double-FP Compare LE
SMPTypeCategory[NN_cmpunordpd] = 1;          // Packed Double-FP Compare UNORD
SMPTypeCategory[NN_cmpneqpd] = 1;            // Packed Double-FP Compare NOT EQ
SMPTypeCategory[NN_cmpnltpd] = 1;            // Packed Double-FP Compare NOT LT
SMPTypeCategory[NN_cmpnlepd] = 1;            // Packed Double-FP Compare NOT LE
SMPTypeCategory[NN_cmpordpd] = 1;            // Packed Double-FP Compare ORDERED
SMPTypeCategory[NN_cmpeqsd] = 1;             // Scalar Double-FP Compare EQ
SMPTypeCategory[NN_cmpltsd] = 1;             // Scalar Double-FP Compare LT
SMPTypeCategory[NN_cmplesd] = 1;             // Scalar Double-FP Compare LE
SMPTypeCategory[NN_cmpunordsd] = 1;          // Scalar Double-FP Compare UNORD
SMPTypeCategory[NN_cmpneqsd] = 1;            // Scalar Double-FP Compare NOT EQ
SMPTypeCategory[NN_cmpnltsd] = 1;            // Scalar Double-FP Compare NOT LT
SMPTypeCategory[NN_cmpnlesd] = 1;            // Scalar Double-FP Compare NOT LE
SMPTypeCategory[NN_cmpordsd] = 1;            // Scalar Double-FP Compare ORDERED

// SSSE4.1 instructions

SMPTypeCategory[NN_blendpd] = 14;             // Blend Packed Double Precision Floating-Point Values
SMPTypeCategory[NN_blendps] = 14;             // Blend Packed Single Precision Floating-Point Values
SMPTypeCategory[NN_blendvpd] = 14;            // Variable Blend Packed Double Precision Floating-Point Values
SMPTypeCategory[NN_blendvps] = 14;            // Variable Blend Packed Single Precision Floating-Point Values
SMPTypeCategory[NN_dppd] = 14;                // Dot Product of Packed Double Precision Floating-Point Values
SMPTypeCategory[NN_dpps] = 14;                // Dot Product of Packed Single Precision Floating-Point Values
SMPTypeCategory[NN_extractps] = 2;            // Extract Packed Single Precision Floating-Point Value
SMPTypeCategory[NN_insertps] = 14;            // Insert Packed Single Precision Floating-Point Value
SMPTypeCategory[NN_movntdqa] = 0;             // Load Double Quadword Non-Temporal Aligned Hint
SMPTypeCategory[NN_mpsadbw] = 1;              // Compute Multiple Packed Sums of Absolute Difference
SMPTypeCategory[NN_packusdw] = 14;            // Pack with Unsigned Saturation
SMPTypeCategory[NN_pblendvb] = 14;            // Variable Blend Packed Bytes