SMPDataFlowAnalysis.cpp

SMPTypeCategory[NN_f2xm1] = 1;               // 2^x - 1
SMPTypeCategory[NN_fyl2x] = 1;               // Y * lg2(X)
SMPTypeCategory[NN_fyl2xp1] = 1;             // Y * lg2(X+1)
SMPTypeCategory[NN_fldz] = 1;                // Load +0.0
SMPTypeCategory[NN_fld1] = 1;                // Load +1.0
SMPTypeCategory[NN_fldpi] = 1;               // Load PI=3.14...
SMPTypeCategory[NN_fldl2t] = 1;              // Load lg2(10)
SMPTypeCategory[NN_fldl2e] = 1;              // Load lg2(e)
SMPTypeCategory[NN_fldlg2] = 1;              // Load lg10(2)
SMPTypeCategory[NN_fldln2] = 1;              // Load ln(2)
SMPTypeCategory[NN_finit] = 1;               // Initialize Processor
SMPTypeCategory[NN_fninit] = 1;              // Initialize Processor (no wait)
SMPTypeCategory[NN_fsetpm] = 1;              // Set Protected Mode
SMPTypeCategory[NN_fldcw] = 14;               // Load Control Word
SMPTypeCategory[NN_fstcw] = 13;               // Store Control Word
SMPTypeCategory[NN_fnstcw] = 13;              // Store Control Word (no wait)
SMPTypeCategory[NN_fstsw] = 2;               // Store Status Word to memory or AX
SMPTypeCategory[NN_fnstsw] = 2;              // Store Status Word (no wait) to memory or AX
SMPTypeCategory[NN_fclex] = 1;               // Clear Exceptions
SMPTypeCategory[NN_fnclex] = 1;              // Clear Exceptions (no wait)
SMPTypeCategory[NN_fstenv] = 13;              // Store Environment
SMPTypeCategory[NN_fnstenv] = 13;             // Store Environment (no wait)
SMPTypeCategory[NN_fldenv] = 14;              // Load Environment
SMPTypeCategory[NN_fsave] = 13;               // Save State
SMPTypeCategory[NN_fnsave] = 13;              // Save State (no wait)
SMPTypeCategory[NN_frstor] = 14;              // Restore State    **  infer src is 'n'
SMPTypeCategory[NN_fincstp] = 1;             // Increment Stack Pointer
SMPTypeCategory[NN_fdecstp] = 1;             // Decrement Stack Pointer
SMPTypeCategory[NN_ffree] = 1;               // Free Register
SMPTypeCategory[NN_fnop] = 1;                // No Operation
SMPTypeCategory[NN_feni] = 1;                // (8087 only)
SMPTypeCategory[NN_fneni] = 1;               // (no wait) (8087 only)
SMPTypeCategory[NN_fdisi] = 1;               // (8087 only)
SMPTypeCategory[NN_fndisi] = 1;              // (no wait) (8087 only)

//
//      80387 instructions
//

SMPTypeCategory[NN_fprem1] = 1;              // Partial Remainder ( < half )
SMPTypeCategory[NN_fsincos] = 1;             // t<-cos(st); st<-sin(st); push t
SMPTypeCategory[NN_fsin] = 1;                // Sine
SMPTypeCategory[NN_fcos] = 1;                // Cosine
SMPTypeCategory[NN_fucom] = 1;               // Compare Unordered Real
SMPTypeCategory[NN_fucomp] = 1;              // Compare Unordered Real and Pop
SMPTypeCategory[NN_fucompp] = 1;             // Compare Unordered Real and Pop Twice

//
//      Instructions added 28.02.96
//

SMPTypeCategory[NN_setalc] = 2;              // Set AL to Carry Flag     **
SMPTypeCategory[NN_svdc] = 0;                // Save Register and Descriptor
SMPTypeCategory[NN_rsdc] = 0;                // Restore Register and Descriptor
SMPTypeCategory[NN_svldt] = 0;               // Save LDTR and Descriptor
SMPTypeCategory[NN_rsldt] = 0;               // Restore LDTR and Descriptor
SMPTypeCategory[NN_svts] = 1;                // Save TR and Descriptor
SMPTypeCategory[NN_rsts] = 1;                // Restore TR and Descriptor
SMPTypeCategory[NN_icebp] = 1;               // ICE Break Point
SMPTypeCategory[NN_loadall] = 0;             // Load the entire CPU state from ES:EDI ???

//
//      MMX instructions
//

SMPTypeCategory[NN_emms] = 1;                // Empty MMX state
SMPTypeCategory[NN_movd] = 15;                // Move 32 bits
SMPTypeCategory[NN_movq] = 15;                // Move 64 bits
SMPTypeCategory[NN_packsswb] = 14;            // Pack with Signed Saturation (Word->Byte)
SMPTypeCategory[NN_packssdw] = 14;            // Pack with Signed Saturation (Dword->Word)
SMPTypeCategory[NN_packuswb] = 14;            // Pack with Unsigned Saturation (Word->Byte)
SMPTypeCategory[NN_paddb] = 14;               // Packed Add Byte
SMPTypeCategory[NN_paddw] = 14;               // Packed Add Word
SMPTypeCategory[NN_paddd] = 14;               // Packed Add Dword
SMPTypeCategory[NN_paddsb] = 14;              // Packed Add with Saturation (Byte)
SMPTypeCategory[NN_paddsw] = 14;              // Packed Add with Saturation (Word)
SMPTypeCategory[NN_paddusb] = 14;             // Packed Add Unsigned with Saturation (Byte)
SMPTypeCategory[NN_paddusw] = 14;             // Packed Add Unsigned with Saturation (Word)
SMPTypeCategory[NN_pand] = 14;                // Bitwise Logical And
SMPTypeCategory[NN_pandn] = 14;               // Bitwise Logical And Not
SMPTypeCategory[NN_pcmpeqb] = 14;             // Packed Compare for Equal (Byte)
SMPTypeCategory[NN_pcmpeqw] = 14;             // Packed Compare for Equal (Word)
SMPTypeCategory[NN_pcmpeqd] = 14;             // Packed Compare for Equal (Dword)
SMPTypeCategory[NN_pcmpgtb] = 14;             // Packed Compare for Greater Than (Byte)
SMPTypeCategory[NN_pcmpgtw] = 14;             // Packed Compare for Greater Than (Word)
SMPTypeCategory[NN_pcmpgtd] = 14;             // Packed Compare for Greater Than (Dword)
SMPTypeCategory[NN_pmaddwd] = 14;             // Packed Multiply and Add
SMPTypeCategory[NN_pmulhw] = 14;              // Packed Multiply High
SMPTypeCategory[NN_pmullw] = 14;              // Packed Multiply Low
SMPTypeCategory[NN_por] = 14;                 // Bitwise Logical Or
SMPTypeCategory[NN_psllw] = 14;               // Packed Shift Left Logical (Word)
SMPTypeCategory[NN_pslld] = 14;               // Packed Shift Left Logical (Dword)
SMPTypeCategory[NN_psllq] = 14;               // Packed Shift Left Logical (Qword)
SMPTypeCategory[NN_psraw] = 14;               // Packed Shift Right Arithmetic (Word)
SMPTypeCategory[NN_psrad] = 14;               // Packed Shift Right Arithmetic (Dword)
SMPTypeCategory[NN_psrlw] = 14;               // Packed Shift Right Logical (Word)
SMPTypeCategory[NN_psrld] = 14;               // Packed Shift Right Logical (Dword)
SMPTypeCategory[NN_psrlq] = 14;               // Packed Shift Right Logical (Qword)
SMPTypeCategory[NN_psubb] = 14;               // Packed Subtract Byte
SMPTypeCategory[NN_psubw] = 14;               // Packed Subtract Word
SMPTypeCategory[NN_psubd] = 14;               // Packed Subtract Dword
SMPTypeCategory[NN_psubsb] = 14;              // Packed Subtract with Saturation (Byte)
SMPTypeCategory[NN_psubsw] = 14;              // Packed Subtract with Saturation (Word)
SMPTypeCategory[NN_psubusb] = 14;             // Packed Subtract Unsigned with Saturation (Byte)
SMPTypeCategory[NN_psubusw] = 14;             // Packed Subtract Unsigned with Saturation (Word)
SMPTypeCategory[NN_punpckhbw] = 14;           // Unpack High Packed Data (Byte->Word)
SMPTypeCategory[NN_punpckhwd] = 14;           // Unpack High Packed Data (Word->Dword)
SMPTypeCategory[NN_punpckhdq] = 14;           // Unpack High Packed Data (Dword->Qword)
SMPTypeCategory[NN_punpcklbw] = 14;           // Unpack Low Packed Data (Byte->Word)
SMPTypeCategory[NN_punpcklwd] = 14;           // Unpack Low Packed Data (Word->Dword)
SMPTypeCategory[NN_punpckldq] = 14;           // Unpack Low Packed Data (Dword->Qword)
SMPTypeCategory[NN_pxor] = 14;                // Bitwise Logical Exclusive Or

//
//      Undocumented Deschutes processor instructions
//

SMPTypeCategory[NN_fxsave] = 1;              // Fast save FP context            ** to where?
SMPTypeCategory[NN_fxrstor] = 1;             // Fast restore FP context         ** from where?

//      Pentium II instructions

SMPTypeCategory[NN_sysenter] = 1;            // Fast Transition to System Call Entry Point
SMPTypeCategory[NN_sysexit] = 1;             // Fast Transition from System Call Entry Point

//      3DNow! instructions

SMPTypeCategory[NN_pavgusb] = 14;             // Packed 8-bit Unsigned Integer Averaging
SMPTypeCategory[NN_pfadd] = 14;               // Packed Floating-Point Addition
SMPTypeCategory[NN_pfsub] = 14;               // Packed Floating-Point Subtraction
SMPTypeCategory[NN_pfsubr] = 14;              // Packed Floating-Point Reverse Subtraction
SMPTypeCategory[NN_pfacc] = 14;               // Packed Floating-Point Accumulate
SMPTypeCategory[NN_pfcmpge] = 14;             // Packed Floating-Point Comparison, Greater or Equal
SMPTypeCategory[NN_pfcmpgt] = 14;             // Packed Floating-Point Comparison, Greater
SMPTypeCategory[NN_pfcmpeq] = 14;             // Packed Floating-Point Comparison, Equal
SMPTypeCategory[NN_pfmin] = 14;               // Packed Floating-Point Minimum
SMPTypeCategory[NN_pfmax] = 14;               // Packed Floating-Point Maximum
SMPTypeCategory[NN_pi2fd] = 14;               // Packed 32-bit Integer to Floating-Point
SMPTypeCategory[NN_pf2id] = 14;               // Packed Floating-Point to 32-bit Integer
SMPTypeCategory[NN_pfrcp] = 14;               // Packed Floating-Point Reciprocal Approximation
SMPTypeCategory[NN_pfrsqrt] = 14;             // Packed Floating-Point Reciprocal Square Root Approximation
SMPTypeCategory[NN_pfmul] = 14;               // Packed Floating-Point Multiplication
SMPTypeCategory[NN_pfrcpit1] = 14;            // Packed Floating-Point Reciprocal First Iteration Step
SMPTypeCategory[NN_pfrsqit1] = 14;            // Packed Floating-Point Reciprocal Square Root First Iteration Step
SMPTypeCategory[NN_pfrcpit2] = 14;            // Packed Floating-Point Reciprocal Second Iteration Step
SMPTypeCategory[NN_pmulhrw] = 14;             // Packed Floating-Point 16-bit Integer Multiply with rounding
SMPTypeCategory[NN_femms] = 1;               // Faster entry/exit of the MMX or floating-point state
SMPTypeCategory[NN_prefetch] = 1;            // Prefetch at least a 32-byte line into L1 data cache
SMPTypeCategory[NN_prefetchw] = 1;           // Prefetch processor cache line into L1 data cache (mark as modified)


//      Pentium III instructions

SMPTypeCategory[NN_addps] = 14;               // Packed Single-FP Add
SMPTypeCategory[NN_addss] = 14;               // Scalar Single-FP Add
SMPTypeCategory[NN_andnps] = 14;              // Bitwise Logical And Not for Single-FP
SMPTypeCategory[NN_andps] = 14;               // Bitwise Logical And for Single-FP
SMPTypeCategory[NN_cmpps] = 14;               // Packed Single-FP Compare
SMPTypeCategory[NN_cmpss] = 14;               // Scalar Single-FP Compare
SMPTypeCategory[NN_comiss] = 14;              // Scalar Ordered Single-FP Compare and Set EFLAGS
SMPTypeCategory[NN_cvtpi2ps] = 14;            // Packed signed INT32 to Packed Single-FP conversion
SMPTypeCategory[NN_cvtps2pi] = 14;            // Packed Single-FP to Packed INT32 conversion
SMPTypeCategory[NN_cvtsi2ss] = 14;            // Scalar signed INT32 to Single-FP conversion
SMPTypeCategory[NN_cvtss2si] = 14;            // Scalar Single-FP to signed INT32 conversion
SMPTypeCategory[NN_cvttps2pi] = 14;           // Packed Single-FP to Packed INT32 conversion (truncate)
SMPTypeCategory[NN_cvttss2si] = 14;           // Scalar Single-FP to signed INT32 conversion (truncate)
SMPTypeCategory[NN_divps] = 14;               // Packed Single-FP Divide
SMPTypeCategory[NN_divss] = 14;               // Scalar Single-FP Divide
SMPTypeCategory[NN_ldmxcsr] = 14;             // Load Streaming SIMD Extensions Technology Control/Status Register
SMPTypeCategory[NN_maxps] = 14;               // Packed Single-FP Maximum
SMPTypeCategory[NN_maxss] = 14;               // Scalar Single-FP Maximum
SMPTypeCategory[NN_minps] = 14;               // Packed Single-FP Minimum
SMPTypeCategory[NN_minss] = 14;               // Scalar Single-FP Minimum
SMPTypeCategory[NN_movaps] = 15;              // Move Aligned Four Packed Single-FP  ** infer memsrc 'n'?
SMPTypeCategory[NN_movhlps] = 15;             // Move High to Low Packed Single-FP
SMPTypeCategory[NN_movhps] = 15;              // Move High Packed Single-FP
SMPTypeCategory[NN_movlhps] = 15;             // Move Low to High Packed Single-FP
SMPTypeCategory[NN_movlps] = 15;              // Move Low Packed Single-FP
SMPTypeCategory[NN_movmskps] = 15;            // Move Mask to Register
SMPTypeCategory[NN_movss] = 15;               // Move Scalar Single-FP
SMPTypeCategory[NN_movups] = 15;              // Move Unaligned Four Packed Single-FP
SMPTypeCategory[NN_mulps] = 14;               // Packed Single-FP Multiply
SMPTypeCategory[NN_mulss] = 14;               // Scalar Single-FP Multiply
SMPTypeCategory[NN_orps] = 14;                // Bitwise Logical OR for Single-FP Data
SMPTypeCategory[NN_rcpps] = 14;               // Packed Single-FP Reciprocal
SMPTypeCategory[NN_rcpss] = 14;               // Scalar Single-FP Reciprocal
SMPTypeCategory[NN_rsqrtps] = 14;             // Packed Single-FP Square Root Reciprocal
SMPTypeCategory[NN_rsqrtss] = 14;             // Scalar Single-FP Square Root Reciprocal
SMPTypeCategory[NN_shufps] = 14;              // Shuffle Single-FP
SMPTypeCategory[NN_sqrtps] = 14;              // Packed Single-FP Square Root
SMPTypeCategory[NN_sqrtss] = 14;              // Scalar Single-FP Square Root
SMPTypeCategory[NN_stmxcsr] = 15;             // Store Streaming SIMD Extensions Technology Control/Status Register    ** Infer dest is 'n'
SMPTypeCategory[NN_subps] = 14;               // Packed Single-FP Subtract
SMPTypeCategory[NN_subss] = 14;               // Scalar Single-FP Subtract
SMPTypeCategory[NN_ucomiss] = 14;             // Scalar Unordered Single-FP Compare and Set EFLAGS
SMPTypeCategory[NN_unpckhps] = 14;            // Unpack High Packed Single-FP Data
SMPTypeCategory[NN_unpcklps] = 14;            // Unpack Low Packed Single-FP Data
SMPTypeCategory[NN_xorps] = 14;               // Bitwise Logical XOR for Single-FP Data
SMPTypeCategory[NN_pavgb] = 14;               // Packed Average (Byte)
SMPTypeCategory[NN_pavgw] = 14;               // Packed Average (Word)
SMPTypeCategory[NN_pextrw] = 2;               // Extract Word
SMPTypeCategory[NN_pinsrw] = 14;              // Insert Word
SMPTypeCategory[NN_pmaxsw] = 14;              // Packed Signed Integer Word Maximum
SMPTypeCategory[NN_pmaxub] = 14;              // Packed Unsigned Integer Byte Maximum
SMPTypeCategory[NN_pminsw] = 14;              // Packed Signed Integer Word Minimum
SMPTypeCategory[NN_pminub] = 14;              // Packed Unsigned Integer Byte Minimum
SMPTypeCategory[NN_pmovmskb] = 2;             // Move Byte Mask to Integer
SMPTypeCategory[NN_pmulhuw] = 14;             // Packed Multiply High Unsigned
SMPTypeCategory[NN_psadbw] = 14;              // Packed Sum of Absolute Differences
SMPTypeCategory[NN_pshufw] = 14;              // Packed Shuffle Word
SMPTypeCategory[NN_maskmovq] = 15;            // Byte Mask write   ** Infer dest is 'n'
SMPTypeCategory[NN_movntps] = 13;             // Move Aligned Four Packed Single-FP Non Temporal  * infer dest is 'n'
SMPTypeCategory[NN_movntq] = 13;              // Move 64 Bits Non Temporal    ** Infer dest is 'n'
SMPTypeCategory[NN_prefetcht0] = 1;          // Prefetch to all cache levels
SMPTypeCategory[NN_prefetcht1] = 1;          // Prefetch to all cache levels
SMPTypeCategory[NN_prefetcht2] = 1;          // Prefetch to L2 cache
SMPTypeCategory[NN_prefetchnta] = 1;         // Prefetch to L1 cache
SMPTypeCategory[NN_sfence] = 1;              // Store Fence

// Pentium III Pseudo instructions

SMPTypeCategory[NN_cmpeqps] = 14;             // Packed Single-FP Compare EQ
SMPTypeCategory[NN_cmpltps] = 14;             // Packed Single-FP Compare LT
SMPTypeCategory[NN_cmpleps] = 14;             // Packed Single-FP Compare LE
SMPTypeCategory[NN_cmpunordps] = 14;          // Packed Single-FP Compare UNORD
SMPTypeCategory[NN_cmpneqps] = 14;            // Packed Single-FP Compare NOT EQ
SMPTypeCategory[NN_cmpnltps] = 14;            // Packed Single-FP Compare NOT LT
SMPTypeCategory[NN_cmpnleps] = 14;            // Packed Single-FP Compare NOT LE
SMPTypeCategory[NN_cmpordps] = 14;            // Packed Single-FP Compare ORDERED
SMPTypeCategory[NN_cmpeqss] = 14;             // Scalar Single-FP Compare EQ
SMPTypeCategory[NN_cmpltss] = 14;             // Scalar Single-FP Compare LT
SMPTypeCategory[NN_cmpless] = 14;             // Scalar Single-FP Compare LE
SMPTypeCategory[NN_cmpunordss] = 14;          // Scalar Single-FP Compare UNORD
SMPTypeCategory[NN_cmpneqss] = 14;            // Scalar Single-FP Compare NOT EQ
SMPTypeCategory[NN_cmpnltss] = 14;            // Scalar Single-FP Compare NOT LT
SMPTypeCategory[NN_cmpnless] = 14;            // Scalar Single-FP Compare NOT LE
SMPTypeCategory[NN_cmpordss] = 14;            // Scalar Single-FP Compare ORDERED

// AMD K7 instructions

// Revisit AMD if we port to it.
SMPTypeCategory[NN_pf2iw] = 15;               // Packed Floating-Point to Integer with Sign Extend
SMPTypeCategory[NN_pfnacc] = 15;              // Packed Floating-Point Negative Accumulate
SMPTypeCategory[NN_pfpnacc] = 15;             // Packed Floating-Point Mixed Positive-Negative Accumulate
SMPTypeCategory[NN_pi2fw] = 15;               // Packed 16-bit Integer to Floating-Point
SMPTypeCategory[NN_pswapd] = 15;              // Packed Swap Double Word

// Undocumented FP instructions (thanks to norbert.juffa@adm.com)

SMPTypeCategory[NN_fstp1] = 9;               // Alias of Store Real and Pop
SMPTypeCategory[NN_fcom2] = 1;               // Alias of Compare Real
SMPTypeCategory[NN_fcomp3] = 1;              // Alias of Compare Real and Pop
SMPTypeCategory[NN_fxch4] = 1;               // Alias of Exchange Registers
SMPTypeCategory[NN_fcomp5] = 1;              // Alias of Compare Real and Pop
SMPTypeCategory[NN_ffreep] = 1;              // Free Register and Pop
SMPTypeCategory[NN_fxch7] = 1;               // Alias of Exchange Registers
SMPTypeCategory[NN_fstp8] = 9;               // Alias of Store Real and Pop
SMPTypeCategory[NN_fstp9] = 9;               // Alias of Store Real and Pop

// Pentium 4 instructions

SMPTypeCategory[NN_addpd] = 14;               // Add Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_addsd] = 14;               // Add Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_andnpd] = 14;              // Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_andpd] = 14;               // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_clflush] = 1;             // Flush Cache Line
SMPTypeCategory[NN_cmppd] = 14;               // Compare Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_cmpsd] = 14;               // Compare Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_comisd] = 14;              // Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
SMPTypeCategory[NN_cvtdq2pd] = 14;            // Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_cvtdq2ps] = 14;            // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_cvtpd2dq] = 14;            // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_cvtpd2pi] = 14;            // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_cvtpd2ps] = 14;            // Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
SMPTypeCategory[NN_cvtpi2pd] = 14;            // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_cvtps2dq] = 14;            // Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_cvtps2pd] = 14;            // Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_cvtsd2si] = 14;            // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
SMPTypeCategory[NN_cvtsd2ss] = 14;            // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
SMPTypeCategory[NN_cvtsi2sd] = 14;            // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_cvtss2sd] = 14;            // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_cvttpd2dq] = 14;           // Convert With Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_cvttpd2pi] = 14;           // Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_cvttps2dq] = 14;           // Convert With Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
SMPTypeCategory[NN_cvttsd2si] = 14;           // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
SMPTypeCategory[NN_divpd] = 14;               // Divide Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_divsd] = 14;               // Divide Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_lfence] = 1;              // Load Fence
SMPTypeCategory[NN_maskmovdqu] = 13;          // Store Selected Bytes of Double Quadword  ** Infer dest is 'n'
SMPTypeCategory[NN_maxpd] = 14;               // Return Maximum Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_maxsd] = 14;               // Return Maximum Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_mfence] = 1;              // Memory Fence
SMPTypeCategory[NN_minpd] = 14;               // Return Minimum Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_minsd] = 14;               // Return Minimum Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_movapd] = 15;              // Move Aligned Packed Double-Precision Floating-Point Values  ** Infer dest is 'n'
SMPTypeCategory[NN_movdq2q] = 15;             // Move Quadword from XMM to MMX Register
SMPTypeCategory[NN_movdqa] = 15;              // Move Aligned Double Quadword  ** Infer dest is 'n'
SMPTypeCategory[NN_movdqu] = 15;              // Move Unaligned Double Quadword  ** Infer dest is 'n'
SMPTypeCategory[NN_movhpd] = 15;              // Move High Packed Double-Precision Floating-Point Values  ** Infer dest is 'n'
SMPTypeCategory[NN_movlpd] = 15;              // Move Low Packed Double-Precision Floating-Point Values  ** Infer dest is 'n'
SMPTypeCategory[NN_movmskpd] = 15;            // Extract Packed Double-Precision Floating-Point Sign Mask
SMPTypeCategory[NN_movntdq] = 13;             // Store Double Quadword Using Non-Temporal Hint
SMPTypeCategory[NN_movnti] = 13;              // Store Doubleword Using Non-Temporal Hint
SMPTypeCategory[NN_movntpd] = 13;             // Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
SMPTypeCategory[NN_movq2dq] = 1;             // Move Quadword from MMX to XMM Register
SMPTypeCategory[NN_movsd] = 15;               // Move Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_movupd] = 15;              // Move Unaligned Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_mulpd] = 14;               // Multiply Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_mulsd] = 14;               // Multiply Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_orpd] = 14;                // Bitwise Logical OR of Double-Precision Floating-Point Values
SMPTypeCategory[NN_paddq] = 14;               // Add Packed Quadword Integers
SMPTypeCategory[NN_pause] = 1;               // Spin Loop Hint
SMPTypeCategory[NN_pmuludq] = 14;             // Multiply Packed Unsigned Doubleword Integers
SMPTypeCategory[NN_pshufd] = 14;              // Shuffle Packed Doublewords
SMPTypeCategory[NN_pshufhw] = 14;             // Shuffle Packed High Words
SMPTypeCategory[NN_pshuflw] = 14;             // Shuffle Packed Low Words
SMPTypeCategory[NN_pslldq] = 14;              // Shift Double Quadword Left Logical
SMPTypeCategory[NN_psrldq] = 14;              // Shift Double Quadword Right Logical
SMPTypeCategory[NN_psubq] = 14;               // Subtract Packed Quadword Integers
SMPTypeCategory[NN_punpckhqdq] = 14;          // Unpack High Data
SMPTypeCategory[NN_punpcklqdq] = 14;          // Unpack Low Data
SMPTypeCategory[NN_shufpd] = 14;              // Shuffle Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_sqrtpd] = 1;              // Compute Square Roots of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_sqrtsd] = 14;              // Compute Square Rootof Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_subpd] = 14;               // Subtract Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_subsd] = 14;               // Subtract Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_ucomisd] = 14;             // Unordered Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
SMPTypeCategory[NN_unpckhpd] = 14;            // Unpack and Interleave High Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_unpcklpd] = 14;            // Unpack and Interleave Low Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_xorpd] = 14;               // Bitwise Logical OR of Double-Precision Floating-Point Values


// AMD syscall/sysret instructions  NOTE: not AMD, found in Intel manual

SMPTypeCategory[NN_syscall] = 1;             // Low latency system call
SMPTypeCategory[NN_sysret] = 1;              // Return from system call

// AMD64 instructions    NOTE: not AMD, found in Intel manual

SMPTypeCategory[NN_swapgs] = 1;              // Exchange GS base with KernelGSBase MSR

// New Pentium instructions (SSE3)

SMPTypeCategory[NN_movddup] = 14;             // Move One Double-FP and Duplicate
SMPTypeCategory[NN_movshdup] = 14;            // Move Packed Single-FP High and Duplicate
SMPTypeCategory[NN_movsldup] = 14;            // Move Packed Single-FP Low and Duplicate

// Missing AMD64 instructions  NOTE: also found in Intel manual

SMPTypeCategory[NN_movsxd] = 2;              // Move with Sign-Extend Doubleword
SMPTypeCategory[NN_cmpxchg16b] = 0;          // Compare and Exchange 16 Bytes

// SSE3 instructions

SMPTypeCategory[NN_addsubpd] = 14;            // Add /Sub packed DP FP numbers
SMPTypeCategory[NN_addsubps] = 14;            // Add /Sub packed SP FP numbers
SMPTypeCategory[NN_haddpd] = 14;              // Add horizontally packed DP FP numbers
SMPTypeCategory[NN_haddps] = 14;              // Add horizontally packed SP FP numbers
SMPTypeCategory[NN_hsubpd] = 14;              // Sub horizontally packed DP FP numbers
SMPTypeCategory[NN_hsubps] = 14;              // Sub horizontally packed SP FP numbers
SMPTypeCategory[NN_monitor] = 1;             // Set up a linear address range to be monitored by hardware
SMPTypeCategory[NN_mwait] = 1;               // Wait until write-back store performed within the range specified by the MONITOR instruction
SMPTypeCategory[NN_fisttp] = 13;              // Store ST in intXX (chop) and pop
SMPTypeCategory[NN_lddqu] = 14;               // Load unaligned integer 128-bit

// SSSE3 instructions

SMPTypeCategory[NN_psignb] = 14;              // Packed SIGN Byte
SMPTypeCategory[NN_psignw] = 14;              // Packed SIGN Word
SMPTypeCategory[NN_psignd] = 14;              // Packed SIGN Doubleword
SMPTypeCategory[NN_pshufb] = 14;              // Packed Shuffle Bytes
SMPTypeCategory[NN_pmulhrsw] = 14;            // Packed Multiply High with Round and Scale
SMPTypeCategory[NN_pmaddubsw] = 14;           // Multiply and Add Packed Signed and Unsigned Bytes
SMPTypeCategory[NN_phsubsw] = 14;             // Packed Horizontal Subtract and Saturate
SMPTypeCategory[NN_phaddsw] = 14;             // Packed Horizontal Add and Saturate
SMPTypeCategory[NN_phaddw] = 14;              // Packed Horizontal Add Word
SMPTypeCategory[NN_phaddd] = 14;              // Packed Horizontal Add Doubleword
SMPTypeCategory[NN_phsubw] = 14;              // Packed Horizontal Subtract Word
SMPTypeCategory[NN_phsubd] = 14;              // Packed Horizontal Subtract Doubleword
SMPTypeCategory[NN_palignr] = 14;             // Packed Align Right
SMPTypeCategory[NN_pabsb] = 14;               // Packed Absolute Value Byte
SMPTypeCategory[NN_pabsw] = 14;               // Packed Absolute Value Word
SMPTypeCategory[NN_pabsd] = 14;               // Packed Absolute Value Doubleword

// VMX instructions

SMPTypeCategory[NN_vmcall] = 1;              // Call to VM Monitor
SMPTypeCategory[NN_vmclear] = 0;             // Clear Virtual Machine Control Structure
SMPTypeCategory[NN_vmlaunch] = 1;            // Launch Virtual Machine
SMPTypeCategory[NN_vmresume] = 1;            // Resume Virtual Machine
SMPTypeCategory[NN_vmptrld] = 6;             // Load Pointer to Virtual Machine Control Structure
SMPTypeCategory[NN_vmptrst] = 0;             // Store Pointer to Virtual Machine Control Structure
SMPTypeCategory[NN_vmread] = 0;              // Read Field from Virtual Machine Control Structure
SMPTypeCategory[NN_vmwrite] = 0;             // Write Field from Virtual Machine Control Structure
SMPTypeCategory[NN_vmxoff] = 1;              // Leave VMX Operation
SMPTypeCategory[NN_vmxon] = 1;               // Enter VMX Operation

SMPTypeCategory[NN_last] = 1;

  return;

} // end InitTypeCategory()