SMPDataFlowAnalysis.cpp

SMPDefsFlags[NN_fxsave] = false;              // Fast save FP context        
SMPDefsFlags[NN_fxrstor] = false;             // Fast restore FP context     

//      Pentium II instructions

SMPDefsFlags[NN_sysexit] = false;             // Fast Transition from System Call Entry Point

//      3DNow! instructions

SMPDefsFlags[NN_pavgusb] = false;             // Packed 8-bit Unsigned Integer Averaging
SMPDefsFlags[NN_pfadd] = false;               // Packed Floating-Point Addition
SMPDefsFlags[NN_pfsub] = false;               // Packed Floating-Point Subtraction
SMPDefsFlags[NN_pfsubr] = false;              // Packed Floating-Point Reverse Subtraction
SMPDefsFlags[NN_pfacc] = false;               // Packed Floating-Point Accumulate
SMPDefsFlags[NN_pfcmpge] = false;             // Packed Floating-Point Comparison, Greater or Equal
SMPDefsFlags[NN_pfcmpgt] = false;             // Packed Floating-Point Comparison, Greater
SMPDefsFlags[NN_pfcmpeq] = false;             // Packed Floating-Point Comparison, Equal
SMPDefsFlags[NN_pfmin] = false;               // Packed Floating-Point Minimum
SMPDefsFlags[NN_pfmax] = false;               // Packed Floating-Point Maximum
SMPDefsFlags[NN_pi2fd] = false;               // Packed 32-bit Integer to Floating-Point
SMPDefsFlags[NN_pf2id] = false;               // Packed Floating-Point to 32-bit Integer
SMPDefsFlags[NN_pfrcp] = false;               // Packed Floating-Point Reciprocal Approximation
SMPDefsFlags[NN_pfrsqrt] = false;             // Packed Floating-Point Reciprocal Square Root Approximation
SMPDefsFlags[NN_pfmul] = false;               // Packed Floating-Point Multiplication
SMPDefsFlags[NN_pfrcpit1] = false;            // Packed Floating-Point Reciprocal First Iteration Step
SMPDefsFlags[NN_pfrsqit1] = false;            // Packed Floating-Point Reciprocal Square Root First Iteration Step
SMPDefsFlags[NN_pfrcpit2] = false;            // Packed Floating-Point Reciprocal Second Iteration Step
SMPDefsFlags[NN_pmulhrw] = false;             // Packed Floating-Point 16-bit Integer Multiply with rounding
SMPDefsFlags[NN_femms] = false;               // Faster entry/exit of the MMX or floating-point state
SMPDefsFlags[NN_prefetch] = false;            // Prefetch at least a 32-byte line into L1 data cache
SMPDefsFlags[NN_prefetchw] = false;           // Prefetch processor cache line into L1 data cache (mark as modified)


//      Pentium III instructions

SMPDefsFlags[NN_addps] = false;               // Packed Single-FP Add
SMPDefsFlags[NN_addss] = false;               // Scalar Single-FP Add
SMPDefsFlags[NN_andnps] = false;              // Bitwise Logical And Not for Single-FP
SMPDefsFlags[NN_andps] = false;               // Bitwise Logical And for Single-FP
SMPDefsFlags[NN_cmpps] = false;               // Packed Single-FP Compare
SMPDefsFlags[NN_cmpss] = false;               // Scalar Single-FP Compare
SMPDefsFlags[NN_cvtpi2ps] = false;            // Packed signed INT32 to Packed Single-FP conversion
SMPDefsFlags[NN_cvtps2pi] = false;            // Packed Single-FP to Packed INT32 conversion
SMPDefsFlags[NN_cvtsi2ss] = false;            // Scalar signed INT32 to Single-FP conversion
SMPDefsFlags[NN_cvtss2si] = false;            // Scalar Single-FP to signed INT32 conversion
SMPDefsFlags[NN_cvttps2pi] = false;           // Packed Single-FP to Packed INT32 conversion (truncate)
SMPDefsFlags[NN_cvttss2si] = false;           // Scalar Single-FP to signed INT32 conversion (truncate)
SMPDefsFlags[NN_divps] = false;               // Packed Single-FP Divide
SMPDefsFlags[NN_divss] = false;               // Scalar Single-FP Divide
SMPDefsFlags[NN_ldmxcsr] = false;             // Load Streaming SIMD Extensions Technology Control/Status Register
SMPDefsFlags[NN_maxps] = false;               // Packed Single-FP Maximum
SMPDefsFlags[NN_maxss] = false;               // Scalar Single-FP Maximum
SMPDefsFlags[NN_minps] = false;               // Packed Single-FP Minimum
SMPDefsFlags[NN_minss] = false;               // Scalar Single-FP Minimum
SMPDefsFlags[NN_movaps] = false;              // Move Aligned Four Packed Single-FP  
SMPDefsFlags[NN_movhlps] = false;             // Move High to Low Packed Single-FP
SMPDefsFlags[NN_movhps] = false;              // Move High Packed Single-FP
SMPDefsFlags[NN_movlhps] = false;             // Move Low to High Packed Single-FP
SMPDefsFlags[NN_movlps] = false;              // Move Low Packed Single-FP
SMPDefsFlags[NN_movmskps] = false;            // Move Mask to Register
SMPDefsFlags[NN_movss] = false;               // Move Scalar Single-FP
SMPDefsFlags[NN_movups] = false;              // Move Unaligned Four Packed Single-FP
SMPDefsFlags[NN_mulps] = false;               // Packed Single-FP Multiply
SMPDefsFlags[NN_mulss] = false;               // Scalar Single-FP Multiply
SMPDefsFlags[NN_orps] = false;                // Bitwise Logical OR for Single-FP Data
SMPDefsFlags[NN_rcpps] = false;               // Packed Single-FP Reciprocal
SMPDefsFlags[NN_rcpss] = false;               // Scalar Single-FP Reciprocal
SMPDefsFlags[NN_rsqrtps] = false;             // Packed Single-FP Square Root Reciprocal
SMPDefsFlags[NN_rsqrtss] = false;             // Scalar Single-FP Square Root Reciprocal
SMPDefsFlags[NN_shufps] = false;              // Shuffle Single-FP
SMPDefsFlags[NN_sqrtps] = false;              // Packed Single-FP Square Root
SMPDefsFlags[NN_sqrtss] = false;              // Scalar Single-FP Square Root
SMPDefsFlags[NN_stmxcsr] = false;             // Store Streaming SIMD Extensions Technology Control/Status Register 
SMPDefsFlags[NN_subps] = false;               // Packed Single-FP Subtract
SMPDefsFlags[NN_subss] = false;               // Scalar Single-FP Subtract
SMPDefsFlags[NN_unpckhps] = false;            // Unpack High Packed Single-FP Data
SMPDefsFlags[NN_unpcklps] = false;            // Unpack Low Packed Single-FP Data
SMPDefsFlags[NN_xorps] = false;               // Bitwise Logical XOR for Single-FP Data
SMPDefsFlags[NN_pavgb] = false;               // Packed Average (Byte)
SMPDefsFlags[NN_pavgw] = false;               // Packed Average (Word)
SMPDefsFlags[NN_pextrw] = false;              // Extract Word
SMPDefsFlags[NN_pinsrw] = false;              // Insert Word
SMPDefsFlags[NN_pmaxsw] = false;              // Packed Signed Integer Word Maximum
SMPDefsFlags[NN_pmaxub] = false;              // Packed Unsigned Integer Byte Maximum
SMPDefsFlags[NN_pminsw] = false;              // Packed Signed Integer Word Minimum
SMPDefsFlags[NN_pminub] = false;              // Packed Unsigned Integer Byte Minimum
SMPDefsFlags[NN_pmovmskb] = false;            // Move Byte Mask to Integer
SMPDefsFlags[NN_pmulhuw] = false;             // Packed Multiply High Unsigned
SMPDefsFlags[NN_psadbw] = false;              // Packed Sum of Absolute Differences
SMPDefsFlags[NN_pshufw] = false;              // Packed Shuffle Word
SMPDefsFlags[NN_maskmovq] = false;            // Byte Mask write  
SMPDefsFlags[NN_movntps] = false;             // Move Aligned Four Packed Single-FP Non Temporal
SMPDefsFlags[NN_movntq] = false;              // Move 64 Bits Non Temporal   
SMPDefsFlags[NN_prefetcht0] = false;          // Prefetch to all cache levels
SMPDefsFlags[NN_prefetcht1] = false;          // Prefetch to all cache levels
SMPDefsFlags[NN_prefetcht2] = false;          // Prefetch to L2 cache
SMPDefsFlags[NN_prefetchnta] = false;         // Prefetch to L1 cache
SMPDefsFlags[NN_sfence] = false;              // Store Fence

// Pentium III Pseudo instructions

SMPDefsFlags[NN_cmpeqps] = false;             // Packed Single-FP Compare EQ
SMPDefsFlags[NN_cmpltps] = false;             // Packed Single-FP Compare LT
SMPDefsFlags[NN_cmpleps] = false;             // Packed Single-FP Compare LE
SMPDefsFlags[NN_cmpunordps] = false;          // Packed Single-FP Compare UNORD
SMPDefsFlags[NN_cmpneqps] = false;            // Packed Single-FP Compare NOT EQ
SMPDefsFlags[NN_cmpnltps] = false;            // Packed Single-FP Compare NOT LT
SMPDefsFlags[NN_cmpnleps] = false;            // Packed Single-FP Compare NOT LE
SMPDefsFlags[NN_cmpordps] = false;            // Packed Single-FP Compare ORDERED
SMPDefsFlags[NN_cmpeqss] = false;             // Scalar Single-FP Compare EQ
SMPDefsFlags[NN_cmpltss] = false;             // Scalar Single-FP Compare LT
SMPDefsFlags[NN_cmpless] = false;             // Scalar Single-FP Compare LE
SMPDefsFlags[NN_cmpunordss] = false;          // Scalar Single-FP Compare UNORD
SMPDefsFlags[NN_cmpneqss] = false;            // Scalar Single-FP Compare NOT EQ
SMPDefsFlags[NN_cmpnltss] = false;            // Scalar Single-FP Compare NOT LT
SMPDefsFlags[NN_cmpnless] = false;            // Scalar Single-FP Compare NOT LE
SMPDefsFlags[NN_cmpordss] = false;            // Scalar Single-FP Compare ORDERED

// AMD K7 instructions

// Revisit AMD if we port to it.
SMPDefsFlags[NN_pf2iw] = false;               // Packed Floating-Point to Integer with Sign Extend
SMPDefsFlags[NN_pfnacc] = false;              // Packed Floating-Point Negative Accumulate
SMPDefsFlags[NN_pfpnacc] = false;             // Packed Floating-Point Mixed Positive-Negative Accumulate
SMPDefsFlags[NN_pi2fw] = false;               // Packed 16-bit Integer to Floating-Point
SMPDefsFlags[NN_pswapd] = false;              // Packed Swap Double Word

// Undocumented FP instructions (thanks to norbert.juffa@adm.com)

SMPDefsFlags[NN_fstp1] = false;               // Alias of Store Real and Pop
SMPDefsFlags[NN_fxch4] = false;               // Alias of Exchange Registers
SMPDefsFlags[NN_ffreep] = false;              // Free Register and Pop
SMPDefsFlags[NN_fxch7] = false;               // Alias of Exchange Registers
SMPDefsFlags[NN_fstp8] = false;               // Alias of Store Real and Pop
SMPDefsFlags[NN_fstp9] = false;               // Alias of Store Real and Pop

// Pentium 4 instructions

SMPDefsFlags[NN_addpd] = false;               // Add Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_addsd] = false;               // Add Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_andnpd] = false;              // Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_andpd] = false;               // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_clflush] = false;             // Flush Cache Line
SMPDefsFlags[NN_cmppd] = false;               // Compare Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_cmpsd] = false;               // Compare Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_cvtdq2pd] = false;            // Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_cvtdq2ps] = false;            // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_cvtpd2dq] = false;            // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_cvtpd2pi] = false;            // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_cvtpd2ps] = false;            // Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
SMPDefsFlags[NN_cvtpi2pd] = false;            // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_cvtps2dq] = false;            // Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_cvtps2pd] = false;            // Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_cvtsd2si] = false;            // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
SMPDefsFlags[NN_cvtsd2ss] = false;            // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
SMPDefsFlags[NN_cvtsi2sd] = false;            // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_cvtss2sd] = false;            // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_cvttpd2dq] = false;           // Convert With Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_cvttpd2pi] = false;           // Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_cvttps2dq] = false;           // Convert With Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
SMPDefsFlags[NN_cvttsd2si] = false;           // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
SMPDefsFlags[NN_divpd] = false;               // Divide Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_divsd] = false;               // Divide Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_lfence] = false;              // Load Fence
SMPDefsFlags[NN_maskmovdqu] = false;          // Store Selected Bytes of Double Quadword 
SMPDefsFlags[NN_maxpd] = false;               // Return Maximum Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_maxsd] = false;               // Return Maximum Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_mfence] = false;              // Memory Fence
SMPDefsFlags[NN_minpd] = false;               // Return Minimum Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_minsd] = false;               // Return Minimum Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_movapd] = false;              // Move Aligned Packed Double-Precision Floating-Point Values 
SMPDefsFlags[NN_movdq2q] = false;             // Move Quadword from XMM to MMX Register
SMPDefsFlags[NN_movdqa] = false;              // Move Aligned Double Quadword  
SMPDefsFlags[NN_movdqu] = false;              // Move Unaligned Double Quadword  
SMPDefsFlags[NN_movhpd] = false;              // Move High Packed Double-Precision Floating-Point Values 
SMPDefsFlags[NN_movlpd] = false;              // Move Low Packed Double-Precision Floating-Point Values 
SMPDefsFlags[NN_movmskpd] = false;            // Extract Packed Double-Precision Floating-Point Sign Mask
SMPDefsFlags[NN_movntdq] = false;             // Store Double Quadword Using Non-Temporal Hint
SMPDefsFlags[NN_movnti] = false;              // Store Doubleword Using Non-Temporal Hint
SMPDefsFlags[NN_movntpd] = false;             // Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
SMPDefsFlags[NN_movq2dq] = false;             // Move Quadword from MMX to XMM Register
SMPDefsFlags[NN_movsd] = false;               // Move Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_movupd] = false;              // Move Unaligned Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_mulpd] = false;               // Multiply Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_mulsd] = false;               // Multiply Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_orpd] = false;                // Bitwise Logical OR of Double-Precision Floating-Point Values
SMPDefsFlags[NN_paddq] = false;               // Add Packed Quadword Integers
SMPDefsFlags[NN_pause] = false;               // Spin Loop Hint
SMPDefsFlags[NN_pmuludq] = false;             // Multiply Packed Unsigned Doubleword Integers
SMPDefsFlags[NN_pshufd] = false;              // Shuffle Packed Doublewords
SMPDefsFlags[NN_pshufhw] = false;             // Shuffle Packed High Words
SMPDefsFlags[NN_pshuflw] = false;             // Shuffle Packed Low Words
SMPDefsFlags[NN_pslldq] = false;              // Shift Double Quadword Left Logical
SMPDefsFlags[NN_psrldq] = false;              // Shift Double Quadword Right Logical
SMPDefsFlags[NN_psubq] = false;               // Subtract Packed Quadword Integers
SMPDefsFlags[NN_punpckhqdq] = false;          // Unpack High Data
SMPDefsFlags[NN_punpcklqdq] = false;          // Unpack Low Data
SMPDefsFlags[NN_shufpd] = false;              // Shuffle Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_sqrtpd] = false;              // Compute Square Roots of Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_sqrtsd] = false;              // Compute Square Rootof Scalar Double-Precision Floating-Point Value
SMPDefsFlags[NN_subpd] = false;               // Subtract Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_subsd] = false;               // Subtract Scalar Double-Precision Floating-Point Values
SMPDefsFlags[NN_unpckhpd] = false;            // Unpack and Interleave High Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_unpcklpd] = false;            // Unpack and Interleave Low Packed Double-Precision Floating-Point Values
SMPDefsFlags[NN_xorpd] = false;               // Bitwise Logical OR of Double-Precision Floating-Point Values


// AMD syscall/sysret instructions  NOTE: not AMD, found in Intel manual


// AMD64 instructions    NOTE: not AMD, found in Intel manual

SMPDefsFlags[NN_swapgs] = false;              // Exchange GS base with KernelGSBase MSR

// New Pentium instructions (SSE3)

SMPDefsFlags[NN_movddup] = false;             // Move One Double-FP and Duplicate
SMPDefsFlags[NN_movshdup] = false;            // Move Packed Single-FP High and Duplicate
SMPDefsFlags[NN_movsldup] = false;            // Move Packed Single-FP Low and Duplicate

// Missing AMD64 instructions  NOTE: also found in Intel manual

SMPDefsFlags[NN_movsxd] = false;              // Move with Sign-Extend Doubleword

// SSE3 instructions

SMPDefsFlags[NN_addsubpd] = false;            // Add /Sub packed DP FP numbers
SMPDefsFlags[NN_addsubps] = false;            // Add /Sub packed SP FP numbers
SMPDefsFlags[NN_haddpd] = false;              // Add horizontally packed DP FP numbers
SMPDefsFlags[NN_haddps] = false;              // Add horizontally packed SP FP numbers
SMPDefsFlags[NN_hsubpd] = false;              // Sub horizontally packed DP FP numbers
SMPDefsFlags[NN_hsubps] = false;              // Sub horizontally packed SP FP numbers
SMPDefsFlags[NN_monitor] = false;             // Set up a linear address range to be monitored by hardware
SMPDefsFlags[NN_mwait] = false;               // Wait until write-back store performed within the range specified by the MONITOR instruction
SMPDefsFlags[NN_fisttp] = false;              // Store ST in intXX (chop) and pop
SMPDefsFlags[NN_lddqu] = false;               // Load unaligned integer 128-bit

// SSSE3 instructions

SMPDefsFlags[NN_psignb] = false;              // Packed SIGN Byte
SMPDefsFlags[NN_psignw] = false;              // Packed SIGN Word
SMPDefsFlags[NN_psignd] = false;              // Packed SIGN Doubleword
SMPDefsFlags[NN_pshufb] = false;              // Packed Shuffle Bytes
SMPDefsFlags[NN_pmulhrsw] = false;            // Packed Multiply High with Round and Scale
SMPDefsFlags[NN_pmaddubsw] = false;           // Multiply and Add Packed Signed and Unsigned Bytes
SMPDefsFlags[NN_phsubsw] = false;             // Packed Horizontal Subtract and Saturate
SMPDefsFlags[NN_phaddsw] = false;             // Packed Horizontal Add and Saturate
SMPDefsFlags[NN_phaddw] = false;              // Packed Horizontal Add Word
SMPDefsFlags[NN_phaddd] = false;              // Packed Horizontal Add Doubleword
SMPDefsFlags[NN_phsubw] = false;              // Packed Horizontal Subtract Word
SMPDefsFlags[NN_phsubd] = false;              // Packed Horizontal Subtract Doubleword
SMPDefsFlags[NN_palignr] = false;             // Packed Align Right
SMPDefsFlags[NN_pabsb] = false;               // Packed Absolute Value Byte
SMPDefsFlags[NN_pabsw] = false;               // Packed Absolute Value Word
SMPDefsFlags[NN_pabsd] = false;               // Packed Absolute Value Doubleword

// VMX instructions

SMPDefsFlags[NN_last] = false;

  return;

} // end InitSMPDefsFlags()

// Initialize the SMPUsesFlags[] array to define how we emit
//   optimizing annotations.
void InitSMPUsesFlags(void) {
	// Default value is false. Few instructions use the flags.
	(void) memset(SMPUsesFlags, false, sizeof(SMPUsesFlags));

SMPUsesFlags[NN_null] = true;            // Unknown Operation
#if 1
SMPUsesFlags[NN_aaa] = true;                 // ASCII adjust after addition
SMPUsesFlags[NN_aas] = true;				 // ASCII adjust after subtraction
#endif
SMPUsesFlags[NN_adc] = true;                 // Add with Carry
SMPUsesFlags[NN_into] = true;                // Call to Interrupt Procedure if Overflow Flag = 1
SMPUsesFlags[NN_ja] = true;                  // Jump if Above (CF=0 & ZF=0)
SMPUsesFlags[NN_jae] = true;                 // Jump if Above or Equal (CF=0)
SMPUsesFlags[NN_jb] = true;                  // Jump if Below (CF=1)
SMPUsesFlags[NN_jbe] = true;                 // Jump if Below or Equal (CF=1 | ZF=1)
SMPUsesFlags[NN_jc] = true;                  // Jump if Carry (CF=1)
SMPUsesFlags[NN_jcxz] = true;                // Jump if CX is 0
SMPUsesFlags[NN_jecxz] = true;               // Jump if ECX is 0
SMPUsesFlags[NN_jrcxz] = true;               // Jump if RCX is 0
SMPUsesFlags[NN_je] = true;                  // Jump if Equal (ZF=1)
SMPUsesFlags[NN_jg] = true;                  // Jump if Greater (ZF=0 & SF=OF)
SMPUsesFlags[NN_jge] = true;                 // Jump if Greater or Equal (SF=OF)
SMPUsesFlags[NN_jl] = true;                  // Jump if Less (SF!=OF)
SMPUsesFlags[NN_jle] = true;                 // Jump if Less or Equal (ZF=1 | SF!=OF)
SMPUsesFlags[NN_jna] = true;                 // Jump if Not Above (CF=1 | ZF=1)
SMPUsesFlags[NN_jnae] = true;                // Jump if Not Above or Equal (CF=1)
SMPUsesFlags[NN_jnb] = true;                 // Jump if Not Below (CF=0)
SMPUsesFlags[NN_jnbe] = true;                // Jump if Not Below or Equal (CF=0 & ZF=0)
SMPUsesFlags[NN_jnc] = true;                 // Jump if Not Carry (CF=0)
SMPUsesFlags[NN_jne] = true;                 // Jump if Not Equal (ZF=0)
SMPUsesFlags[NN_jng] = true;                 // Jump if Not Greater (ZF=1 | SF!=OF)
SMPUsesFlags[NN_jnge] = true;                // Jump if Not Greater or Equal (ZF=1)
SMPUsesFlags[NN_jnl] = true;                 // Jump if Not Less (SF=OF)
SMPUsesFlags[NN_jnle] = true;                // Jump if Not Less or Equal (ZF=0 & SF=OF)
SMPUsesFlags[NN_jno] = true;                 // Jump if Not Overflow (OF=0)
SMPUsesFlags[NN_jnp] = true;                 // Jump if Not Parity (PF=0)
SMPUsesFlags[NN_jns] = true;                 // Jump if Not Sign (SF=0)
SMPUsesFlags[NN_jnz] = true;                 // Jump if Not Zero (ZF=0)
SMPUsesFlags[NN_jo] = true;                  // Jump if Overflow (OF=1)
SMPUsesFlags[NN_jp] = true;                  // Jump if Parity (PF=1)
SMPUsesFlags[NN_jpe] = true;                 // Jump if Parity Even (PF=1)
SMPUsesFlags[NN_jpo] = true;                 // Jump if Parity Odd  (PF=0)
SMPUsesFlags[NN_js] = true;                  // Jump if Sign (SF=1)
SMPUsesFlags[NN_jz] = true;                  // Jump if Zero (ZF=1)
SMPUsesFlags[NN_lahf] = true;                // Load Flags into AH Register
SMPUsesFlags[NN_loopwe] = true;              // Loop while CX != 0 and ZF=1
SMPUsesFlags[NN_loope] = true;               // Loop while rCX != 0 and ZF=1
SMPUsesFlags[NN_loopde] = true;              // Loop while ECX != 0 and ZF=1
SMPUsesFlags[NN_loopqe] = true;              // Loop while RCX != 0 and ZF=1
SMPUsesFlags[NN_loopwne] = true;             // Loop while CX != 0 and ZF=0
SMPUsesFlags[NN_loopne] = true;              // Loop while rCX != 0 and ZF=0
SMPUsesFlags[NN_loopdne] = true;             // Loop while ECX != 0 and ZF=0
SMPUsesFlags[NN_loopqne] = true;             // Loop while RCX != 0 and ZF=0
SMPUsesFlags[NN_pushfw] = true;              // Push Flags Register onto the Stack
SMPUsesFlags[NN_pushf] = true;               // Push Flags Register onto the Stack
SMPUsesFlags[NN_pushfd] = true;              // Push Flags Register onto the Stack (use32)
SMPUsesFlags[NN_pushfq] = true;              // Push Flags Register onto the Stack (use64)
SMPUsesFlags[NN_repe] = true;                // Repeat String Operation while ZF=1
SMPUsesFlags[NN_repne] = true;               // Repeat String Operation while ZF=0
#if 0
SMPUsesFlags[NN_sahf] = true;                // Store AH into Flags Register
SMPUsesFlags[NN_shl] = true;                 // Shift Logical Left
SMPUsesFlags[NN_shr] = true;                 // Shift Logical Right
#endif
SMPUsesFlags[NN_sbb] = true;                 // Integer Subtraction with Borrow
SMPUsesFlags[NN_seta] = true;                // Set Byte if Above (CF=0 & ZF=0)
SMPUsesFlags[NN_setae] = true;               // Set Byte if Above or Equal (CF=0)
SMPUsesFlags[NN_setb] = true;                // Set Byte if Below (CF=1)
SMPUsesFlags[NN_setbe] = true;               // Set Byte if Below or Equal (CF=1 | ZF=1)
SMPUsesFlags[NN_setc] = true;                // Set Byte if Carry (CF=1)
SMPUsesFlags[NN_sete] = true;                // Set Byte if Equal (ZF=1)
SMPUsesFlags[NN_setg] = true;                // Set Byte if Greater (ZF=0 & SF=OF)
SMPUsesFlags[NN_setge] = true;               // Set Byte if Greater or Equal (SF=OF)
SMPUsesFlags[NN_setl] = true;                // Set Byte if Less (SF!=OF)
SMPUsesFlags[NN_setle] = true;               // Set Byte if Less or Equal (ZF=1 | SF!=OF)
SMPUsesFlags[NN_setna] = true;               // Set Byte if Not Above (CF=1 | ZF=1)
SMPUsesFlags[NN_setnae] = true;              // Set Byte if Not Above or Equal (CF=1)
SMPUsesFlags[NN_setnb] = true;               // Set Byte if Not Below (CF=0)
SMPUsesFlags[NN_setnbe] = true;              // Set Byte if Not Below or Equal (CF=0 & ZF=0)
SMPUsesFlags[NN_setnc] = true;               // Set Byte if Not Carry (CF=0)
SMPUsesFlags[NN_setne] = true;               // Set Byte if Not Equal (ZF=0)
SMPUsesFlags[NN_setng] = true;               // Set Byte if Not Greater (ZF=1 | SF!=OF)
SMPUsesFlags[NN_setnge] = true;              // Set Byte if Not Greater or Equal (ZF=1)
SMPUsesFlags[NN_setnl] = true;               // Set Byte if Not Less (SF=OF)
SMPUsesFlags[NN_setnle] = true;              // Set Byte if Not Less or Equal (ZF=0 & SF=OF)
SMPUsesFlags[NN_setno] = true;               // Set Byte if Not Overflow (OF=0)
SMPUsesFlags[NN_setnp] = true;               // Set Byte if Not Parity (PF=0)
SMPUsesFlags[NN_setns] = true;               // Set Byte if Not Sign (SF=0)
SMPUsesFlags[NN_setnz] = true;               // Set Byte if Not Zero (ZF=0)
SMPUsesFlags[NN_seto] = true;                // Set Byte if Overflow (OF=1)
SMPUsesFlags[NN_setp] = true;                // Set Byte if Parity (PF=1)
SMPUsesFlags[NN_setpe] = true;               // Set Byte if Parity Even (PF=1)
SMPUsesFlags[NN_setpo] = true;               // Set Byte if Parity Odd  (PF=0)
SMPUsesFlags[NN_sets] = true;                // Set Byte if Sign (SF=1)
SMPUsesFlags[NN_setz] = true;                // Set Byte if Zero (ZF=1)
SMPUsesFlags[NN_stos] = true;                // Store String

//
//      486 instructions
//

//
//      Pentium instructions
//

SMPUsesFlags[NN_cpuid] = true;               // Get CPU ID
#if 0
SMPUsesFlags[NN_cmpxchg8b] = true;           // Compare and Exchange Eight Bytes
#endif

//
//      Pentium Pro instructions
//

SMPUsesFlags[NN_cmova] = true;               // Move if Above (CF=0 & ZF=0)
SMPUsesFlags[NN_cmovb] = true;               // Move if Below (CF=1)
SMPUsesFlags[NN_cmovbe] = true;              // Move if Below or Equal (CF=1 | ZF=1)
SMPUsesFlags[NN_cmovg] = true;               // Move if Greater (ZF=0 & SF=OF)
SMPUsesFlags[NN_cmovge] = true;              // Move if Greater or Equal (SF=OF)
SMPUsesFlags[NN_cmovl] = true;               // Move if Less (SF!=OF)
SMPUsesFlags[NN_cmovle] = true;              // Move if Less or Equal (ZF=1 | SF!=OF)
SMPUsesFlags[NN_cmovnb] = true;              // Move if Not Below (CF=0)
SMPUsesFlags[NN_cmovno] = true;              // Move if Not Overflow (OF=0)
SMPUsesFlags[NN_cmovnp] = true;              // Move if Not Parity (PF=0)
SMPUsesFlags[NN_cmovns] = true;              // Move if Not Sign (SF=0)
SMPUsesFlags[NN_cmovnz] = true;              // Move if Not Zero (ZF=0)
SMPUsesFlags[NN_cmovo] = true;               // Move if Overflow (OF=1)
SMPUsesFlags[NN_cmovp] = true;               // Move if Parity (PF=1)
SMPUsesFlags[NN_cmovs] = true;               // Move if Sign (SF=1)
SMPUsesFlags[NN_cmovz] = true;               // Move if Zero (ZF=1)
SMPUsesFlags[NN_fcmovb] = true;              // Floating Move if Below          
SMPUsesFlags[NN_fcmove] = true;              // Floating Move if Equal          
SMPUsesFlags[NN_fcmovbe] = true;             // Floating Move if Below or Equal 
SMPUsesFlags[NN_fcmovu] = true;              // Floating Move if Unordered      
SMPUsesFlags[NN_fcmovnb] = true;             // Floating Move if Not Below      
SMPUsesFlags[NN_fcmovne] = true;             // Floating Move if Not Equal      
SMPUsesFlags[NN_fcmovnbe] = true;            // Floating Move if Not Below or Equal
SMPUsesFlags[NN_fcmovnu] = true;             // Floating Move if Not Unordered     

//
//      FPP instructions
//


//
//      80387 instructions
//


//
//      Instructions added 28.02.96
//

SMPUsesFlags[NN_setalc] = true;              // Set AL to Carry Flag      

//
//      MMX instructions
//


//
//      Undocumented Deschutes processor instructions
//


//      Pentium II instructions


//      3DNow! instructions


//      Pentium III instructions


// Pentium III Pseudo instructions


// AMD K7 instructions

// Revisit AMD if we port to it.

// Undocumented FP instructions (thanks to norbert.juffa@adm.com)

// Pentium 4 instructions



// AMD syscall/sysret instructions  NOTE: not AMD, found in Intel manual

// AMD64 instructions    NOTE: not AMD, found in Intel manual


// New Pentium instructions (SSE3)


// Missing AMD64 instructions  NOTE: also found in Intel manual


// SSE3 instructions


// SSSE3 instructions


// VMX instructions


SMPUsesFlags[NN_last] = false;

  return;

} // end InitSMPUsesFlags()