SMPDataFlowAnalysis.cpp

SMPTypeCategory[NN_pshufd] = 14;              // Shuffle Packed Doublewords
SMPTypeCategory[NN_pshufhw] = 14;             // Shuffle Packed High Words
SMPTypeCategory[NN_pshuflw] = 14;             // Shuffle Packed Low Words
SMPTypeCategory[NN_pslldq] = 14;              // Shift Double Quadword Left Logical
SMPTypeCategory[NN_psrldq] = 14;              // Shift Double Quadword Right Logical
SMPTypeCategory[NN_psubq] = 14;               // Subtract Packed Quadword Integers
SMPTypeCategory[NN_punpckhqdq] = 14;          // Unpack High Data
SMPTypeCategory[NN_punpcklqdq] = 14;          // Unpack Low Data
SMPTypeCategory[NN_shufpd] = 14;              // Shuffle Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_sqrtpd] = 1;              // Compute Square Roots of Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_sqrtsd] = 14;              // Compute Square Rootof Scalar Double-Precision Floating-Point Value
SMPTypeCategory[NN_subpd] = 14;               // Subtract Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_subsd] = 14;               // Subtract Scalar Double-Precision Floating-Point Values
SMPTypeCategory[NN_ucomisd] = 14;             // Unordered Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
SMPTypeCategory[NN_unpckhpd] = 14;            // Unpack and Interleave High Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_unpcklpd] = 14;            // Unpack and Interleave Low Packed Double-Precision Floating-Point Values
SMPTypeCategory[NN_xorpd] = 14;               // Bitwise Logical OR of Double-Precision Floating-Point Values


// AMD syscall/sysret instructions  NOTE: not AMD, found in Intel manual

SMPTypeCategory[NN_syscall] = 1;             // Low latency system call
SMPTypeCategory[NN_sysret] = 1;              // Return from system call

// AMD64 instructions    NOTE: not AMD, found in Intel manual

SMPTypeCategory[NN_swapgs] = 1;              // Exchange GS base with KernelGSBase MSR

// New Pentium instructions (SSE3)

SMPTypeCategory[NN_movddup] = 14;             // Move One Double-FP and Duplicate
SMPTypeCategory[NN_movshdup] = 14;            // Move Packed Single-FP High and Duplicate
SMPTypeCategory[NN_movsldup] = 14;            // Move Packed Single-FP Low and Duplicate

// Missing AMD64 instructions  NOTE: also found in Intel manual

SMPTypeCategory[NN_movsxd] = 2;              // Move with Sign-Extend Doubleword
SMPTypeCategory[NN_cmpxchg16b] = 0;          // Compare and Exchange 16 Bytes

// SSE3 instructions

SMPTypeCategory[NN_addsubpd] = 14;            // Add /Sub packed DP FP numbers
SMPTypeCategory[NN_addsubps] = 14;            // Add /Sub packed SP FP numbers
SMPTypeCategory[NN_haddpd] = 14;              // Add horizontally packed DP FP numbers
SMPTypeCategory[NN_haddps] = 14;              // Add horizontally packed SP FP numbers
SMPTypeCategory[NN_hsubpd] = 14;              // Sub horizontally packed DP FP numbers
SMPTypeCategory[NN_hsubps] = 14;              // Sub horizontally packed SP FP numbers
SMPTypeCategory[NN_monitor] = 1;             // Set up a linear address range to be monitored by hardware
SMPTypeCategory[NN_mwait] = 1;               // Wait until write-back store performed within the range specified by the MONITOR instruction
SMPTypeCategory[NN_fisttp] = 13;              // Store ST in intXX (chop) and pop
SMPTypeCategory[NN_lddqu] = 14;               // Load unaligned integer 128-bit

// SSSE3 instructions

SMPTypeCategory[NN_psignb] = 14;              // Packed SIGN Byte
SMPTypeCategory[NN_psignw] = 14;              // Packed SIGN Word
SMPTypeCategory[NN_psignd] = 14;              // Packed SIGN Doubleword
SMPTypeCategory[NN_pshufb] = 14;              // Packed Shuffle Bytes
SMPTypeCategory[NN_pmulhrsw] = 14;            // Packed Multiply High with Round and Scale
SMPTypeCategory[NN_pmaddubsw] = 14;           // Multiply and Add Packed Signed and Unsigned Bytes
SMPTypeCategory[NN_phsubsw] = 14;             // Packed Horizontal Subtract and Saturate
SMPTypeCategory[NN_phaddsw] = 14;             // Packed Horizontal Add and Saturate
SMPTypeCategory[NN_phaddw] = 14;              // Packed Horizontal Add Word
SMPTypeCategory[NN_phaddd] = 14;              // Packed Horizontal Add Doubleword
SMPTypeCategory[NN_phsubw] = 14;              // Packed Horizontal Subtract Word
SMPTypeCategory[NN_phsubd] = 14;              // Packed Horizontal Subtract Doubleword
SMPTypeCategory[NN_palignr] = 15;             // Packed Align Right
SMPTypeCategory[NN_pabsb] = 14;               // Packed Absolute Value Byte
SMPTypeCategory[NN_pabsw] = 14;               // Packed Absolute Value Word
SMPTypeCategory[NN_pabsd] = 14;               // Packed Absolute Value Doubleword

// VMX instructions

SMPTypeCategory[NN_vmcall] = 1;              // Call to VM Monitor
SMPTypeCategory[NN_vmclear] = 0;             // Clear Virtual Machine Control Structure
SMPTypeCategory[NN_vmlaunch] = 1;            // Launch Virtual Machine
SMPTypeCategory[NN_vmresume] = 1;            // Resume Virtual Machine
SMPTypeCategory[NN_vmptrld] = 6;             // Load Pointer to Virtual Machine Control Structure
SMPTypeCategory[NN_vmptrst] = 0;             // Store Pointer to Virtual Machine Control Structure
SMPTypeCategory[NN_vmread] = 0;              // Read Field from Virtual Machine Control Structure
SMPTypeCategory[NN_vmwrite] = 0;             // Write Field from Virtual Machine Control Structure
SMPTypeCategory[NN_vmxoff] = 1;              // Leave VMX Operation
SMPTypeCategory[NN_vmxon] = 1;               // Enter VMX Operation

#if 599 < IDA_SDK_VERSION

SMPTypeCategory[NN_ud2] = 1;                 // Undefined Instruction

// Added with x86-64

SMPTypeCategory[NN_rdtscp] = 8;              // Read Time-Stamp Counter and Processor ID

// Geode LX 3DNow! extensions

SMPTypeCategory[NN_pfrcpv] = 1;              // Reciprocal Approximation for a Pair of 32-bit Floats
SMPTypeCategory[NN_pfrsqrtv] = 1;            // Reciprocal Square Root Approximation for a Pair of 32-bit Floats

// SSE2 pseudoinstructions

SMPTypeCategory[NN_cmpeqpd] = 1;             // Packed Double-FP Compare EQ
SMPTypeCategory[NN_cmpltpd] = 1;             // Packed Double-FP Compare LT
SMPTypeCategory[NN_cmplepd] = 1;             // Packed Double-FP Compare LE
SMPTypeCategory[NN_cmpunordpd] = 1;          // Packed Double-FP Compare UNORD
SMPTypeCategory[NN_cmpneqpd] = 1;            // Packed Double-FP Compare NOT EQ
SMPTypeCategory[NN_cmpnltpd] = 1;            // Packed Double-FP Compare NOT LT
SMPTypeCategory[NN_cmpnlepd] = 1;            // Packed Double-FP Compare NOT LE
SMPTypeCategory[NN_cmpordpd] = 1;            // Packed Double-FP Compare ORDERED
SMPTypeCategory[NN_cmpeqsd] = 1;             // Scalar Double-FP Compare EQ
SMPTypeCategory[NN_cmpltsd] = 1;             // Scalar Double-FP Compare LT
SMPTypeCategory[NN_cmplesd] = 1;             // Scalar Double-FP Compare LE
SMPTypeCategory[NN_cmpunordsd] = 1;          // Scalar Double-FP Compare UNORD
SMPTypeCategory[NN_cmpneqsd] = 1;            // Scalar Double-FP Compare NOT EQ
SMPTypeCategory[NN_cmpnltsd] = 1;            // Scalar Double-FP Compare NOT LT
SMPTypeCategory[NN_cmpnlesd] = 1;            // Scalar Double-FP Compare NOT LE
SMPTypeCategory[NN_cmpordsd] = 1;            // Scalar Double-FP Compare ORDERED

// SSSE4.1 instructions

SMPTypeCategory[NN_blendpd] = 14;             // Blend Packed Double Precision Floating-Point Values
SMPTypeCategory[NN_blendps] = 14;             // Blend Packed Single Precision Floating-Point Values
SMPTypeCategory[NN_blendvpd] = 14;            // Variable Blend Packed Double Precision Floating-Point Values
SMPTypeCategory[NN_blendvps] = 14;            // Variable Blend Packed Single Precision Floating-Point Values
SMPTypeCategory[NN_dppd] = 14;                // Dot Product of Packed Double Precision Floating-Point Values
SMPTypeCategory[NN_dpps] = 14;                // Dot Product of Packed Single Precision Floating-Point Values
SMPTypeCategory[NN_extractps] = 2;            // Extract Packed Single Precision Floating-Point Value
SMPTypeCategory[NN_insertps] = 14;            // Insert Packed Single Precision Floating-Point Value
SMPTypeCategory[NN_movntdqa] = 0;             // Load Double Quadword Non-Temporal Aligned Hint
SMPTypeCategory[NN_mpsadbw] = 1;              // Compute Multiple Packed Sums of Absolute Difference
SMPTypeCategory[NN_packusdw] = 14;            // Pack with Unsigned Saturation
SMPTypeCategory[NN_pblendvb] = 14;            // Variable Blend Packed Bytes
SMPTypeCategory[NN_pblendw] = 14;             // Blend Packed Words
SMPTypeCategory[NN_pcmpeqq] = 14;             // Compare Packed Qword Data for Equal
SMPTypeCategory[NN_pextrb] = 15;              // Extract Byte
SMPTypeCategory[NN_pextrd] = 15;              // Extract Dword
SMPTypeCategory[NN_pextrq] = 15;              // Extract Qword
SMPTypeCategory[NN_phminposuw] = 14;          // Packed Horizontal Word Minimum
SMPTypeCategory[NN_pinsrb] = 14;              // Insert Byte  !!! Could this be used as a generic move???
SMPTypeCategory[NN_pinsrd] = 14;              // Insert Dword  !!! Could this be used as a generic move???
SMPTypeCategory[NN_pinsrq] = 14;              // Insert Qword  !!! Could this be used as a generic move???
SMPTypeCategory[NN_pmaxsb] = 14;              // Maximum of Packed Signed Byte Integers
SMPTypeCategory[NN_pmaxsd] = 14;              // Maximum of Packed Signed Dword Integers
SMPTypeCategory[NN_pmaxud] = 14;              // Maximum of Packed Unsigned Dword Integers
SMPTypeCategory[NN_pmaxuw] = 14;              // Maximum of Packed Word Integers
SMPTypeCategory[NN_pminsb] = 14;              // Minimum of Packed Signed Byte Integers
SMPTypeCategory[NN_pminsd] = 14;              // Minimum of Packed Signed Dword Integers
SMPTypeCategory[NN_pminud] = 14;              // Minimum of Packed Unsigned Dword Integers
SMPTypeCategory[NN_pminuw] = 14;              // Minimum of Packed Word Integers
SMPTypeCategory[NN_pmovsxbw] = 14;            // Packed Move with Sign Extend
SMPTypeCategory[NN_pmovsxbd] = 14;            // Packed Move with Sign Extend
SMPTypeCategory[NN_pmovsxbq] = 14;            // Packed Move with Sign Extend
SMPTypeCategory[NN_pmovsxwd] = 14;            // Packed Move with Sign Extend
SMPTypeCategory[NN_pmovsxwq] = 14;            // Packed Move with Sign Extend
SMPTypeCategory[NN_pmovsxdq] = 14;            // Packed Move with Sign Extend
SMPTypeCategory[NN_pmovzxbw] = 14;            // Packed Move with Zero Extend
SMPTypeCategory[NN_pmovzxbd] = 14;            // Packed Move with Zero Extend
SMPTypeCategory[NN_pmovzxbq] = 14;            // Packed Move with Zero Extend
SMPTypeCategory[NN_pmovzxwd] = 14;            // Packed Move with Zero Extend
SMPTypeCategory[NN_pmovzxwq] = 14;            // Packed Move with Zero Extend
SMPTypeCategory[NN_pmovzxdq] = 14;            // Packed Move with Zero Extend
SMPTypeCategory[NN_pmuldq] = 14;              // Multiply Packed Signed Dword Integers
SMPTypeCategory[NN_pmulld] = 14;              // Multiply Packed Signed Dword Integers and Store Low Result
SMPTypeCategory[NN_ptest] = 1;                // Logical Compare
SMPTypeCategory[NN_roundpd] = 14;             // Round Packed Double Precision Floating-Point Values
SMPTypeCategory[NN_roundps] = 14;             // Round Packed Single Precision Floating-Point Values
SMPTypeCategory[NN_roundsd] = 14;             // Round Scalar Double Precision Floating-Point Values
SMPTypeCategory[NN_roundss] = 14;             // Round Scalar Single Precision Floating-Point Values

// SSSE4.2 instructions
SMPTypeCategory[NN_crc32] = 14;               // Accumulate CRC32 Value
SMPTypeCategory[NN_pcmpestri] = 2;            // Packed Compare Explicit Length Strings, Return Index
SMPTypeCategory[NN_pcmpestrm] = 2;            // Packed Compare Explicit Length Strings, Return Mask
SMPTypeCategory[NN_pcmpistri] = 2;            // Packed Compare Implicit Length Strings, Return Index
SMPTypeCategory[NN_pcmpistrm] = 2;            // Packed Compare Implicit Length Strings, Return Mask
SMPTypeCategory[NN_pcmpgtq] = 14;             // Compare Packed Data for Greater Than
SMPTypeCategory[NN_popcnt] = 2;               // Return the Count of Number of Bits Set to 1

// AMD SSE4a instructions

SMPTypeCategory[NN_extrq] = 14;               // Extract Field From Register
SMPTypeCategory[NN_insertq] = 14;             // Insert Field
SMPTypeCategory[NN_movntsd] = 13;             // Move Non-Temporal Scalar Double-Precision Floating-Point !!! Could this be used as a generic move???
SMPTypeCategory[NN_movntss] = 13;             // Move Non-Temporal Scalar Single-Precision Floating-Point !!! Could this be used as a generic move???
SMPTypeCategory[NN_lzcnt] = 2;                // Leading Zero Count

// xsave/xrstor instructions

SMPTypeCategory[NN_xgetbv] = 8;               // Get Value of Extended Control Register
SMPTypeCategory[NN_xrstor] = 0;               // Restore Processor Extended States
SMPTypeCategory[NN_xsave] = 1;                // Save Processor Extended States
SMPTypeCategory[NN_xsetbv] = 1;               // Set Value of Extended Control Register

// Intel Safer Mode Extensions (SMX)

SMPTypeCategory[NN_getsec] = 1;               // Safer Mode Extensions (SMX) Instruction

// AMD-V Virtualization ISA Extension

SMPTypeCategory[NN_clgi] = 0;                 // Clear Global Interrupt Flag
SMPTypeCategory[NN_invlpga] = 1;              // Invalidate TLB Entry in a Specified ASID
SMPTypeCategory[NN_skinit] = 1;               // Secure Init and Jump with Attestation
SMPTypeCategory[NN_stgi] = 0;                 // Set Global Interrupt Flag
SMPTypeCategory[NN_vmexit] = 1;               // Stop Executing Guest, Begin Executing Host
SMPTypeCategory[NN_vmload] = 0;               // Load State from VMCB
SMPTypeCategory[NN_vmmcall] = 1;              // Call VMM
SMPTypeCategory[NN_vmrun] = 1;                // Run Virtual Machine
SMPTypeCategory[NN_vmsave] = 0;               // Save State to VMCB

// VMX+ instructions

SMPTypeCategory[NN_invept] = 1;               // Invalidate Translations Derived from EPT
SMPTypeCategory[NN_invvpid] = 1;              // Invalidate Translations Based on VPID

// Intel Atom instructions

// !!!! continue work here
SMPTypeCategory[NN_movbe] = 3;                // Move Data After Swapping Bytes

// Intel AES instructions

SMPTypeCategory[NN_aesenc] = 14;              // Perform One Round of an AES Encryption Flow
SMPTypeCategory[NN_aesenclast] = 14;          // Perform the Last Round of an AES Encryption Flow
SMPTypeCategory[NN_aesdec] = 14;              // Perform One Round of an AES Decryption Flow
SMPTypeCategory[NN_aesdeclast] = 14;          // Perform the Last Round of an AES Decryption Flow
SMPTypeCategory[NN_aesimc] = 14;              // Perform the AES InvMixColumn Transformation
SMPTypeCategory[NN_aeskeygenassist] = 14;     // AES Round Key Generation Assist

// Carryless multiplication

SMPTypeCategory[NN_pclmulqdq] = 14;           // Carry-Less Multiplication Quadword

#endif  // 599 < IDA_SDK_VERSION

SMPTypeCategory[NN_last] = 1;

  return;

} // end InitTypeCategory()