SMPStaticAnalyzer.cpp

OptCategory[NN_andps] = 1;               // Bitwise Logical And for Single-FP
OptCategory[NN_cmpps] = 1;               // Packed Single-FP Compare
OptCategory[NN_cmpss] = 1;               // Scalar Single-FP Compare
OptCategory[NN_comiss] = 1;              // Scalar Ordered Single-FP Compare and Set EFLAGS
OptCategory[NN_cvtpi2ps] = 1;            // Packed signed INT32 to Packed Single-FP conversion
OptCategory[NN_cvtps2pi] = 1;            // Packed Single-FP to Packed INT32 conversion
OptCategory[NN_cvtsi2ss] = 1;            // Scalar signed INT32 to Single-FP conversion
OptCategory[NN_cvtss2si] = 2;            // Scalar Single-FP to signed INT32 conversion
OptCategory[NN_cvttps2pi] = 1;           // Packed Single-FP to Packed INT32 conversion (truncate)
OptCategory[NN_cvttss2si] = 2;           // Scalar Single-FP to signed INT32 conversion (truncate)
OptCategory[NN_divps] = 1;               // Packed Single-FP Divide
OptCategory[NN_divss] = 1;               // Scalar Single-FP Divide
OptCategory[NN_ldmxcsr] = 1;             // Load Streaming SIMD Extensions Technology Control/Status Register
OptCategory[NN_maxps] = 1;               // Packed Single-FP Maximum
OptCategory[NN_maxss] = 1;               // Scalar Single-FP Maximum
OptCategory[NN_minps] = 1;               // Packed Single-FP Minimum
OptCategory[NN_minss] = 1;               // Scalar Single-FP Minimum
OptCategory[NN_movaps] = 9;              // Move Aligned Four Packed Single-FP  ** infer memsrc 'n'?
OptCategory[NN_movhlps] = 1;             // Move High to Low Packed Single-FP
OptCategory[NN_movhps] = 1;              // Move High Packed Single-FP
OptCategory[NN_movlhps] = 1;             // Move Low to High Packed Single-FP
OptCategory[NN_movlps] = 1;              // Move Low Packed Single-FP
OptCategory[NN_movmskps] = 1;            // Move Mask to Register
OptCategory[NN_movss] = 9;               // Move Scalar Single-FP
OptCategory[NN_movups] = 9;              // Move Unaligned Four Packed Single-FP
OptCategory[NN_mulps] = 1;               // Packed Single-FP Multiply
OptCategory[NN_mulss] = 1;               // Scalar Single-FP Multiply
OptCategory[NN_orps] = 1;                // Bitwise Logical OR for Single-FP Data
OptCategory[NN_rcpps] = 1;               // Packed Single-FP Reciprocal
OptCategory[NN_rcpss] = 1;               // Scalar Single-FP Reciprocal
OptCategory[NN_rsqrtps] = 1;             // Packed Single-FP Square Root Reciprocal
OptCategory[NN_rsqrtss] = 1;             // Scalar Single-FP Square Root Reciprocal
OptCategory[NN_shufps] = 1;              // Shuffle Single-FP
OptCategory[NN_sqrtps] = 1;              // Packed Single-FP Square Root
OptCategory[NN_sqrtss] = 1;              // Scalar Single-FP Square Root
OptCategory[NN_stmxcsr] = 0;             // Store Streaming SIMD Extensions Technology Control/Status Register    ** Infer dest is 'n'
OptCategory[NN_subps] = 1;               // Packed Single-FP Subtract
OptCategory[NN_subss] = 1;               // Scalar Single-FP Subtract
OptCategory[NN_ucomiss] = 1;             // Scalar Unordered Single-FP Compare and Set EFLAGS
OptCategory[NN_unpckhps] = 1;            // Unpack High Packed Single-FP Data
OptCategory[NN_unpcklps] = 1;            // Unpack Low Packed Single-FP Data
OptCategory[NN_xorps] = 1;               // Bitwise Logical XOR for Single-FP Data
OptCategory[NN_pavgb] = 1;               // Packed Average (Byte)
OptCategory[NN_pavgw] = 1;               // Packed Average (Word)
OptCategory[NN_pextrw] = 2;              // Extract Word
OptCategory[NN_pinsrw] = 1;              // Insert Word
OptCategory[NN_pmaxsw] = 1;              // Packed Signed Integer Word Maximum
OptCategory[NN_pmaxub] = 1;              // Packed Unsigned Integer Byte Maximum
OptCategory[NN_pminsw] = 1;              // Packed Signed Integer Word Minimum
OptCategory[NN_pminub] = 1;              // Packed Unsigned Integer Byte Minimum
OptCategory[NN_pmovmskb] = 1;            // Move Byte Mask to Integer
OptCategory[NN_pmulhuw] = 1;             // Packed Multiply High Unsigned
OptCategory[NN_psadbw] = 1;              // Packed Sum of Absolute Differences
OptCategory[NN_pshufw] = 1;              // Packed Shuffle Word
OptCategory[NN_maskmovq] = 0;            // Byte Mask write   ** Infer dest is 'n'
OptCategory[NN_movntps] = 0;             // Move Aligned Four Packed Single-FP Non Temporal  * infer dest is 'n'
OptCategory[NN_movntq] = 0;              // Move 64 Bits Non Temporal    ** Infer dest is 'n'
OptCategory[NN_prefetcht0] = 1;          // Prefetch to all cache levels
OptCategory[NN_prefetcht1] = 1;          // Prefetch to all cache levels
OptCategory[NN_prefetcht2] = 1;          // Prefetch to L2 cache
OptCategory[NN_prefetchnta] = 1;         // Prefetch to L1 cache
OptCategory[NN_sfence] = 1;              // Store Fence

// Pentium III Pseudo instructions

OptCategory[NN_cmpeqps] = 1;             // Packed Single-FP Compare EQ
OptCategory[NN_cmpltps] = 1;             // Packed Single-FP Compare LT
OptCategory[NN_cmpleps] = 1;             // Packed Single-FP Compare LE
OptCategory[NN_cmpunordps] = 1;          // Packed Single-FP Compare UNORD
OptCategory[NN_cmpneqps] = 1;            // Packed Single-FP Compare NOT EQ
OptCategory[NN_cmpnltps] = 1;            // Packed Single-FP Compare NOT LT
OptCategory[NN_cmpnleps] = 1;            // Packed Single-FP Compare NOT LE
OptCategory[NN_cmpordps] = 1;            // Packed Single-FP Compare ORDERED
OptCategory[NN_cmpeqss] = 1;             // Scalar Single-FP Compare EQ
OptCategory[NN_cmpltss] = 1;             // Scalar Single-FP Compare LT
OptCategory[NN_cmpless] = 1;             // Scalar Single-FP Compare LE
OptCategory[NN_cmpunordss] = 1;          // Scalar Single-FP Compare UNORD
OptCategory[NN_cmpneqss] = 1;            // Scalar Single-FP Compare NOT EQ
OptCategory[NN_cmpnltss] = 1;            // Scalar Single-FP Compare NOT LT
OptCategory[NN_cmpnless] = 1;            // Scalar Single-FP Compare NOT LE
OptCategory[NN_cmpordss] = 1;            // Scalar Single-FP Compare ORDERED

// AMD K7 instructions

// Revisit AMD if we port to it.
OptCategory[NN_pf2iw] = 0;               // Packed Floating-Point to Integer with Sign Extend
OptCategory[NN_pfnacc] = 0;              // Packed Floating-Point Negative Accumulate
OptCategory[NN_pfpnacc] = 0;             // Packed Floating-Point Mixed Positive-Negative Accumulate
OptCategory[NN_pi2fw] = 0;               // Packed 16-bit Integer to Floating-Point
OptCategory[NN_pswapd] = 0;              // Packed Swap Double Word

// Undocumented FP instructions (thanks to norbert.juffa@adm.com)

OptCategory[NN_fstp1] = 9;               // Alias of Store Real and Pop
OptCategory[NN_fcom2] = 1;               // Alias of Compare Real
OptCategory[NN_fcomp3] = 1;              // Alias of Compare Real and Pop
OptCategory[NN_fxch4] = 1;               // Alias of Exchange Registers
OptCategory[NN_fcomp5] = 1;              // Alias of Compare Real and Pop
OptCategory[NN_ffreep] = 1;              // Free Register and Pop
OptCategory[NN_fxch7] = 1;               // Alias of Exchange Registers
OptCategory[NN_fstp8] = 9;               // Alias of Store Real and Pop
OptCategory[NN_fstp9] = 9;               // Alias of Store Real and Pop

// Pentium 4 instructions

OptCategory[NN_addpd] = 1;               // Add Packed Double-Precision Floating-Point Values
OptCategory[NN_addsd] = 1;               // Add Scalar Double-Precision Floating-Point Values
OptCategory[NN_andnpd] = 1;              // Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
OptCategory[NN_andpd] = 1;               // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
OptCategory[NN_clflush] = 1;             // Flush Cache Line
OptCategory[NN_cmppd] = 1;               // Compare Packed Double-Precision Floating-Point Values
OptCategory[NN_cmpsd] = 1;               // Compare Scalar Double-Precision Floating-Point Values
OptCategory[NN_comisd] = 1;              // Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
OptCategory[NN_cvtdq2pd] = 1;            // Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
OptCategory[NN_cvtdq2ps] = 1;            // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
OptCategory[NN_cvtpd2dq] = 1;            // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
OptCategory[NN_cvtpd2pi] = 1;            // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
OptCategory[NN_cvtpd2ps] = 1;            // Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
OptCategory[NN_cvtpi2pd] = 1;            // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
OptCategory[NN_cvtps2dq] = 1;            // Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
OptCategory[NN_cvtps2pd] = 1;            // Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
OptCategory[NN_cvtsd2si] = 2;            // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
OptCategory[NN_cvtsd2ss] = 1;            // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
OptCategory[NN_cvtsi2sd] = 1;            // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
OptCategory[NN_cvtss2sd] = 1;            // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
OptCategory[NN_cvttpd2dq] = 1;           // Convert With Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
OptCategory[NN_cvttpd2pi] = 1;           // Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
OptCategory[NN_cvttps2dq] = 1;           // Convert With Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
OptCategory[NN_cvttsd2si] = 2;           // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
OptCategory[NN_divpd] = 1;               // Divide Packed Double-Precision Floating-Point Values
OptCategory[NN_divsd] = 1;               // Divide Scalar Double-Precision Floating-Point Values
OptCategory[NN_lfence] = 1;              // Load Fence
OptCategory[NN_maskmovdqu] = 0;          // Store Selected Bytes of Double Quadword  ** Infer dest is 'n'
OptCategory[NN_maxpd] = 1;               // Return Maximum Packed Double-Precision Floating-Point Values
OptCategory[NN_maxsd] = 1;               // Return Maximum Scalar Double-Precision Floating-Point Value
OptCategory[NN_mfence] = 1;              // Memory Fence
OptCategory[NN_minpd] = 1;               // Return Minimum Packed Double-Precision Floating-Point Values
OptCategory[NN_minsd] = 1;               // Return Minimum Scalar Double-Precision Floating-Point Value
OptCategory[NN_movapd] = 9;              // Move Aligned Packed Double-Precision Floating-Point Values  ** Infer dest is 'n'
OptCategory[NN_movdq2q] = 1;             // Move Quadword from XMM to MMX Register
OptCategory[NN_movdqa] = 9;              // Move Aligned Double Quadword  ** Infer dest is 'n'
OptCategory[NN_movdqu] = 9;              // Move Unaligned Double Quadword  ** Infer dest is 'n'
OptCategory[NN_movhpd] = 9;              // Move High Packed Double-Precision Floating-Point Values  ** Infer dest is 'n'
OptCategory[NN_movlpd] = 9;              // Move Low Packed Double-Precision Floating-Point Values  ** Infer dest is 'n'
OptCategory[NN_movmskpd] = 2;            // Extract Packed Double-Precision Floating-Point Sign Mask
OptCategory[NN_movntdq] = 0;             // Store Double Quadword Using Non-Temporal Hint
OptCategory[NN_movnti] = 0;              // Store Doubleword Using Non-Temporal Hint
OptCategory[NN_movntpd] = 0;             // Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
OptCategory[NN_movq2dq] = 1;             // Move Quadword from MMX to XMM Register
OptCategory[NN_movsd] = 9;               // Move Scalar Double-Precision Floating-Point Values
OptCategory[NN_movupd] = 9;              // Move Unaligned Packed Double-Precision Floating-Point Values
OptCategory[NN_mulpd] = 1;               // Multiply Packed Double-Precision Floating-Point Values
OptCategory[NN_mulsd] = 1;               // Multiply Scalar Double-Precision Floating-Point Values
OptCategory[NN_orpd] = 1;                // Bitwise Logical OR of Double-Precision Floating-Point Values
OptCategory[NN_paddq] = 1;               // Add Packed Quadword Integers
OptCategory[NN_pause] = 1;               // Spin Loop Hint
OptCategory[NN_pmuludq] = 1;             // Multiply Packed Unsigned Doubleword Integers
OptCategory[NN_pshufd] = 1;              // Shuffle Packed Doublewords
OptCategory[NN_pshufhw] = 1;             // Shuffle Packed High Words
OptCategory[NN_pshuflw] = 1;             // Shuffle Packed Low Words
OptCategory[NN_pslldq] = 1;              // Shift Double Quadword Left Logical
OptCategory[NN_psrldq] = 1;              // Shift Double Quadword Right Logical
OptCategory[NN_psubq] = 1;               // Subtract Packed Quadword Integers
OptCategory[NN_punpckhqdq] = 1;          // Unpack High Data
OptCategory[NN_punpcklqdq] = 1;          // Unpack Low Data
OptCategory[NN_shufpd] = 1;              // Shuffle Packed Double-Precision Floating-Point Values
OptCategory[NN_sqrtpd] = 1;              // Compute Square Roots of Packed Double-Precision Floating-Point Values
OptCategory[NN_sqrtsd] = 1;              // Compute Square Rootof Scalar Double-Precision Floating-Point Value
OptCategory[NN_subpd] = 1;               // Subtract Packed Double-Precision Floating-Point Values
OptCategory[NN_subsd] = 1;               // Subtract Scalar Double-Precision Floating-Point Values
OptCategory[NN_ucomisd] = 1;             // Unordered Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
OptCategory[NN_unpckhpd] = 1;            // Unpack and Interleave High Packed Double-Precision Floating-Point Values
OptCategory[NN_unpcklpd] = 1;            // Unpack and Interleave Low Packed Double-Precision Floating-Point Values
OptCategory[NN_xorpd] = 1;               // Bitwise Logical OR of Double-Precision Floating-Point Values


// AMD syscall/sysret instructions  NOTE: not AMD, found in Intel manual

OptCategory[NN_syscall] = 1;             // Low latency system call
OptCategory[NN_sysret] = 1;              // Return from system call

// AMD64 instructions    NOTE: not AMD, found in Intel manual

OptCategory[NN_swapgs] = 1;              // Exchange GS base with KernelGSBase MSR

// New Pentium instructions (SSE3)

OptCategory[NN_movddup] = 9;             // Move One Double-FP and Duplicate
OptCategory[NN_movshdup] = 9;            // Move Packed Single-FP High and Duplicate
OptCategory[NN_movsldup] = 9;            // Move Packed Single-FP Low and Duplicate

// Missing AMD64 instructions  NOTE: also found in Intel manual

OptCategory[NN_movsxd] = 2;              // Move with Sign-Extend Doubleword
OptCategory[NN_cmpxchg16b] = 0;          // Compare and Exchange 16 Bytes

// SSE3 instructions

OptCategory[NN_addsubpd] = 1;            // Add /Sub packed DP FP numbers
OptCategory[NN_addsubps] = 1;            // Add /Sub packed SP FP numbers
OptCategory[NN_haddpd] = 1;              // Add horizontally packed DP FP numbers
OptCategory[NN_haddps] = 1;              // Add horizontally packed SP FP numbers
OptCategory[NN_hsubpd] = 1;              // Sub horizontally packed DP FP numbers
OptCategory[NN_hsubps] = 1;              // Sub horizontally packed SP FP numbers
OptCategory[NN_monitor] = 1;             // Set up a linear address range to be monitored by hardware
OptCategory[NN_mwait] = 1;               // Wait until write-back store performed within the range specified by the MONITOR instruction
OptCategory[NN_fisttp] = 0;              // Store ST in intXX (chop) and pop
OptCategory[NN_lddqu] = 1;               // Load unaligned integer 128-bit

// SSSE3 instructions

OptCategory[NN_psignb] = 1;              // Packed SIGN Byte
OptCategory[NN_psignw] = 1;              // Packed SIGN Word
OptCategory[NN_psignd] = 1;              // Packed SIGN Doubleword
OptCategory[NN_pshufb] = 1;              // Packed Shuffle Bytes
OptCategory[NN_pmulhrsw] = 1;            // Packed Multiply High with Round and Scale
OptCategory[NN_pmaddubsw] = 1;           // Multiply and Add Packed Signed and Unsigned Bytes
OptCategory[NN_phsubsw] = 1;             // Packed Horizontal Subtract and Saturate
OptCategory[NN_phaddsw] = 1;             // Packed Horizontal Add and Saturate
OptCategory[NN_phaddw] = 1;              // Packed Horizontal Add Word
OptCategory[NN_phaddd] = 1;              // Packed Horizontal Add Doubleword
OptCategory[NN_phsubw] = 1;              // Packed Horizontal Subtract Word
OptCategory[NN_phsubd] = 1;              // Packed Horizontal Subtract Doubleword
OptCategory[NN_palignr] = 1;             // Packed Align Right
OptCategory[NN_pabsb] = 1;               // Packed Absolute Value Byte
OptCategory[NN_pabsw] = 1;               // Packed Absolute Value Word
OptCategory[NN_pabsd] = 1;               // Packed Absolute Value Doubleword

// VMX instructions

OptCategory[NN_vmcall] = 1;              // Call to VM Monitor
OptCategory[NN_vmclear] = 0;             // Clear Virtual Machine Control Structure
OptCategory[NN_vmlaunch] = 1;            // Launch Virtual Machine
OptCategory[NN_vmresume] = 1;            // Resume Virtual Machine
OptCategory[NN_vmptrld] = 6;             // Load Pointer to Virtual Machine Control Structure
OptCategory[NN_vmptrst] = 0;             // Store Pointer to Virtual Machine Control Structure
OptCategory[NN_vmread] = 0;              // Read Field from Virtual Machine Control Structure
OptCategory[NN_vmwrite] = 0;             // Write Field from Virtual Machine Control Structure
OptCategory[NN_vmxoff] = 1;              // Leave VMX Operation
OptCategory[NN_vmxon] = 1;               // Enter VMX Operation

#if 599 < IDA_SDK_VERSION

OptCategory[NN_ud2] = 1;                 // Undefined Instruction

// Added with x86-64

OptCategory[NN_rdtscp] = 10;             // Read Time-Stamp Counter and Processor ID

// Geode LX 3DNow! extensions

OptCategory[NN_pfrcpv] = 1;              // Reciprocal Approximation for a Pair of 32-bit Floats
OptCategory[NN_pfrsqrtv] = 1;            // Reciprocal Square Root Approximation for a Pair of 32-bit Floats

// SSE2 pseudoinstructions

OptCategory[NN_cmpeqpd] = 1;             // Packed Double-FP Compare EQ
OptCategory[NN_cmpltpd] = 1;             // Packed Double-FP Compare LT
OptCategory[NN_cmplepd] = 1;             // Packed Double-FP Compare LE
OptCategory[NN_cmpunordpd] = 1;          // Packed Double-FP Compare UNORD
OptCategory[NN_cmpneqpd] = 1;            // Packed Double-FP Compare NOT EQ
OptCategory[NN_cmpnltpd] = 1;            // Packed Double-FP Compare NOT LT
OptCategory[NN_cmpnlepd] = 1;            // Packed Double-FP Compare NOT LE
OptCategory[NN_cmpordpd] = 1;            // Packed Double-FP Compare ORDERED
OptCategory[NN_cmpeqsd] = 1;             // Scalar Double-FP Compare EQ
OptCategory[NN_cmpltsd] = 1;             // Scalar Double-FP Compare LT
OptCategory[NN_cmplesd] = 1;             // Scalar Double-FP Compare LE
OptCategory[NN_cmpunordsd] = 1;          // Scalar Double-FP Compare UNORD
OptCategory[NN_cmpneqsd] = 1;            // Scalar Double-FP Compare NOT EQ
OptCategory[NN_cmpnltsd] = 1;            // Scalar Double-FP Compare NOT LT
OptCategory[NN_cmpnlesd] = 1;            // Scalar Double-FP Compare NOT LE
OptCategory[NN_cmpordsd] = 1;            // Scalar Double-FP Compare ORDERED

// SSSE4.1 instructions

OptCategory[NN_blendpd] = 1;              // Blend Packed Double Precision Floating-Point Values
OptCategory[NN_blendps] = 1;              // Blend Packed Single Precision Floating-Point Values
OptCategory[NN_blendvpd] = 1;             // Variable Blend Packed Double Precision Floating-Point Values
OptCategory[NN_blendvps] = 1;             // Variable Blend Packed Single Precision Floating-Point Values
OptCategory[NN_dppd] = 1;                 // Dot Product of Packed Double Precision Floating-Point Values
OptCategory[NN_dpps] = 1;                 // Dot Product of Packed Single Precision Floating-Point Values
OptCategory[NN_extractps] = 2;            // Extract Packed Single Precision Floating-Point Value
OptCategory[NN_insertps] = 1;             // Insert Packed Single Precision Floating-Point Value
OptCategory[NN_movntdqa] = 0;             // Load Double Quadword Non-Temporal Aligned Hint
OptCategory[NN_mpsadbw] = 1;              // Compute Multiple Packed Sums of Absolute Difference
OptCategory[NN_packusdw] = 1;             // Pack with Unsigned Saturation
OptCategory[NN_pblendvb] = 1;             // Variable Blend Packed Bytes
OptCategory[NN_pblendw] = 1;              // Blend Packed Words
OptCategory[NN_pcmpeqq] = 1;              // Compare Packed Qword Data for Equal
OptCategory[NN_pextrb] = 1;               // Extract Byte
OptCategory[NN_pextrd] = 1;               // Extract Dword
OptCategory[NN_pextrq] = 1;               // Extract Qword
OptCategory[NN_phminposuw] = 1;           // Packed Horizontal Word Minimum
OptCategory[NN_pinsrb] = 1;               // Insert Byte 
OptCategory[NN_pinsrd] = 1;               // Insert Dword
OptCategory[NN_pinsrq] = 1;               // Insert Qword
OptCategory[NN_pmaxsb] = 1;               // Maximum of Packed Signed Byte Integers
OptCategory[NN_pmaxsd] = 1;               // Maximum of Packed Signed Dword Integers
OptCategory[NN_pmaxud] = 1;               // Maximum of Packed Unsigned Dword Integers
OptCategory[NN_pmaxuw] = 1;               // Maximum of Packed Word Integers
OptCategory[NN_pminsb] = 1;               // Minimum of Packed Signed Byte Integers
OptCategory[NN_pminsd] = 1;               // Minimum of Packed Signed Dword Integers
OptCategory[NN_pminud] = 1;               // Minimum of Packed Unsigned Dword Integers
OptCategory[NN_pminuw] = 1;               // Minimum of Packed Word Integers
OptCategory[NN_pmovsxbw] = 1;             // Packed Move with Sign Extend
OptCategory[NN_pmovsxbd] = 1;             // Packed Move with Sign Extend
OptCategory[NN_pmovsxbq] = 1;             // Packed Move with Sign Extend
OptCategory[NN_pmovsxwd] = 1;             // Packed Move with Sign Extend
OptCategory[NN_pmovsxwq] = 1;             // Packed Move with Sign Extend
OptCategory[NN_pmovsxdq] = 1;             // Packed Move with Sign Extend
OptCategory[NN_pmovzxbw] = 1;             // Packed Move with Zero Extend
OptCategory[NN_pmovzxbd] = 1;             // Packed Move with Zero Extend
OptCategory[NN_pmovzxbq] = 1;             // Packed Move with Zero Extend
OptCategory[NN_pmovzxwd] = 1;             // Packed Move with Zero Extend
OptCategory[NN_pmovzxwq] = 1;             // Packed Move with Zero Extend
OptCategory[NN_pmovzxdq] = 1;             // Packed Move with Zero Extend
OptCategory[NN_pmuldq] = 1;               // Multiply Packed Signed Dword Integers
OptCategory[NN_pmulld] = 1;               // Multiply Packed Signed Dword Integers and Store Low Result
OptCategory[NN_ptest] = 1;                // Logical Compare
OptCategory[NN_roundpd] = 1;              // Round Packed Double Precision Floating-Point Values
OptCategory[NN_roundps] = 1;              // Round Packed Single Precision Floating-Point Values
OptCategory[NN_roundsd] = 1;              // Round Scalar Double Precision Floating-Point Values
OptCategory[NN_roundss] = 1;              // Round Scalar Single Precision Floating-Point Values

// SSSE4.2 instructions
OptCategory[NN_crc32] = 2;                // Accumulate CRC32 Value
OptCategory[NN_pcmpestri] = 2;            // Packed Compare Explicit Length Strings, Return Index
OptCategory[NN_pcmpestrm] = 2;            // Packed Compare Explicit Length Strings, Return Mask
OptCategory[NN_pcmpistri] = 2;            // Packed Compare Implicit Length Strings, Return Index
OptCategory[NN_pcmpistrm] = 2;            // Packed Compare Implicit Length Strings, Return Mask
OptCategory[NN_pcmpgtq] = 1;              // Compare Packed Data for Greater Than
OptCategory[NN_popcnt] = 2;               // Return the Count of Number of Bits Set to 1

// AMD SSE4a instructions

OptCategory[NN_extrq] = 1;                // Extract Field From Register
OptCategory[NN_insertq] = 1;              // Insert Field
OptCategory[NN_movntsd] = 0;              // Move Non-Temporal Scalar Double-Precision Floating-Point
OptCategory[NN_movntss] = 0;              // Move Non-Temporal Scalar Single-Precision Floating-Point
OptCategory[NN_lzcnt] = 2;                // Leading Zero Count

// xsave/xrstor instructions

OptCategory[NN_xgetbv] = 8;               // Get Value of Extended Control Register
OptCategory[NN_xrstor] = 0;               // Restore Processor Extended States
OptCategory[NN_xsave] = 1;                // Save Processor Extended States
OptCategory[NN_xsetbv] = 1;               // Set Value of Extended Control Register

// Intel Safer Mode Extensions (SMX)

OptCategory[NN_getsec] = 1;               // Safer Mode Extensions (SMX) Instruction

// AMD-V Virtualization ISA Extension

OptCategory[NN_clgi] = 0;                 // Clear Global Interrupt Flag
OptCategory[NN_invlpga] = 1;              // Invalidate TLB Entry in a Specified ASID
OptCategory[NN_skinit] = 1;               // Secure Init and Jump with Attestation
OptCategory[NN_stgi] = 0;                 // Set Global Interrupt Flag
OptCategory[NN_vmexit] = 1;               // Stop Executing Guest, Begin Executing Host
OptCategory[NN_vmload] = 0;               // Load State from VMCB
OptCategory[NN_vmmcall] = 1;              // Call VMM
OptCategory[NN_vmrun] = 1;                // Run Virtual Machine
OptCategory[NN_vmsave] = 0;               // Save State to VMCB

// VMX+ instructions

OptCategory[NN_invept] = 1;               // Invalidate Translations Derived from EPT
OptCategory[NN_invvpid] = 1;              // Invalidate Translations Based on VPID

// Intel Atom instructions

OptCategory[NN_movbe] = 3;                // Move Data After Swapping Bytes

// Intel AES instructions

OptCategory[NN_aesenc] = 1;                // Perform One Round of an AES Encryption Flow
OptCategory[NN_aesenclast] = 1;            // Perform the Last Round of an AES Encryption Flow
OptCategory[NN_aesdec] = 1;                // Perform One Round of an AES Decryption Flow
OptCategory[NN_aesdeclast] = 1;            // Perform the Last Round of an AES Decryption Flow
OptCategory[NN_aesimc] = 1;                // Perform the AES InvMixColumn Transformation
OptCategory[NN_aeskeygenassist] = 1;       // AES Round Key Generation Assist

// Carryless multiplication

OptCategory[NN_pclmulqdq] = 1;            // Carry-Less Multiplication Quadword

// Returns modified by operand size prefixes

OptCategory[NN_retnw] = 0;               // Return Near from Procedure (use16)
OptCategory[NN_retnd] = 0;               // Return Near from Procedure (use32)
OptCategory[NN_retnq] = 0;               // Return Near from Procedure (use64)
OptCategory[NN_retfw] = 0;               // Return Far from Procedure (use16)
OptCategory[NN_retfd] = 0;               // Return Far from Procedure (use32)
OptCategory[NN_retfq] = 0;               // Return Far from Procedure (use64)

// RDRAND support

OptCategory[NN_rdrand] = 2;               // Read Random Number

// new GPR instructions

OptCategory[NN_adcx] = 5;                 // Unsigned Integer Addition of Two Operands with Carry Flag
OptCategory[NN_adox] = 5;                 // Unsigned Integer Addition of Two Operands with Overflow Flag
OptCategory[NN_andn] = 0;                 // Logical AND NOT
OptCategory[NN_bextr] = 2;                // Bit Field Extract
OptCategory[NN_blsi] = 2;                 // Extract Lowest Set Isolated Bit
OptCategory[NN_blsmsk] = 2;               // Get Mask Up to Lowest Set Bit
OptCategory[NN_blsr] = 2;                 // Reset Lowest Set Bit
OptCategory[NN_bzhi] = 2;                 // Zero High Bits Starting with Specified Bit Position
OptCategory[NN_clac] = 1;                 // Clear AC Flag in EFLAGS Register
OptCategory[NN_mulx] = 2;                 // Unsigned Multiply Without Affecting Flags
OptCategory[NN_pdep] = 2;                 // Parallel Bits Deposit
OptCategory[NN_pext] = 2;                 // Parallel Bits Extract
OptCategory[NN_rorx] = 2;                 // Rotate Right Logical Without Affecting Flags
OptCategory[NN_sarx] = 2;                 // Shift Arithmetically Right Without Affecting Flags
OptCategory[NN_shlx] = 2;                 // Shift Logically Left Without Affecting Flags
OptCategory[NN_shrx] = 2;                 // Shift Logically Right Without Affecting Flags
OptCategory[NN_stac] = 1;                  // Set AC Flag in EFLAGS Register
OptCategory[NN_tzcnt] = 2;                // Count the Number of Trailing Zero Bits
OptCategory[NN_xsaveopt] = 1;             // Save Processor Extended States Optimized
OptCategory[NN_invpcid] = 1;              // Invalidate Processor Context ID
OptCategory[NN_rdseed] = 2;               // Read Random Seed
OptCategory[NN_rdfsbase] = 6;             // Read FS Segment Base
OptCategory[NN_rdgsbase] = 6;             // Read GS Segment Base
OptCategory[NN_wrfsbase] = 6;             // Write FS Segment Base
OptCategory[NN_wrgsbase] = 6;             // Write GS Segment Base

// new AVX instructions

OptCategory[NN_vaddpd] = 1;               // Add Packed Double-Precision Floating-Point Values
OptCategory[NN_vaddps] = 1;               // Packed Single-FP Add
OptCategory[NN_vaddsd] = 1;               // Add Scalar Double-Precision Floating-Point Values
OptCategory[NN_vaddss] = 1;               // Scalar Single-FP Add
OptCategory[NN_vaddsubpd] = 1;            // Add /Sub packed DP FP numbers
OptCategory[NN_vaddsubps] = 1;            // Add /Sub packed SP FP numbers
OptCategory[NN_vaesdec] = 1;              // Perform One Round of an AES Decryption Flow
OptCategory[NN_vaesdeclast] = 1;          // Perform the Last Round of an AES Decryption Flow
OptCategory[NN_vaesenc] = 1;              // Perform One Round of an AES Encryption Flow
OptCategory[NN_vaesenclast] = 1;          // Perform the Last Round of an AES Encryption Flow
OptCategory[NN_vaesimc] = 1;              // Perform the AES InvMixColumn Transformation
OptCategory[NN_vaeskeygenassist] = 1;     // AES Round Key Generation Assist
OptCategory[NN_vandnpd] = 1;              // Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
OptCategory[NN_vandnps] = 1;              // Bitwise Logical And Not for Single-FP
OptCategory[NN_vandpd] = 1;               // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
OptCategory[NN_vandps] = 1;               // Bitwise Logical And for Single-FP
OptCategory[NN_vblendpd] = 1;             // Blend Packed Double Precision Floating-Point Values
OptCategory[NN_vblendps] = 1;             // Blend Packed Single Precision Floating-Point Values
OptCategory[NN_vblendvpd] = 1;            // Variable Blend Packed Double Precision Floating-Point Values
OptCategory[NN_vblendvps] = 1;            // Variable Blend Packed Single Precision Floating-Point Values
OptCategory[NN_vbroadcastf128] = 1;       // Broadcast 128 Bits of Floating-Point Data
OptCategory[NN_vbroadcasti128] = 1;       // Broadcast 128 Bits of Integer Data
OptCategory[NN_vbroadcastsd] = 1;         // Broadcast Double-Precision Floating-Point Element
OptCategory[NN_vbroadcastss] = 1;         // Broadcast Single-Precision Floating-Point Element
OptCategory[NN_vcmppd] = 1;               // Compare Packed Double-Precision Floating-Point Values
OptCategory[NN_vcmpps] = 1;               // Packed Single-FP Compare
OptCategory[NN_vcmpsd] = 1;               // Compare Scalar Double-Precision Floating-Point Values
OptCategory[NN_vcmpss] = 1;               // Scalar Single-FP Compare
OptCategory[NN_vcomisd] = 1;              // Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
OptCategory[NN_vcomiss] = 1;              // Scalar Ordered Single-FP Compare and Set EFLAGS
OptCategory[NN_vcvtdq2pd] = 1;            // Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
OptCategory[NN_vcvtdq2ps] = 1;            // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
OptCategory[NN_vcvtpd2dq] = 1;            // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
OptCategory[NN_vcvtpd2ps] = 1;            // Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
OptCategory[NN_vcvtph2ps] = 1;            // Convert 16-bit FP Values to Single-Precision FP Values
OptCategory[NN_vcvtps2dq] = 1;            // Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
OptCategory[NN_vcvtps2pd] = 1;            // Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
OptCategory[NN_vcvtps2ph] = 1;            // Convert Single-Precision FP value to 16-bit FP value
OptCategory[NN_vcvtsd2si] = 1;            // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
OptCategory[NN_vcvtsd2ss] = 1;            // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
OptCategory[NN_vcvtsi2sd] = 1;            // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
OptCategory[NN_vcvtsi2ss] = 1;            // Scalar signed INT32 to Single-FP conversion
OptCategory[NN_vcvtss2sd] = 1;            // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
OptCategory[NN_vcvtss2si] = 1;            // Scalar Single-FP to signed INT32 conversion
OptCategory[NN_vcvttpd2dq] = 1;           // Convert With Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
OptCategory[NN_vcvttps2dq] = 1;           // Convert With Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
OptCategory[NN_vcvttsd2si] = 1;           // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
OptCategory[NN_vcvttss2si] = 1;           // Scalar Single-FP to signed INT32 conversion (truncate)
OptCategory[NN_vdivpd] = 1;               // Divide Packed Double-Precision Floating-Point Values
OptCategory[NN_vdivps] = 1;               // Packed Single-FP Divide
OptCategory[NN_vdivsd] = 1;               // Divide Scalar Double-Precision Floating-Point Values
OptCategory[NN_vdivss] = 1;               // Scalar Single-FP Divide
OptCategory[NN_vdppd] = 1;                // Dot Product of Packed Double Precision Floating-Point Values
OptCategory[NN_vdpps] = 1;                // Dot Product of Packed Single Precision Floating-Point Values
OptCategory[NN_vextractf128] = 1;         // Extract Packed Floating-Point Values
OptCategory[NN_vextracti128] = 1;         // Extract Packed Integer Values
OptCategory[NN_vextractps] = 1;           // Extract Packed Floating-Point Values
OptCategory[NN_vfmadd132pd] = 1;          // Fused Multiply-Add of Packed Double-Precision Floating-Point Values
OptCategory[NN_vfmadd132ps] = 1;          // Fused Multiply-Add of Packed Single-Precision Floating-Point Values
OptCategory[NN_vfmadd132sd] = 1;          // Fused Multiply-Add of Scalar Double-Precision Floating-Point Values
OptCategory[NN_vfmadd132ss] = 1;          // Fused Multiply-Add of Scalar Single-Precision Floating-Point Values
OptCategory[NN_vfmadd213pd] = 1;          // Fused Multiply-Add of Packed Double-Precision Floating-Point Values
OptCategory[NN_vfmadd213ps] = 1;          // Fused Multiply-Add of Packed Single-Precision Floating-Point Values
OptCategory[NN_vfmadd213sd] = 1;          // Fused Multiply-Add of Scalar Double-Precision Floating-Point Values
OptCategory[NN_vfmadd213ss] = 1;          // Fused Multiply-Add of Scalar Single-Precision Floating-Point Values
OptCategory[NN_vfmadd231pd] = 1;          // Fused Multiply-Add of Packed Double-Precision Floating-Point Values
OptCategory[NN_vfmadd231ps] = 1;          // Fused Multiply-Add of Packed Single-Precision Floating-Point Values
OptCategory[NN_vfmadd231sd] = 1;          // Fused Multiply-Add of Scalar Double-Precision Floating-Point Values
OptCategory[NN_vfmadd231ss] = 1;          // Fused Multiply-Add of Scalar Single-Precision Floating-Point Values
OptCategory[NN_vfmaddsub132pd] = 1;       // Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values
OptCategory[NN_vfmaddsub132ps] = 1;       // Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
OptCategory[NN_vfmaddsub213pd] = 1;       // Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values
OptCategory[NN_vfmaddsub213ps] = 1;       // Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
OptCategory[NN_vfmaddsub231pd] = 1;       // Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values
OptCategory[NN_vfmaddsub231ps] = 1;       // Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
OptCategory[NN_vfmsub132pd] = 1;          // Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
OptCategory[NN_vfmsub132ps] = 1;          // Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
OptCategory[NN_vfmsub132sd] = 1;          // Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
OptCategory[NN_vfmsub132ss] = 1;          // Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
OptCategory[NN_vfmsub213pd] = 1;          // Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
OptCategory[NN_vfmsub213ps] = 1;          // Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
OptCategory[NN_vfmsub213sd] = 1;          // Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
OptCategory[NN_vfmsub213ss] = 1;          // Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
OptCategory[NN_vfmsub231pd] = 1;          // Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
OptCategory[NN_vfmsub231ps] = 1;          // Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
OptCategory[NN_vfmsub231sd] = 1;          // Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
OptCategory[NN_vfmsub231ss] = 1;          // Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
OptCategory[NN_vfmsubadd132pd] = 1;       // Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
OptCategory[NN_vfmsubadd132ps] = 1;       // Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
OptCategory[NN_vfmsubadd213pd] = 1;       // Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
OptCategory[NN_vfmsubadd213ps] = 1;       // Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
OptCategory[NN_vfmsubadd231pd] = 1;       // Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
OptCategory[NN_vfmsubadd231ps] = 1;       // Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
OptCategory[NN_vfnmadd132pd] = 1;         // Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
OptCategory[NN_vfnmadd132ps] = 1;         // Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
OptCategory[NN_vfnmadd132sd] = 1;         // Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
OptCategory[NN_vfnmadd132ss] = 1;         // Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
OptCategory[NN_vfnmadd213pd] = 1;         // Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
OptCategory[NN_vfnmadd213ps] = 1;         // Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
OptCategory[NN_vfnmadd213sd] = 1;         // Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
OptCategory[NN_vfnmadd213ss] = 1;         // Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
OptCategory[NN_vfnmadd231pd] = 1;         // Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
OptCategory[NN_vfnmadd231ps] = 1;         // Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
OptCategory[NN_vfnmadd231sd] = 1;         // Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
OptCategory[NN_vfnmadd231ss] = 1;         // Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
OptCategory[NN_vfnmsub132pd] = 1;         // Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values
OptCategory[NN_vfnmsub132ps] = 1;         // Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values
OptCategory[NN_vfnmsub132sd] = 1;         // Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values
OptCategory[NN_vfnmsub132ss] = 1;         // Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values
OptCategory[NN_vfnmsub213pd] = 1;         // Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values
OptCategory[NN_vfnmsub213ps] = 1;         // Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values
OptCategory[NN_vfnmsub213sd] = 1;         // Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values
OptCategory[NN_vfnmsub213ss] = 1;         // Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values
OptCategory[NN_vfnmsub231pd] = 1;         // Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values
OptCategory[NN_vfnmsub231ps] = 1;         // Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values
OptCategory[NN_vfnmsub231sd] = 1;         // Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values
OptCategory[NN_vfnmsub231ss] = 1;         // Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values
OptCategory[NN_vgatherdps] = 1;           // Gather Packed SP FP Values Using Signed Dword Indices
OptCategory[NN_vgatherdpd] = 1;           // Gather Packed DP FP Values Using Signed Dword Indices
OptCategory[NN_vgatherqps] = 1;           // Gather Packed SP FP Values Using Signed Qword Indices
OptCategory[NN_vgatherqpd] = 1;           // Gather Packed DP FP Values Using Signed Qword Indices
OptCategory[NN_vhaddpd] = 1;              // Add horizontally packed DP FP numbers
OptCategory[NN_vhaddps] = 1;              // Add horizontally packed SP FP numbers
OptCategory[NN_vhsubpd] = 1;              // Sub horizontally packed DP FP numbers
OptCategory[NN_vhsubps] = 1;              // Sub horizontally packed SP FP numbers
OptCategory[NN_vinsertf128] = 1;          // Insert Packed Floating-Point Values
OptCategory[NN_vinserti128] = 1;          // Insert Packed Integer Values
OptCategory[NN_vinsertps] = 1;            // Insert Packed Single Precision Floating-Point Value
OptCategory[NN_vlddqu] = 1;               // Load Unaligned Packed Integer Values
OptCategory[NN_vldmxcsr] = 1;             // Load Streaming SIMD Extensions Technology Control/Status Register
OptCategory[NN_vmaskmovdqu] = 9;          // Store Selected Bytes of Double Quadword with NT Hint
OptCategory[NN_vmaskmovpd] = 9;           // Conditionally Load Packed Double-Precision Floating-Point Values
OptCategory[NN_vmaskmovps] = 9;           // Conditionally Load Packed Single-Precision Floating-Point Values
OptCategory[NN_vmaxpd] = 1;               // Return Maximum Packed Double-Precision Floating-Point Values
OptCategory[NN_vmaxps] = 1;               // Packed Single-FP Maximum
OptCategory[NN_vmaxsd] = 1;               // Return Maximum Scalar Double-Precision Floating-Point Value
OptCategory[NN_vmaxss] = 1;               // Scalar Single-FP Maximum
OptCategory[NN_vminpd] = 1;               // Return Minimum Packed Double-Precision Floating-Point Values
OptCategory[NN_vminps] = 1;               // Packed Single-FP Minimum
OptCategory[NN_vminsd] = 1;               // Return Minimum Scalar Double-Precision Floating-Point Value
OptCategory[NN_vminss] = 1;               // Scalar Single-FP Minimum
OptCategory[NN_vmovapd] = 9;              // Move Aligned Packed Double-Precision Floating-Point Values
OptCategory[NN_vmovaps] = 9;              // Move Aligned Four Packed Single-FP
OptCategory[NN_vmovd] = 9;                // Move 32 bits
OptCategory[NN_vmovddup] = 1;             // Move One Double-FP and Duplicate
OptCategory[NN_vmovdqa] = 1;              // Move Aligned Double Quadword
OptCategory[NN_vmovdqu] = 1;              // Move Unaligned Double Quadword
OptCategory[NN_vmovhlps] = 1;             // Move High to Low Packed Single-FP
OptCategory[NN_vmovhpd] = 1;              // Move High Packed Double-Precision Floating-Point Values
OptCategory[NN_vmovhps] = 1;              // Move High Packed Single-FP
OptCategory[NN_vmovlhps] = 1;             // Move Low to High Packed Single-FP
OptCategory[NN_vmovlpd] = 1;              // Move Low Packed Double-Precision Floating-Point Values
OptCategory[NN_vmovlps] = 1;              // Move Low Packed Single-FP
OptCategory[NN_vmovmskpd] = 1;            // Extract Packed Double-Precision Floating-Point Sign Mask
OptCategory[NN_vmovmskps] = 1;            // Move Mask to Register
OptCategory[NN_vmovntdq] = 1;             // Store Double Quadword Using Non-Temporal Hint
OptCategory[NN_vmovntdqa] = 1;            // Load Double Quadword Non-Temporal Aligned Hint
OptCategory[NN_vmovntpd] = 1;             // Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
OptCategory[NN_vmovntps] = 1;             // Move Aligned Four Packed Single-FP Non Temporal
OptCategory[NN_vmovntsd] = 1;             // Move Non-Temporal Scalar Double-Precision Floating-Point
OptCategory[NN_vmovntss] = 1;             // Move Non-Temporal Scalar Single-Precision Floating-Point
OptCategory[NN_vmovq] = 1;                // Move 64 bits
OptCategory[NN_vmovsd] = 1;               // Move Scalar Double-Precision Floating-Point Values
OptCategory[NN_vmovshdup] = 1;            // Move Packed Single-FP High and Duplicate
OptCategory[NN_vmovsldup] = 1;            // Move Packed Single-FP Low and Duplicate
OptCategory[NN_vmovss] = 1;               // Move Scalar Single-FP
OptCategory[NN_vmovupd] = 1;              // Move Unaligned Packed Double-Precision Floating-Point Values
OptCategory[NN_vmovups] = 1;              // Move Unaligned Four Packed Single-FP
OptCategory[NN_vmpsadbw] = 1;             // Compute Multiple Packed Sums of Absolute Difference
OptCategory[NN_vmulpd] = 1;               // Multiply Packed Double-Precision Floating-Point Values
OptCategory[NN_vmulps] = 1;               // Packed Single-FP Multiply
OptCategory[NN_vmulsd] = 1;               // Multiply Scalar Double-Precision Floating-Point Values
OptCategory[NN_vmulss] = 1;               // Scalar Single-FP Multiply
OptCategory[NN_vorpd] = 1;                // Bitwise Logical OR of Double-Precision Floating-Point Values
OptCategory[NN_vorps] = 1;                // Bitwise Logical OR for Single-FP Data
OptCategory[NN_vpabsb] = 1;               // Packed Absolute Value Byte
OptCategory[NN_vpabsd] = 1;               // Packed Absolute Value Doubleword
OptCategory[NN_vpabsw] = 1;               // Packed Absolute Value Word
OptCategory[NN_vpackssdw] = 1;            // Pack with Signed Saturation (Dword->Word)
OptCategory[NN_vpacksswb] = 1;            // Pack with Signed Saturation (Word->Byte)
OptCategory[NN_vpackusdw] = 1;            // Pack with Unsigned Saturation
OptCategory[NN_vpackuswb] = 1;            // Pack with Unsigned Saturation (Word->Byte)
OptCategory[NN_vpaddb] = 1;               // Packed Add Byte
OptCategory[NN_vpaddd] = 1;               // Packed Add Dword
OptCategory[NN_vpaddq] = 1;               // Add Packed Quadword Integers
OptCategory[NN_vpaddsb] = 1;              // Packed Add with Saturation (Byte)
OptCategory[NN_vpaddsw] = 1;              // Packed Add with Saturation (Word)
OptCategory[NN_vpaddusb] = 1;             // Packed Add Unsigned with Saturation (Byte)
OptCategory[NN_vpaddusw] = 1;             // Packed Add Unsigned with Saturation (Word)
OptCategory[NN_vpaddw] = 1;               // Packed Add Word
OptCategory[NN_vpalignr] = 1;             // Packed Align Right
OptCategory[NN_vpand] = 1;                // Bitwise Logical And
OptCategory[NN_vpandn] = 1;               // Bitwise Logical And Not
OptCategory[NN_vpavgb] = 1;               // Packed Average (Byte)
OptCategory[NN_vpavgw] = 1;               // Packed Average (Word)
OptCategory[NN_vpblendd] = 1;             // Blend Packed Dwords
OptCategory[NN_vpblendvb] = 1;            // Variable Blend Packed Bytes
OptCategory[NN_vpblendw] = 1;             // Blend Packed Words
OptCategory[NN_vpbroadcastb] = 1;         // Broadcast a Byte Integer
OptCategory[NN_vpbroadcastd] = 1;         // Broadcast a Dword Integer
OptCategory[NN_vpbroadcastq] = 1;         // Broadcast a Qword Integer
OptCategory[NN_vpbroadcastw] = 1;         // Broadcast a Word Integer
OptCategory[NN_vpclmulqdq] = 1;           // Carry-Less Multiplication Quadword
OptCategory[NN_vpcmpeqb] = 1;             // Packed Compare for Equal (Byte)
OptCategory[NN_vpcmpeqd] = 1;             // Packed Compare for Equal (Dword)
OptCategory[NN_vpcmpeqq] = 1;             // Compare Packed Qword Data for Equal
OptCategory[NN_vpcmpeqw] = 1;             // Packed Compare for Equal (Word)
OptCategory[NN_vpcmpestri] = 1;           // Packed Compare Explicit Length Strings, Return Index
OptCategory[NN_vpcmpestrm] = 1;           // Packed Compare Explicit Length Strings, Return Mask
OptCategory[NN_vpcmpgtb] = 1;             // Packed Compare for Greater Than (Byte)
OptCategory[NN_vpcmpgtd] = 1;             // Packed Compare for Greater Than (Dword)
OptCategory[NN_vpcmpgtq] = 1;             // Compare Packed Data for Greater Than
OptCategory[NN_vpcmpgtw] = 1;             // Packed Compare for Greater Than (Word)
OptCategory[NN_vpcmpistri] = 1;           // Packed Compare Implicit Length Strings, Return Index
OptCategory[NN_vpcmpistrm] = 1;           // Packed Compare Implicit Length Strings, Return Mask
OptCategory[NN_vperm2f128] = 1;           // Permute Floating-Point Values
OptCategory[NN_vperm2i128] = 1;           // Permute Integer Values
OptCategory[NN_vpermd] = 1;               // Full Doublewords Element Permutation
OptCategory[NN_vpermilpd] = 1;            // Permute Double-Precision Floating-Point Values
OptCategory[NN_vpermilps] = 1;            // Permute Single-Precision Floating-Point Values
OptCategory[NN_vpermpd] = 1;              // Permute Double-Precision Floating-Point Elements
OptCategory[NN_vpermps] = 1;              // Permute Single-Precision Floating-Point Elements
OptCategory[NN_vpermq] = 1;               // Qwords Element Permutation
OptCategory[NN_vpextrb] = 1;              // Extract Byte
OptCategory[NN_vpextrd] = 1;              // Extract Dword
OptCategory[NN_vpextrq] = 1;              // Extract Qword
OptCategory[NN_vpextrw] = 1;              // Extract Word
OptCategory[NN_vpgatherdd] = 1;           // Gather Packed Dword Values Using Signed Dword Indices
OptCategory[NN_vpgatherdq] = 1;           // Gather Packed Qword Values Using Signed Dword Indices
OptCategory[NN_vpgatherqd] = 1;           // Gather Packed Dword Values Using Signed Qword Indices
OptCategory[NN_vpgatherqq] = 1;           // Gather Packed Qword Values Using Signed Qword Indices
OptCategory[NN_vphaddd] = 1;              // Packed Horizontal Add Doubleword
OptCategory[NN_vphaddsw] = 1;          // Packed Horizontal Add and Saturate
OptCategory[NN_vphaddw] = 1;           // Packed Horizontal Add Word
OptCategory[NN_vphminposuw] = 1;       // Packed Horizontal Word Minimum
OptCategory[NN_vphsubd] = 1;           // Packed Horizontal Subtract Doubleword
OptCategory[NN_vphsubsw] = 1;          // Packed Horizontal Subtract and Saturate
OptCategory[NN_vphsubw] = 1;           // Packed Horizontal Subtract Word
OptCategory[NN_vpinsrb] = 1;           // Insert Byte
OptCategory[NN_vpinsrd] = 1;           // Insert Dword
OptCategory[NN_vpinsrq] = 1;           // Insert Qword
OptCategory[NN_vpinsrw] = 1;           // Insert Word
OptCategory[NN_vpmaddubsw] = 1;        // Multiply and Add Packed Signed and Unsigned Bytes
OptCategory[NN_vpmaddwd] = 1;          // Packed Multiply and Add
OptCategory[NN_vpmaskmovd] = 1;        // Conditionally Store Dword Values Using Mask
OptCategory[NN_vpmaskmovq] = 1;        // Conditionally Store Qword Values Using Mask
OptCategory[NN_vpmaxsb] = 1;           // Maximum of Packed Signed Byte Integers
OptCategory[NN_vpmaxsd] = 1;           // Maximum of Packed Signed Dword Integers
OptCategory[NN_vpmaxsw] = 1;           // Packed Signed Integer Word Maximum
OptCategory[NN_vpmaxub] = 1;           // Packed Unsigned Integer Byte Maximum
OptCategory[NN_vpmaxud] = 1;           // Maximum of Packed Unsigned Dword Integers
OptCategory[NN_vpmaxuw] = 1;           // Maximum of Packed Word Integers
OptCategory[NN_vpminsb] = 1;           // Minimum of Packed Signed Byte Integers
OptCategory[NN_vpminsd] = 1;           // Minimum of Packed Signed Dword Integers
OptCategory[NN_vpminsw] = 1;           // Packed Signed Integer Word Minimum
OptCategory[NN_vpminub] = 1;           // Packed Unsigned Integer Byte Minimum
OptCategory[NN_vpminud] = 1;           // Minimum of Packed Unsigned Dword Integers
OptCategory[NN_vpminuw] = 1;           // Minimum of Packed Word Integers
OptCategory[NN_vpmovmskb] = 1;         // Move Byte Mask to Integer
OptCategory[NN_vpmovsxbd] = 1;         // Packed Move with Sign Extend
OptCategory[NN_vpmovsxbq] = 1;         // Packed Move with Sign Extend
OptCategory[NN_vpmovsxbw] = 1;         // Packed Move with Sign Extend
OptCategory[NN_vpmovsxdq] = 1;         // Packed Move with Sign Extend
OptCategory[NN_vpmovsxwd] = 1;         // Packed Move with Sign Extend
OptCategory[NN_vpmovsxwq] = 1;         // Packed Move with Sign Extend
OptCategory[NN_vpmovzxbd] = 1;         // Packed Move with Zero Extend
OptCategory[NN_vpmovzxbq] = 1;         // Packed Move with Zero Extend
OptCategory[NN_vpmovzxbw] = 1;         // Packed Move with Zero Extend
OptCategory[NN_vpmovzxdq] = 1;         // Packed Move with Zero Extend
OptCategory[NN_vpmovzxwd] = 1;         // Packed Move with Zero Extend
OptCategory[NN_vpmovzxwq] = 1;         // Packed Move with Zero Extend
OptCategory[NN_vpmuldq] = 1;           // Multiply Packed Signed Dword Integers
OptCategory[NN_vpmulhrsw] = 1;         // Packed Multiply High with Round and Scale
OptCategory[NN_vpmulhuw] = 1;          // Packed Multiply High Unsigned
OptCategory[NN_vpmulhw] = 1;           // Packed Multiply High
OptCategory[NN_vpmulld] = 1;           // Multiply Packed Signed Dword Integers and Store Low Result
OptCategory[NN_vpmullw] = 1;           // Packed Multiply Low
OptCategory[NN_vpmuludq] = 1;          // Multiply Packed Unsigned Doubleword Integers
OptCategory[NN_vpor] = 1;              // Bitwise Logical Or
OptCategory[NN_vpsadbw] = 1;           // Packed Sum of Absolute Differences
OptCategory[NN_vpshufb] = 1;           // Packed Shuffle Bytes
OptCategory[NN_vpshufd] = 1;           // Shuffle Packed Doublewords
OptCategory[NN_vpshufhw] = 1;          // Shuffle Packed High Words
OptCategory[NN_vpshuflw] = 1;          // Shuffle Packed Low Words
OptCategory[NN_vpsignb] = 1;           // Packed SIGN Byte
OptCategory[NN_vpsignd] = 1;           // Packed SIGN Doubleword
OptCategory[NN_vpsignw] = 1;           // Packed SIGN Word
OptCategory[NN_vpslld] = 1;            // Packed Shift Left Logical (Dword)
OptCategory[NN_vpslldq] = 1;           // Shift Double Quadword Left Logical
OptCategory[NN_vpsllq] = 1;            // Packed Shift Left Logical (Qword)
OptCategory[NN_vpsllvd] = 1;           // Variable Bit Shift Left Logical (Dword)
OptCategory[NN_vpsllvq] = 1;           // Variable Bit Shift Left Logical (Qword)
OptCategory[NN_vpsllw] = 1;            // Packed Shift Left Logical (Word)
OptCategory[NN_vpsrad] = 1;            // Packed Shift Right Arithmetic (Dword)
OptCategory[NN_vpsravd] = 1;           // Variable Bit Shift Right Arithmetic
OptCategory[NN_vpsraw] = 1;            // Packed Shift Right Arithmetic (Word)
OptCategory[NN_vpsrld] = 1;            // Packed Shift Right Logical (Dword)
OptCategory[NN_vpsrldq] = 1;           // Shift Double Quadword Right Logical (Qword)
OptCategory[NN_vpsrlq] = 1;            // Packed Shift Right Logical (Qword)
OptCategory[NN_vpsrlvd] = 1;           // Variable Bit Shift Right Logical (Dword)
OptCategory[NN_vpsrlvq] = 1;           // Variable Bit Shift Right Logical (Qword)
OptCategory[NN_vpsrlw] = 1;            // Packed Shift Right Logical (Word)
OptCategory[NN_vpsubb] = 1;            // Packed Subtract Byte
OptCategory[NN_vpsubd] = 1;            // Packed Subtract Dword
OptCategory[NN_vpsubq] = 1;            // Subtract Packed Quadword Integers
OptCategory[NN_vpsubsb] = 1;           // Packed Subtract with Saturation (Byte)
OptCategory[NN_vpsubsw] = 1;           // Packed Subtract with Saturation (Word)
OptCategory[NN_vpsubusb] = 1;          // Packed Subtract Unsigned with Saturation (Byte)
OptCategory[NN_vpsubusw] = 1;          // Packed Subtract Unsigned with Saturation (Word)
OptCategory[NN_vpsubw] = 1;            // Packed Subtract Word
OptCategory[NN_vptest] = 1;            // Logical Compare
OptCategory[NN_vpunpckhbw] = 1;        // Unpack High Packed Data (Byte->Word)
OptCategory[NN_vpunpckhdq] = 1;        // Unpack High Packed Data (Dword->Qword)
OptCategory[NN_vpunpckhqdq] = 1;       // Unpack High Packed Data (Qword->Xmmword)
OptCategory[NN_vpunpckhwd] = 1;        // Unpack High Packed Data (Word->Dword)
OptCategory[NN_vpunpcklbw] = 1;        // Unpack Low Packed Data (Byte->Word)
OptCategory[NN_vpunpckldq] = 1;        // Unpack Low Packed Data (Dword->Qword)
OptCategory[NN_vpunpcklqdq] = 1;       // Unpack Low Packed Data (Qword->Xmmword)
OptCategory[NN_vpunpcklwd] = 1;        // Unpack Low Packed Data (Word->Dword)
OptCategory[NN_vpxor] = 1;             // Bitwise Logical Exclusive Or
OptCategory[NN_vrcpps] = 1;            // Packed Single-FP Reciprocal
OptCategory[NN_vrcpss] = 1;            // Scalar Single-FP Reciprocal
OptCategory[NN_vroundpd] = 1;          // Round Packed Double Precision Floating-Point Values
OptCategory[NN_vroundps] = 1;          // Round Packed Single Precision Floating-Point Values
OptCategory[NN_vroundsd] = 1;          // Round Scalar Double Precision Floating-Point Values
OptCategory[NN_vroundss] = 1;          // Round Scalar Single Precision Floating-Point Values
OptCategory[NN_vrsqrtps] = 1;          // Packed Single-FP Square Root Reciprocal
OptCategory[NN_vrsqrtss] = 1;          // Scalar Single-FP Square Root Reciprocal
OptCategory[NN_vshufpd] = 1;           // Shuffle Packed Double-Precision Floating-Point Values
OptCategory[NN_vshufps] = 1;           // Shuffle Single-FP
OptCategory[NN_vsqrtpd] = 1;           // Compute Square Roots of Packed Double-Precision Floating-Point Values
OptCategory[NN_vsqrtps] = 1;           // Packed Single-FP Square Root
OptCategory[NN_vsqrtsd] = 1;           // Compute Square Rootof Scalar Double-Precision Floating-Point Value
OptCategory[NN_vsqrtss] = 1;           // Scalar Single-FP Square Root
OptCategory[NN_vstmxcsr] = 1;          // Store Streaming SIMD Extensions Technology Control/Status Register
OptCategory[NN_vsubpd] = 1;            // Subtract Packed Double-Precision Floating-Point Values
OptCategory[NN_vsubps] = 1;            // Packed Single-FP Subtract
OptCategory[NN_vsubsd] = 1;            // Subtract Scalar Double-Precision Floating-Point Values
OptCategory[NN_vsubss] = 1;            // Scalar Single-FP Subtract
OptCategory[NN_vtestpd] = 1;           // Packed Double-Precision Floating-Point Bit Test
OptCategory[NN_vtestps] = 1;           // Packed Single-Precision Floating-Point Bit Test
OptCategory[NN_vucomisd] = 1;          // Unordered Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
OptCategory[NN_vucomiss] = 1;          // Scalar Unordered Single-FP Compare and Set EFLAGS
OptCategory[NN_vunpckhpd] = 1;         // Unpack and Interleave High Packed Double-Precision Floating-Point Values
OptCategory[NN_vunpckhps] = 1;         // Unpack High Packed Single-FP Data
OptCategory[NN_vunpcklpd] = 1;         // Unpack and Interleave Low Packed Double-Precision Floating-Point Values
OptCategory[NN_vunpcklps] = 1;         // Unpack Low Packed Single-FP Data
OptCategory[NN_vxorpd] = 1;            // Bitwise Logical OR of Double-Precision Floating-Point Values
OptCategory[NN_vxorps] = 1;            // Bitwise Logical XOR for Single-FP Data
OptCategory[NN_vzeroall] = 1;          // Zero All YMM Registers
OptCategory[NN_vzeroupper] = 1;        // Zero Upper Bits of YMM Registers

// Transactional Synchronization Extensions

OptCategory[NN_xabort] = 1;               // Transaction Abort
OptCategory[NN_xbegin] = 1;               // Transaction Begin
OptCategory[NN_xend] = 1;                 // Transaction End
OptCategory[NN_xtest] = 1;                // Test If In Transactional Execution

// Virtual PC synthetic instructions

OptCategory[NN_vmgetinfo] = 1;            // Virtual PC - Get VM Information
OptCategory[NN_vmsetinfo] = 1;            // Virtual PC - Set VM Information
OptCategory[NN_vmdxdsbl] = 1;             // Virtual PC - Disable Direct Execution
OptCategory[NN_vmdxenbl] = 1;             // Virtual PC - Enable Direct Execution
OptCategory[NN_vmcpuid] = 1;              // Virtual PC - Virtualized CPU Information
OptCategory[NN_vmhlt] = 1;                // Virtual PC - Halt
OptCategory[NN_vmsplaf] = 1;              // Virtual PC - Spin Lock Acquisition Failed
OptCategory[NN_vmpushfd] = 1;             // Virtual PC - Push virtualized flags register
OptCategory[NN_vmpopfd] = 1;              // Virtual PC - Pop virtualized flags register
OptCategory[NN_vmcli] = 1;                // Virtual PC - Clear Interrupt Flag
OptCategory[NN_vmsti] = 1;                // Virtual PC - Set Interrupt Flag
OptCategory[NN_vmiretd] = 1;              // Virtual PC - Return From Interrupt
OptCategory[NN_vmsgdt] = 1;               // Virtual PC - Store Global Descriptor Table
OptCategory[NN_vmsidt] = 1;               // Virtual PC - Store Interrupt Descriptor Table
OptCategory[NN_vmsldt] = 1;               // Virtual PC - Store Local Descriptor Table
OptCategory[NN_vmstr] = 1;                // Virtual PC - Store Task Register
OptCategory[NN_vmsdte] = 1;               // Virtual PC - Store to Descriptor Table Entry
OptCategory[NN_vpcext] = 1;               // Virtual PC - ISA extension

#endif // 599 < IDA_SDK_VERSION

OptCategory[NN_last] = 1;

  return;

} // end InitOptCategory()

// Initialize the StackAlteration[] array to define how opcodes
//   adjust the stack pointer.
void InitStackAlteration(void) {
	// Default category is 0; most instructions do not alter the stack pointer.
	(void) memset(StackAlteration, 0, sizeof(StackAlteration));

	// Many arithmetic instructions could alter the stack pointer. We will have to
	//  examine each instruction that performs addition, subtraction, logical AND, etc.,
	//  to determine if the stack pointer was the DEF operand. We cannot use a purely
	//  table driven approach to compute stack pointer alteration. The table is used for
	//  the deterministic cases, e.g. push, pop, call, return. Because of variability on
	//  a few of these instructions, a value of 1 in the table below is a trigger to investigate RTLs
	//  that might or might not alter the stack pointer, e.g. add, subtract, etc., or that might
	//  have operand-dependent effects on the stack pointer.

StackAlteration[NN_add] = 1;                  // Addition; check operands for stack pointer
StackAlteration[NN_adc] = 1;                  // Addition; check operands for stack pointer ; RARE for stack pointer
StackAlteration[NN_and] = 1;                  // Logical AND; check operands for stack pointer
StackAlteration[NN_call] = -((sval_t) STARS_ISA_Bytewidth);   // Call Procedure; -4, but return cancels it to zero
StackAlteration[NN_callfi] = -2 * ((sval_t) STARS_ISA_Bytewidth);              // Indirect Call Far Procedure; -8, but far return cancels it to zero
StackAlteration[NN_callni] = -((sval_t) STARS_ISA_Bytewidth);              // Indirect Call Near Procedure; -4, but return cancels it to zero
StackAlteration[NN_enterw] = 1;              // Make Stack Frame for Procedure Parameters  **
StackAlteration[NN_enter] = 1;               // Make Stack Frame for Procedure Parameters  **
StackAlteration[NN_enterd] = 1;              // Make Stack Frame for Procedure Parameters  **
StackAlteration[NN_enterq] = 1;              // Make Stack Frame for Procedure Parameters  **
StackAlteration[NN_int] = 0;                 // Call to Interrupt Procedure
StackAlteration[NN_into] = 0;                // Call to Interrupt Procedure if Overflow Flag = 1
StackAlteration[NN_int3] = 0;                // Trap to Debugger
StackAlteration[NN_iretw] = 6;               // Interrupt Return
StackAlteration[NN_iret] = 12;                // Interrupt Return
StackAlteration[NN_iretd] = 12;               // Interrupt Return (use32)
StackAlteration[NN_iretq] = 40;               // Interrupt Return (use64)
StackAlteration[NN_lea] = 1;                 // Load Effective Address (can be used for basic arithmetic assignments)
StackAlteration[NN_leavew] = 1;              // High Level Procedure Exit        **
StackAlteration[NN_leave] = 1;               // High Level Procedure Exit        **
StackAlteration[NN_leaved] = 1;              // High Level Procedure Exit        **
StackAlteration[NN_leaveq] = 1;              // High Level Procedure Exit        **
StackAlteration[NN_mov] = 1;                 // Move Data ; could be esp := ebp (deallocate stack frame) or esp := ebx (unknown)
StackAlteration[NN_pop] = 1;                 // Pop a word from the Stack  ; could be 16-bit or 32-bit operand, etc.
StackAlteration[NN_popaw] = 14;               // Pop all General Registers
StackAlteration[NN_popa] = 28;                // Pop all General Registers
StackAlteration[NN_popad] = 28;               // Pop all General Registers (use32)
StackAlteration[NN_popaq] = 56;               // Pop all General Registers (use64)
StackAlteration[NN_popfw] = 2;               // Pop Stack into Flags Register         **
StackAlteration[NN_popf] = 4;                // Pop Stack into Flags Register         **
StackAlteration[NN_popfd] = 4;               // Pop Stack into Eflags Register        **
StackAlteration[NN_popfq] = 8;               // Pop Stack into Rflags Register        **
StackAlteration[NN_push] = 1;                // Push Operand onto the Stack  ; could be 16-bit or 32-bit operand, etc.
StackAlteration[NN_pushaw] = -14;              // Push all General Registers
StackAlteration[NN_pusha] = -28;               // Push all General Registers
StackAlteration[NN_pushad] = -28;              // Push all General Registers (use32)
StackAlteration[NN_pushaq] = -56;              // Push all General Registers (use64)
StackAlteration[NN_pushfw] = -2;              // Push Flags Register onto the Stack
StackAlteration[NN_pushf] = -4;               // Push Flags Register onto the Stack
StackAlteration[NN_pushfd] = -4;              // Push Flags Register onto the Stack (use32)
StackAlteration[NN_pushfq] = -8;              // Push Flags Register onto the Stack (use64)
StackAlteration[NN_retn] = 1;                // Return Near from Procedure (usually 4 bytes)
StackAlteration[NN_retf] = 1;                // Return Far from Procedure (usually 8 bytes)
StackAlteration[NN_sub] = 1;                  // Subtraction; check operands for stack pointer
StackAlteration[NN_sbb] = 1;                  // Subtraction; check operands for stack pointer ; RARE for stack pointer

//
//      486 instructions
//


//
//      Pentium instructions
//


//
//      Pentium Pro instructions
//


//
//      FPP instructions
//


//
//      80387 instructions
//

//
//      Instructions added 28.02.96
//

StackAlteration[NN_loadall] = 0;             // Load the entire CPU state from ES:EDI ?? Cannot find in Intel manuals

//
//      MMX instructions
//


//
//      Undocumented Deschutes processor instructions
//

//      Pentium II instructions

StackAlteration[NN_sysenter] = 0;            // Fast Transition to System Call Entry Point
StackAlteration[NN_sysexit] = 0;             // Fast Transition from System Call Entry Point

//      3DNow! instructions


//      Pentium III instructions


// Pentium III Pseudo instructions

// AMD K7 instructions

// Revisit AMD if we port to it.

// Undocumented FP instructions (thanks to norbert.juffa@adm.com)

// Pentium 4 instructions


// AMD syscall/sysret instructions  NOTE: not AMD, found in Intel manual

StackAlteration[NN_syscall] = 0;             // Low latency system call
StackAlteration[NN_sysret] = 0;              // Return from system call

// AMD64 instructions    NOTE: not AMD, found in Intel manual

// New Pentium instructions (SSE3)


// Missing AMD64 instructions  NOTE: also found in Intel manual

// SSE3 instructions

// SSSE3 instructions


// VMX instructions

#if 599 < IDA_SDK_VERSION

// Added with x86-64

// Geode LX 3DNow! extensions

// SSE2 pseudoinstructions


// SSSE4.1 instructions


// SSSE4.2 instructions

// AMD SSE4a instructions

// xsave/xrstor instructions

// Intel Safer Mode Extensions (SMX)

// AMD-V Virtualization ISA Extension

// VMX+ instructions

// Intel Atom instructions

// Intel AES instructions

// Carryless multiplication

// Returns modified by operand size prefixes

StackAlteration[NN_retnw] = 1;               // Return Near from Procedure (use16)
StackAlteration[NN_retnd] = 1;               // Return Near from Procedure (use32)
StackAlteration[NN_retnq] = 1;               // Return Near from Procedure (use64)
StackAlteration[NN_retfw] = 1;               // Return Far from Procedure (use16)
StackAlteration[NN_retfd] = 1;               // Return Far from Procedure (use32)
StackAlteration[NN_retfq] = 1;               // Return Far from Procedure (use64)

// RDRAND support

// new GPR instructions