SMPInstr.cpp

		case NN_psrlq:               // Packed Shift Right Logical (Qword)
		case NN_psubb:               // Packed Subtract Byte
		case NN_psubw:               // Packed Subtract Word
		case NN_psubd:               // Packed Subtract Dword
		case NN_psubsb:              // Packed Subtract with Saturation (Byte)
		case NN_psubsw:              // Packed Subtract with Saturation (Word)
		case NN_psubusb:             // Packed Subtract Unsigned with Saturation (Byte)
		case NN_psubusw:             // Packed Subtract Unsigned with Saturation (Word)
		case NN_punpckhbw:           // Unpack High Packed Data (Byte->Word)
		case NN_punpckhwd:           // Unpack High Packed Data (Word->Dword)
		case NN_punpckhdq:           // Unpack High Packed Data (Dword->Qword)
		case NN_punpcklbw:           // Unpack Low Packed Data (Byte->Word)
		case NN_punpcklwd:           // Unpack Low Packed Data (Word->Dword)
		case NN_punpckldq:           // Unpack Low Packed Data (Dword->Qword)
		case NN_pxor:                // Bitwise Logical Exclusive Or

		//
		//      Undocumented Deschutes processor instructions
		//

		case NN_fxsave:              // Fast save FP context
		case NN_fxrstor:             // Fast restore FP context

		//      Pentium II instructions

		case NN_sysenter:            // Fast Transition to System Call Entry Point
		case NN_sysexit:             // Fast Transition from System Call Entry Point

		//      3DNow! instructions

		case NN_pavgusb:             // Packed 8-bit Unsigned Integer Averaging
		case NN_pfadd:               // Packed Floating-Point Addition
		case NN_pfsub:               // Packed Floating-Point Subtraction
		case NN_pfsubr:              // Packed Floating-Point Reverse Subtraction
		case NN_pfacc:               // Packed Floating-Point Accumulate
		case NN_pfcmpge:             // Packed Floating-Point Comparison: Greater or Equal
		case NN_pfcmpgt:             // Packed Floating-Point Comparison: Greater
		case NN_pfcmpeq:             // Packed Floating-Point Comparison: Equal
		case NN_pfmin:               // Packed Floating-Point Minimum
		case NN_pfmax:               // Packed Floating-Point Maximum
		case NN_pi2fd:               // Packed 32-bit Integer to Floating-Point
		case NN_pf2id:               // Packed Floating-Point to 32-bit Integer
		case NN_pfrcp:               // Packed Floating-Point Reciprocal Approximation
		case NN_pfrsqrt:             // Packed Floating-Point Reciprocal Square Root Approximation
		case NN_pfmul:               // Packed Floating-Point Multiplication
		case NN_pfrcpit1:            // Packed Floating-Point Reciprocal First Iteration Step
		case NN_pfrsqit1:            // Packed Floating-Point Reciprocal Square Root First Iteration Step
		case NN_pfrcpit2:            // Packed Floating-Point Reciprocal Second Iteration Step
		case NN_pmulhrw:             // Packed Floating-Point 16-bit Integer Multiply with rounding
		case NN_femms:               // Faster entry/exit of the MMX or floating-point state
		case NN_prefetch:            // Prefetch at least a 32-byte line into L1 data cache
		case NN_prefetchw:           // Prefetch processor cache line into L1 data cache (mark as modified)


		//      Pentium III instructions

		case NN_addps:               // Packed Single-FP Add
		case NN_addss:               // Scalar Single-FP Add
		case NN_andnps:              // Bitwise Logical And Not for Single-FP
		case NN_andps:               // Bitwise Logical And for Single-FP
		case NN_cmpps:               // Packed Single-FP Compare
		case NN_cmpss:               // Scalar Single-FP Compare
		case NN_comiss:              // Scalar Ordered Single-FP Compare and Set EFLAGS
		case NN_cvtpi2ps:            // Packed signed INT32 to Packed Single-FP conversion
		case NN_cvtps2pi:            // Packed Single-FP to Packed INT32 conversion
		case NN_cvtsi2ss:            // Scalar signed INT32 to Single-FP conversion
		case NN_cvtss2si:            // Scalar Single-FP to signed INT32 conversion
		case NN_cvttps2pi:           // Packed Single-FP to Packed INT32 conversion (truncate)
		case NN_cvttss2si:           // Scalar Single-FP to signed INT32 conversion (truncate)
		case NN_divps:               // Packed Single-FP Divide
		case NN_divss:               // Scalar Single-FP Divide
		case NN_ldmxcsr:             // Load Streaming SIMD Extensions Technology Control/Status Register
		case NN_maxps:               // Packed Single-FP Maximum
		case NN_maxss:               // Scalar Single-FP Maximum
		case NN_minps:               // Packed Single-FP Minimum
		case NN_minss:               // Scalar Single-FP Minimum
		case NN_movaps:              // Move Aligned Four Packed Single-FP
		case NN_movhlps:             // Move High to Low Packed Single-FP
		case NN_movhps:              // Move High Packed Single-FP
		case NN_movlhps:             // Move Low to High Packed Single-FP
		case NN_movlps:              // Move Low Packed Single-FP
		case NN_movmskps:            // Move Mask to Register
		case NN_movss:               // Move Scalar Single-FP
		case NN_movups:              // Move Unaligned Four Packed Single-FP
		case NN_mulps:               // Packed Single-FP Multiply
		case NN_mulss:               // Scalar Single-FP Multiply
		case NN_orps:                // Bitwise Logical OR for Single-FP Data
		case NN_rcpps:               // Packed Single-FP Reciprocal
		case NN_rcpss:               // Scalar Single-FP Reciprocal
		case NN_rsqrtps:             // Packed Single-FP Square Root Reciprocal
		case NN_rsqrtss:             // Scalar Single-FP Square Root Reciprocal
		case NN_shufps:              // Shuffle Single-FP
		case NN_sqrtps:              // Packed Single-FP Square Root
		case NN_sqrtss:              // Scalar Single-FP Square Root
		case NN_stmxcsr:             // Store Streaming SIMD Extensions Technology Control/Status Register
		case NN_subps:               // Packed Single-FP Subtract
		case NN_subss:               // Scalar Single-FP Subtract
		case NN_ucomiss:             // Scalar Unordered Single-FP Compare and Set EFLAGS
		case NN_unpckhps:            // Unpack High Packed Single-FP Data
		case NN_unpcklps:            // Unpack Low Packed Single-FP Data
		case NN_xorps:               // Bitwise Logical XOR for Single-FP Data
		case NN_pavgb:               // Packed Average (Byte)
		case NN_pavgw:               // Packed Average (Word)
		case NN_pextrw:              // Extract Word
		case NN_pinsrw:              // Insert Word
		case NN_pmaxsw:              // Packed Signed Integer Word Maximum
		case NN_pmaxub:              // Packed Unsigned Integer Byte Maximum
		case NN_pminsw:              // Packed Signed Integer Word Minimum
		case NN_pminub:              // Packed Unsigned Integer Byte Minimum
		case NN_pmovmskb:            // Move Byte Mask to Integer
		case NN_pmulhuw:             // Packed Multiply High Unsigned
		case NN_psadbw:              // Packed Sum of Absolute Differences
		case NN_pshufw:              // Packed Shuffle Word
		case NN_maskmovq:            // Byte Mask write
		case NN_movntps:             // Move Aligned Four Packed Single-FP Non Temporal
		case NN_movntq:              // Move 64 Bits Non Temporal
		case NN_prefetcht0:          // Prefetch to all cache levels
		case NN_prefetcht1:          // Prefetch to all cache levels
		case NN_prefetcht2:          // Prefetch to L2 cache
		case NN_prefetchnta:         // Prefetch to L1 cache
		case NN_sfence:              // Store Fence

		// Pentium III Pseudo instructions

		case NN_cmpeqps:             // Packed Single-FP Compare EQ
		case NN_cmpltps:             // Packed Single-FP Compare LT
		case NN_cmpleps:             // Packed Single-FP Compare LE
		case NN_cmpunordps:          // Packed Single-FP Compare UNORD
		case NN_cmpneqps:            // Packed Single-FP Compare NOT EQ
		case NN_cmpnltps:            // Packed Single-FP Compare NOT LT
		case NN_cmpnleps:            // Packed Single-FP Compare NOT LE
		case NN_cmpordps:            // Packed Single-FP Compare ORDERED
		case NN_cmpeqss:             // Scalar Single-FP Compare EQ
		case NN_cmpltss:             // Scalar Single-FP Compare LT
		case NN_cmpless:             // Scalar Single-FP Compare LE
		case NN_cmpunordss:          // Scalar Single-FP Compare UNORD
		case NN_cmpneqss:            // Scalar Single-FP Compare NOT EQ
		case NN_cmpnltss:            // Scalar Single-FP Compare NOT LT
		case NN_cmpnless:            // Scalar Single-FP Compare NOT LE
		case NN_cmpordss:            // Scalar Single-FP Compare ORDERED

		// AMD K7 instructions

		case NN_pf2iw:               // Packed Floating-Point to Integer with Sign Extend
		case NN_pfnacc:              // Packed Floating-Point Negative Accumulate
		case NN_pfpnacc:             // Packed Floating-Point Mixed Positive-Negative Accumulate
		case NN_pi2fw:               // Packed 16-bit Integer to Floating-Point
		case NN_pswapd:              // Packed Swap Double Word

		// Undocumented FP instructions (thanks to norbert.juffa@adm.com)

		case NN_fstp1:               // Alias of Store Real and Pop
		case NN_fcom2:               // Alias of Compare Real
		case NN_fcomp3:              // Alias of Compare Real and Pop
		case NN_fxch4:               // Alias of Exchange Registers
		case NN_fcomp5:              // Alias of Compare Real and Pop
		case NN_ffreep:              // Free Register and Pop
		case NN_fxch7:               // Alias of Exchange Registers
		case NN_fstp8:               // Alias of Store Real and Pop
		case NN_fstp9:               // Alias of Store Real and Pop

		// Pentium 4 instructions

		case NN_addpd:               // Add Packed Double-Precision Floating-Point Values
		case NN_addsd:               // Add Scalar Double-Precision Floating-Point Values
		case NN_andnpd:              // Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
		case NN_andpd:               // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
		case NN_clflush:             // Flush Cache Line
		case NN_cmppd:               // Compare Packed Double-Precision Floating-Point Values
		case NN_cmpsd:               // Compare Scalar Double-Precision Floating-Point Values
		case NN_comisd:              // Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
		case NN_cvtdq2pd:            // Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
		case NN_cvtdq2ps:            // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
		case NN_cvtpd2dq:            // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
		case NN_cvtpd2pi:            // Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
		case NN_cvtpd2ps:            // Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
		case NN_cvtpi2pd:            // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
		case NN_cvtps2dq:            // Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
		case NN_cvtps2pd:            // Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
		case NN_cvtsd2si:            // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
		case NN_cvtsd2ss:            // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
		case NN_cvtsi2sd:            // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
		case NN_cvtss2sd:            // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
		case NN_cvttpd2dq:           // Convert With Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
		case NN_cvttpd2pi:           // Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
		case NN_cvttps2dq:           // Convert With Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
		case NN_cvttsd2si:           // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
		case NN_divpd:               // Divide Packed Double-Precision Floating-Point Values
		case NN_divsd:               // Divide Scalar Double-Precision Floating-Point Values
		case NN_lfence:              // Load Fence
		case NN_maskmovdqu:          // Store Selected Bytes of Double Quadword
		case NN_maxpd:               // Return Maximum Packed Double-Precision Floating-Point Values
		case NN_maxsd:               // Return Maximum Scalar Double-Precision Floating-Point Value
		case NN_mfence:              // Memory Fence
		case NN_minpd:               // Return Minimum Packed Double-Precision Floating-Point Values
		case NN_minsd:               // Return Minimum Scalar Double-Precision Floating-Point Value
		case NN_movapd:              // Move Aligned Packed Double-Precision Floating-Point Values
		case NN_movdq2q:             // Move Quadword from XMM to MMX Register
		case NN_movdqa:              // Move Aligned Double Quadword
		case NN_movdqu:              // Move Unaligned Double Quadword
		case NN_movhpd:              // Move High Packed Double-Precision Floating-Point Values
		case NN_movlpd:              // Move Low Packed Double-Precision Floating-Point Values
		case NN_movmskpd:            // Extract Packed Double-Precision Floating-Point Sign Mask
		case NN_movntdq:             // Store Double Quadword Using Non-Temporal Hint
		case NN_movnti:              // Store Doubleword Using Non-Temporal Hint
		case NN_movntpd:             // Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
		case NN_movq2dq:             // Move Quadword from MMX to XMM Register
		case NN_movsd:               // Move Scalar Double-Precision Floating-Point Values
		case NN_movupd:              // Move Unaligned Packed Double-Precision Floating-Point Values
		case NN_mulpd:               // Multiply Packed Double-Precision Floating-Point Values
		case NN_mulsd:               // Multiply Scalar Double-Precision Floating-Point Values
		case NN_orpd:                // Bitwise Logical OR of Double-Precision Floating-Point Values
		case NN_paddq:               // Add Packed Quadword Integers
		case NN_pause:               // Spin Loop Hint
		case NN_pmuludq:             // Multiply Packed Unsigned Doubleword Integers
		case NN_pshufd:              // Shuffle Packed Doublewords
		case NN_pshufhw:             // Shuffle Packed High Words
		case NN_pshuflw:             // Shuffle Packed Low Words
		case NN_pslldq:              // Shift Double Quadword Left Logical
		case NN_psrldq:              // Shift Double Quadword Right Logical
		case NN_psubq:               // Subtract Packed Quadword Integers
		case NN_punpckhqdq:          // Unpack High Data
		case NN_punpcklqdq:          // Unpack Low Data
		case NN_shufpd:              // Shuffle Packed Double-Precision Floating-Point Values
		case NN_sqrtpd:              // Compute Square Roots of Packed Double-Precision Floating-Point Values
		case NN_sqrtsd:              // Compute Square Rootof Scalar Double-Precision Floating-Point Value
		case NN_subpd:               // Subtract Packed Double-Precision Floating-Point Values
		case NN_subsd:               // Subtract Scalar Double-Precision Floating-Point Values
		case NN_ucomisd:             // Unordered Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
		case NN_unpckhpd:            // Unpack and Interleave High Packed Double-Precision Floating-Point Values
		case NN_unpcklpd:            // Unpack and Interleave Low Packed Double-Precision Floating-Point Values
		case NN_xorpd:               // Bitwise Logical OR of Double-Precision Floating-Point Values

		// AMD syscall/sysret instructions

		case NN_syscall:             // Low latency system call
		case NN_sysret:              // Return from system call

		// AMD64 instructions

		case NN_swapgs:              // Exchange GS base with KernelGSBase MSR

		// New Pentium instructions (SSE3)

		case NN_movddup:             // Move One Double-FP and Duplicate
		case NN_movshdup:            // Move Packed Single-FP High and Duplicate
		case NN_movsldup:            // Move Packed Single-FP Low and Duplicate

		// Missing AMD64 instructions

		case NN_movsxd:              // Move with Sign-Extend Doubleword
		case NN_cmpxchg16b:          // Compare and Exchange 16 Bytes

		// SSE3 instructions

		case NN_addsubpd:            // Add /Sub packed DP FP numbers
		case NN_addsubps:            // Add /Sub packed SP FP numbers
		case NN_haddpd:              // Add horizontally packed DP FP numbers
		case NN_haddps:              // Add horizontally packed SP FP numbers
		case NN_hsubpd:              // Sub horizontally packed DP FP numbers
		case NN_hsubps:              // Sub horizontally packed SP FP numbers
		case NN_monitor:             // Set up a linear address range to be monitored by hardware
		case NN_mwait:               // Wait until write-back store performed within the range specified by the MONITOR instruction
		case NN_fisttp:              // Store ST in intXX (chop) and pop
		case NN_lddqu:               // Load unaligned integer 128-bit

		// SSSE3 instructions

		case NN_psignb:              // Packed SIGN Byte
		case NN_psignw:              // Packed SIGN Word
		case NN_psignd:              // Packed SIGN Doubleword
		case NN_pshufb:              // Packed Shuffle Bytes
		case NN_pmulhrsw:            // Packed Multiply High with Round and Scale
		case NN_pmaddubsw:           // Multiply and Add Packed Signed and Unsigned Bytes
		case NN_phsubsw:             // Packed Horizontal Subtract and Saturate
		case NN_phaddsw:             // Packed Horizontal Add and Saturate
		case NN_phaddw:              // Packed Horizontal Add Word
		case NN_phaddd:              // Packed Horizontal Add Doubleword
		case NN_phsubw:              // Packed Horizontal Subtract Word
		case NN_phsubd:              // Packed Horizontal Subtract Doubleword
		case NN_palignr:             // Packed Align Right
		case NN_pabsb:               // Packed Absolute Value Byte
		case NN_pabsw:               // Packed Absolute Value Word
		case NN_pabsd:               // Packed Absolute Value Doubleword

		// VMX instructions

		case NN_vmcall:              // Call to VM Monitor
		case NN_vmclear:             // Clear Virtual Machine Control Structure
		case NN_vmlaunch:            // Launch Virtual Machine
		case NN_vmresume:            // Resume Virtual Machine
		case NN_vmptrld:             // Load Pointer to Virtual Machine Control Structure
		case NN_vmptrst:             // Store Pointer to Virtual Machine Control Structure
		case NN_vmread:              // Read Field from Virtual Machine Control Structure
		case NN_vmwrite:             // Write Field from Virtual Machine Control Structure
		case NN_vmxoff:              // Leave VMX Operation
		case NN_vmxon:               // Enter VMX Operation
			return false;
			break;

		default:
			msg("ERROR: Unknown instruction opcode at %x : %s\n", this->GetAddr(),
				this->GetDisasm());
			break;
	} // end switch on opcode
	return true;
} // end SMPInstr::BuildRTL()

// Iterate through all reg transfers and call SyncRTLDefUse for each.
void SMPInstr::SyncAllRTs(void) {
	for (size_t index = 0; index < this->RTL.GetCount(); ++index) {
		this->SyncRTLDefUse(this->RTL.GetRT(index));
	}
	return;
} // end of SMPInstr:SyncAllRTs()

// Ensure that each operand of the RTL is found in the appropriate DEF or USE list.
void SMPInstr::SyncRTLDefUse(SMPRegTransfer *CurrRT) {
	// The Guard expression and ExtraKills are almost never represented in the DEF and USE
	//  lists. When they are, they are added in MDFixupDefUseLists(), so we ignore them here.

	// The only DEFs should come from left operands of SMP_ASSIGN operators, i.e. the effects
	//  of register transfers.
	op_t LeftOp, RightOp;
	set<DefOrUse, LessDefUse>::iterator CurrDef, CurrUse;
	LeftOp = CurrRT->GetLeftOperand();
	if (SMP_ASSIGN == CurrRT->GetOperator()) {
		assert(o_void != LeftOp.type);
		assert(o_imm != LeftOp.type);
		CurrDef = this->Defs.FindRef(LeftOp);
		if (CurrDef == this->GetLastDef() && !LeftOp.is_reg(R_ip)) {
			msg("WARNING: DEF not found for SMP_ASSIGN in %s ; added\n", this->GetDisasm());
			this->Defs.SetRef(LeftOp, CurrRT->GetOperatorType());
		}
	}
	else { // not SMP_ASSIGN; left operand should be a USE
		if (o_void != LeftOp.type) {
			CurrUse = this->Uses.FindRef(LeftOp);
			if (CurrUse == this->GetLastUse()) {
				msg("WARNING: USE not found for ");
				PrintOperand(LeftOp);
				msg(" in %s ; added\n", this->GetDisasm());
				this->Uses.SetRef(LeftOp);
			}
		}
	}
	if (!CurrRT->HasRightSubTree()) {
		RightOp = CurrRT->GetRightOperand();  // right operand should be a USE
		if (o_void != RightOp.type) {
			CurrUse = this->Uses.FindRef(RightOp);
			if (CurrUse == this->GetLastUse()) {
				msg("WARNING: USE not found for ");
				PrintOperand(RightOp);
				msg(" in %s ; added\n", this->GetDisasm());
				this->Uses.SetRef(RightOp);
			}
		}
	}
	else { // recurse into right subtree
		this->SyncRTLDefUse(CurrRT->GetRightTree());
	}
	return;
} // end of SMPInstr::SyncRTLDefUse()